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How do I use all this?

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Page 1: How do I use all this?. How do I use all this, really?

How do I use all this?

Page 2: How do I use all this?. How do I use all this, really?

How do I use all this, really?

Page 3: How do I use all this?. How do I use all this, really?

How do I use all this, really?– Detailed step-by-step description of a

pipeline verification example

Page 4: How do I use all this?. How do I use all this, really?

Outline

1 Informal Introduction

2 Formal Definitions Reactive Systems

Witnessed Refinement Proofs

Slicing Reactive Systems

Decomposing Refinement Proofs

3 Formal Example: Three-Stage Pipeline

4 Informal Example: Dataflow Processor Array

Page 5: How do I use all this?. How do I use all this, really?

isaRegFile

op

inp

src1src2dest outstall isaOut

isaAlu

Specification: ISA

Page 6: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

isaAlu

load r1 1

xnor r2 r1 r1

store r2

r1 := 1

r2 := 0

out := 0

Notes:

1. Store instruction results in an output

2. Memory hierarchy is not represented

3. Why do we need “stall” ?

Page 7: How do I use all this?. How do I use all this, really?

regFile

op

inp

src1

src2

dst

alu

P1 P2

out out

FETCH EXECUTE WRITE-BACK

Page 8: How do I use all this?. How do I use all this, really?

regFile

op

inp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

Page 9: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

isaAlu

Goal: Establish Pipeline refines ISA

Page 10: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

isaAlu

need for “stall” in ISA

Page 11: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

isaAlu

witnessed refinement

isaRegFile isaAlu

Limitation: State explosion

Page 12: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

isaAlu

Why not decompose

proof?

Page 13: How do I use all this?. How do I use all this, really?

regFile

op

inp

src1

src2

dst

alu

P1 P2

out out

FETCH EXECUTE WRITE-BACK

Page 14: How do I use all this?. How do I use all this, really?

regFile

P2

out out

WRITE-BACK

Page 15: How do I use all this?. How do I use all this, really?

alu

P1 P2

EXECUTE

Page 16: How do I use all this?. How do I use all this, really?

regFile

op

inp

src1

src2

dst

P1

FETCH

Page 17: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

outout

isaAlu

Why not decompose

proof?

opinp

src1

src2

dst

Page 18: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

outout

isaAlu

Why not decompose

proof?

opinp

src1

src2

dst

Page 19: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

res

stall

p2op

p2dst

out

stall

isaAlu

Why not decompose

proof?

Page 20: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dst outstal

lisaOut

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

isaAlu

Decompositon does not work!

Page 21: How do I use all this?. How do I use all this, really?

isaRegFile

op

inp

src1src2dest outstall isaOut

isaAlu

Page 22: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dest outstall isaOut

opr2

res

isaAlu

p2dst

opr1

opr2

res

Page 23: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dst outstal

lisaOut

opr2

resp2dst

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

opr1

opr2

res

“out” proof isaAlu

Page 24: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

outout

isaAlu

opinp

src1

src2

dst

res

“out” proof

Page 25: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

regFile

outout

isaAlu

opinp

src1

src2

dst

res

“out” proof

Page 26: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

regFile

opinp

src1

src2

dst

out

res

stall

p2op

p2dst

out

stall

isaAlu

res

“out” proof

Page 27: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

resp2dst

regFile

op

src1

src2

dst

out

stall

p1op

p1dst

p2op

p2dst

out

stall

“out” proof isaAlu

Page 28: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

resp2dst

regFile

op

src1

src2

dst

out

stall

p1op

p1dst

p2op

p2dst

out

stall

outisaOut

“out” proof isaAlu

Page 29: How do I use all this?. How do I use all this, really?

regFile

P2

out out

WRITE-BACK

Page 30: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dst outstal

lisaOut

opr2

resp2dst

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

opr1

opr2

res

“res” proof isaAlu

Page 31: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dststal

l

opr2

opinp

dst

res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

stall

opr1

opr2

res

“res” proof isaAlu

Page 32: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dststal

l

opr2

opinp

dst

res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

stall

opr1

opr2

res

res resp2dst

“res” proof isaAlu

Page 33: How do I use all this?. How do I use all this, really?

alu

P1 P2

EXECUTE

Page 34: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dst outstal

lisaOut

opr2

resp2dst

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

opr1

opr2

res

“opr1” proof isaAlu

Page 35: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

opr2

resp2dst

regFile

opinp

src1

src2

dst

opr1

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

stall

opr2

res

“opr1” proof isaAlu

Page 36: How do I use all this?. How do I use all this, really?

isaRegFileop

inp

src1src2dststal

l

opr2

resp2dst

regFile

opinp

src1

src2

dst

opr1

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

stall

opr2

res

“opr1” proof

opr1opr1

isaAlu

Page 37: How do I use all this?. How do I use all this, really?

regFile

op

inp

src1

src2

dst

P1

FETCH

Page 38: How do I use all this?. How do I use all this, really?

FETCH

EXECUTE

WRITE-BACK

Page 39: How do I use all this?. How do I use all this, really?

isaRegFile

opr1

op

inp

src1src2dst outstal

lisaOut

opr2

resp2dst

regFile

opinp

src1

src2

dst

out

opr1

opr2res

stall

p1inp

p1op

p1dst

p2op

p2dst

alu

out

stall

opr1

opr2

res

isaAlu

Page 40: How do I use all this?. How do I use all this, really?

But..

Page 41: How do I use all this?. How do I use all this, really?

But.. is this really practical?

Page 42: How do I use all this?. How do I use all this, really?

But.. is this really practical?– Verification of VGI multiprocessor

Page 43: How do I use all this?. How do I use all this, really?

Outline

1 Informal Introduction

2 Formal Definitions Reactive Systems

Witnessed Refinement Proofs

Slicing Reactive Systems

Decomposing Refinement Proofs

3 Formal Example: Three-Stage Pipeline

4 Informal Example: Dataflow Processor Array

Page 44: How do I use all this?. How do I use all this, really?

VGI

• VGI = “Video-Graphics-Image”• Designed by Infopad group at

Berkeley • Purpose: web-based image

processing• Designed using

– VHDL (control) – Schematics (Data path)

Page 45: How do I use all this?. How do I use all this, really?

VGI Architecture

• 16 clusters with 6 processors in each - 4 compute, 1 memory, 1 I/O

• ~30K logic gates per processor• ~800 latches per processor• Pipelined compute processors• Low latency data transfer between

processors - complex control

Page 46: How do I use all this?. How do I use all this, really?

VGI Architecture

Complex handshakepipeline

pipeline pipeline

pipeline

pipeline

Page 47: How do I use all this?. How do I use all this, really?

FIFO buffer

ISA

ISA

ISA ISA

ISA

Complex handshakepipeline

pipeline pipeline

pipeline

pipeline

Page 48: How do I use all this?. How do I use all this, really?

Verification

• Different time scales• Implementation

– two-phase clock– level-sensitive latches – activity on both HI and LO phases of

clk

• Specification – no clk signal

Page 49: How do I use all this?. How do I use all this, really?

S

I

Sample Operator

I’ = Sample I at

Runs of I’ = Runs of I sampled at instances where holds

Page 50: How do I use all this?. How do I use all this, really?

pipeline

pipeline pipeline

pipeline

pipeline

clk

ISA

ISA

ISA ISA

ISA

Page 51: How do I use all this?. How do I use all this, really?

Difficulty - Verification

• Size of the VGI chip – ~800 latches in each compute

processor– 64 compute processors

• Need “divide and conquer”

Page 52: How do I use all this?. How do I use all this, really?

Step 1: Network of Processors to Single Processor

Page 53: How do I use all this?. How do I use all this, really?

pipeline

pipeline pipeline

pipeline

pipeline

clk

ISA

ISA

ISA ISA

ISA

Page 54: How do I use all this?. How do I use all this, really?

pipeline

clk

ISA

Page 55: How do I use all this?. How do I use all this, really?

pipeline

pipeline pipeline

pipeline

pipeline

clk

ISA

ISA

ISA ISA

ISA

Page 56: How do I use all this?. How do I use all this, really?

pipeline

clk

ISA

Page 57: How do I use all this?. How do I use all this, really?

pipeline

pipeline pipeline

pipeline

pipeline

clk

ISA

ISA

ISA ISA

ISA

Page 58: How do I use all this?. How do I use all this, really?

pipeline

pipeline

pipeline

ISA

ISA

ISAISA

ISA

pipeline

pipeline

clk

clk

clk

clkclk

Page 59: How do I use all this?. How do I use all this, really?

Step 2: Single Processor

• Single processor still has ~800 latches• Need “divide-and-conquer” again

ISA

pipeline

clk

Page 60: How do I use all this?. How do I use all this, really?

CommStage

PIPE

ALUGateLevel

REGFILE

ALUSpec

ISA REGFILE

FIFObuffer

OPGEN

Input from upstream processor

Input from upstream processor

clk

Page 61: How do I use all this?. How do I use all this, really?

VGI Results

• All lemmas (exceptALU) checked by Mocha in a few minutes

• 3 bugs in communication control found and fixed

• Abstract definitions crucial - designer insight needed


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