how circuits acquire memory: sequential & clocked circuits....fact: “data flip-flop” or “d...
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How circuits acquire memory: Sequential &
Clocked Circuits.COS 116, Spring 2011Sanjeev Arora
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Midterm
Midterm exam scores
Formula for overall grade: 50% exam + 25% HW + labs, 25% participation
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Recap: Combinational Circuits
← Crossed wires that are not connected are sometimes drawn like this.
No loops allowed (direct or indirect)
Wires: transmit voltage(and hence value)
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Timing Diagram
5V
0VTime
X
5V
0VTime
output
NOT gate
delay
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Recap: Combinational circuit for binary addition?
Want to design a circuit to add any two N-bit integers (say N =64).
25 11001
+29 11101
54 110110
Is the truth table method useful? Ideas?
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Modular design
Have small numberof basic components.
Put them together to achieve desired functionality
Basic principle of modern industrial design; recurring theme in next few lectures.
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1-bit adder
(Carry from previous adder)
Hand in on Mar 22: Truth table, circuit for 1-bit adder.
ak bk
ck1-ADDck+1
sk
Carry bit for next adder.
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Modular Designfor boolean circuits
An N-bit adder using N 1-bit adders(will do Mar 22)
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A Full Adder (from handout)
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Memory
Rest of this lecture:How boolean circuits can have “memory”.
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What do you understand by ‘memory”?
How can you tell that a 1-year old child has it?
Behaviorist’s answer: His/her actions depend upon past events.
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Why combinational circuits have no “memory”
Wires: transmit voltage(and hence value)
Boolean gates connected by wires
Important: no loops allowed
Output is determined by current inputs;no “memory” of past values of the inputs.
Today: Circuits with loops; aka “Sequential Circuits”
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Matt likes Sue but he doesn’t like changing his mind Represent with a circuit:
Matt will go to the party if Sue goes or if he already wanted to go
S
M Is this well-defined?
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Sequential Circuits
Circuits with AND, OR and NOT gates.
Cycles are allowed (ie outputs can feedback into inputs)
Can exhibit “memory”.
Sometimes may have “undefined” values
How to write the “truth table”? Suggestions?
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Enter Rita
Matt will go to the party if Sue goes OR if the following holds: if Rita does not go andhe already wanted to go.
?
M
S
R
MR, S: “control”inputs
What combination of R, S changes M?
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R-S Latch SR
M
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A more convenient form of memory
Fact: “Data Flip-Flop” or “D flip flop”;can be implemented using two R-S flip flops.
No“undefined”outputs ever!
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“Register” with 4 bits of memory
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What controls the “Write” signal?
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The “symphony” inside a computer
Clock
Combinational circuit
Memory
ClockedSequentialCircuit(akaSynchronousCircuits)
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Timing diagram (analog of truth table for sequential circuits)
R S M(t) M(t+1)0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Fill in timing diagram for RS latch and hand in on a piece of paper.
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Clocked Sequential Circuits
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Synchronous Sequential Circuit(aka Clocked Sequential Circuit)
CLOCK
INPUTSCombinational
CircuitMemory
(flip-flops)
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Shorthand
Combinational Circuit
Memory(flip-flops)
CLK
This stands for “lots of wires”(aka “bus”)
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Clock Speeds
Heinrich Hertz1857-94
1974 Intel 8080 2 MHz(Mega = Million)
1981 Original IBM PC 4.77 MHz
1993 Intel Pentium 66 MHz
2005 Pentium 4 3.4 GHz(Giga = Billion)
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What limits clock speed?
Combinational Circuit
Memory(flip-flops)
CLK
Delays in combinational logic (remember the adder). Clock cycle = time needed for circuit value to settle.During 1 clock cycle of Pentium 4, light travels: 4 inches
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Finite State Machines
Read handout (Brian Hayes article) for next time.
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Example: State diagram for automatic door
Closed Open
Detected PersonNo Person Detected
Detected Person
No Person Detected
Finite # of “states”;Transition rules between states
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Next lectures…
FSMs Computer organization: CPUs and RAM Lessons from computer architecture.