Housekeepingteamsend of classExample verilog code (alter)Example altera reportLab Monday: you will be asked to show:-- one or more reports--one or more verilog modules--one or more simulation

Processors (ISA, RTL levels); Instruction cycle; interruptsComputer Processor BasicsISA (Instruction Set Architecture)RTL (Register Transfer Language)

Main references: Peckol, Chapters 1-3Patt and Patel, Introduction to Computing Systems (slides from NC State)

Fig. 01-00

Machine categoriesFSMStack machineTuring machinevon Neumann architectureHarvard architecture

Harvard memory: separation of program, dataprogram data

1. fsm--"finite state machine"--states, input, output; transition from one state to the next is a function of current state or current state + input. Machine does not "remember" where it has been previously--you cannot look back at where you have been.

2 basic types:

Moore machine: output from state machine is in

Mealey machine: output based on state you are in and input

Examples: vending machine, control unit, counter, traffic light.

0

0,1

1

1

START

0

Can be realized by flip-flops and combinational logic (and I/O).

Theory: FSM (( regular languages

B

A

C

Control (fsm)Top

StackPopped Item(from Top)Combinational LogicI/O

2. stack machine--states, input, output, stack (LIFO). We can use the stack to "remember" some past actions.

Examples: parse expressions for grammar; evaluate arithmetic expressions.

Example: to evaluate AB+C* (= (A+B)*C)we perform the operations:

Push A; push B; pop, pop, add and push; push C; pop,pop, multiply and push; output result (end of input string). A simple fsm cannot do general examples of this type of calculation. We need flip-flops, combinational logic, and the stack.

Theory:

stack machine (( context-free languages

stack machines are "more powerful" than fsm's (e.g., using a stack we can write a program to recognize palindromes of the form AnBn,n>0. A fsm would need an infinite number of states to do this task.)

(Actual RAM Hierarchy)

3. Turing machine or "random access machine" or sequential computer--this in turn is more general than the stack machine. It can be realized by flip-flops, combinational logic, and a "random access memory" in which each memory location can be accessed through its unique address:

(solid arrows represent control flow; dotted arrows represent data flow).(Sometimes called a Single Instruction Single Data or SISD machine).

Theory: "UTM": Universal Turing Machine--can execute any algorithm, model any classical computer

Turing machine (( recursively enumerable languages

Two basic configurations:

Von Neumann: store data + program together

Harvard: store data, program in separate memories

CONTROL

(FSM)

I/O

RAM

ALU (comb)

fig_01_05fig_01_05Some processor options(note firmware)DSP (A/D, D/A; high speedvideo, audio, images2. Microcontroller-based system Fig. 1-05 components integrated into one unit)1. Microprocessor-based systemfig_01_06fig_01_07

Instruction Set ArchitectureISA = All of the programmer-visible components and operations of the computermemory organizationaddress space -- how may locations can be addressed?addressibility -- how many bits per location?register sethow many? what size? how are they used?instruction setopcodesdata typesaddressing modesISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).

Example 1:LC-3 (Patt) Overview: Memory and RegistersMemoryaddress space: 216 locations (16-bit addresses)addressability: 16 bits

Registerstemporary storage, accessed in a single machine cycleaccessing memory generally takes longer than a single cycleeight general-purpose registers: R0 - R7each 16 bits widehow many bits to uniquely identify a register?other registersnot directly addressable, but used by (and affected by) instructionsPC (program counter), condition codes

LC-3 Overview: Instruction SetOpcodes15 opcodesOperate instructions: ADD, AND, NOTData movement instructions: LD, LDI, LDR, LEA, ST, STR, STIControl instructions: BR, JSR/JSRR, JMP, RTI, TRAPsome opcodes set/clear condition codes, based on result:N = negative, Z = zero, P = positive (> 0)Data Types16-bit 2s complement integer: (q: how does 2s c arithmetic work?)Addressing ModesHow is the location of an operand specified?non-memory addresses: immediate, registermemory addresses: PC-relative, indirect, base+offset

Example: NOT (Register)Note: Src and Dst could be the same register.

Example: ADD/AND (Register)this zero means register mode

fig_01_08fig_01_08DATA: DATA TYPESNUMERIC--Unsigned integer--Signed integer (2s complement, sign-magnitude, fixed point, etc.)--Floating point:3 components:signexponentmantissaNONNUMERIC--address--characterQ: what common data type is not named? Is it missing?

InstructionsISA levelInstruction coding:HLL (high level language, C, C++ , e.g.) assembly language (ISA) machine language(can work at any level; high level allows faster but less efficient coding)IEEE Standard 694-1985IEEE standard for microprocessor assembly languageused for examples in text

Instruction coding:Fields: operator, operands (type of addressing)Example: 32 bits3 bits: opcode2 bits: address mode (e.g. direct, indirect, indexed, immediate)27 bits: for addressing operand (s)Expanding opcode (example):000-110xxxxxxx: 2 operands1110xxxxxx: 1 operand 1111xxxxxx: no operand (e.g., HALT)operator addr mode operand(s)

fig_01_13fig_01_13fig_01_14fig_01_15Example instruction formats

fig_01_42fig_01_42Typical ALU andregisters

fig_01_16fig_01_16Data movement instructions: source / destination

fig_01_12fig_01_12Addressing modes:Immediate: MOVE A, #BH;Direct:MOVE OPR1, OPR2;Indirect:MOVE OPR1, *myVarPtr;MOVE *OPR1, *OPR1;MOVE *OPR1, **yPtr; Register direct:MOVE Reg1, Reg2;Register indirect:MOVE Reg1, *Reg2;Indexed (loops):MOVE Reg1, OPR2[REG2];PC relative (loops,e.g.; offset can be negative):ADD PC, [Reg1];Example: what is the difference between Y, *Y, **YIndirect addressingmyVarPtr holds address or myVar

fig_01_21fig_01_21Addressing examples:

fig_01_22fig_01_22

fig_01_23fig_01_23

fig_01_24fig_01_24

fig_01_25Control instructionsControl can be:sequential (default)loop (pre or posttest)branch:go toconditional (if, if-else,, case, branch on condition)procedure or function call[interrupt or exception]change in control flow, e.g., I/O device readyUnusual event, e.g., overflow or undefined instruction

fig_01_31fig_01_31Example of conditional statements: C / assembly language:fig_01_32

fig_01_34fig_01_34Looping: examplefig_01_35

fig_01_36fig_01_36fig_01_37Function or procedure call:Must store return address, pass information back and forth

What are standard parameter passing methods?

fig_01_39fig_01_39Stack: common way to handle procedure / function calls

Q: what are two alternative methods for handling function / procedure calls? Which methods facilitate recursion?

fig_01_40fig_01_40Function call: example:fig_01_41

LC-3 Data Path

Filled arrow = info to be processed.Unfilled arrow = control signal.

Instruction Processing CycleDecode instructionEvaluate addressFetch operands from memoryExecute operationStore resultFetch instruction from memoryQ: what about interrupts?

fig_01_46fig_01_46Different viewpoint: RTL: register-transfer language level

fig_01_52fig_01_52RTL VIEWfig_01_53

fig_01_57fig_01_57Multiple levels--examples

fig_01_58fig_01_58

table_01_03table_01_03

ALU

MMAIRACCFMDIAIBPCABUSOBUSBBUSALU OUTPUTM: memoryMA: memory address registerMD: memory data registerIR: instruction registerAC: accumulatorCF: carry flagIA, IB: index registers (13 bit)PC: program counterInstruction format: Functionality: 2's complement add, subtract, multiply, and divide, and, or, not jumps (conditional and unconditional), simple subroutine call and returnInterruptsI/OEx 2: Minimal hardware resources high degree of functionalityWhat should instructions be?

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