hot topics and cool ideas in scaled cmos analog … topics and cool ideas in scaled cmos analog...

October 27, 2006 Slide 1

Engineering Insight 2006

Hot Topics and Cool Ideasin Scaled CMOS Analog Design

C. Patrick YueECE, UCSB

Engineering Insights 2006



Our Research FocusHigh-speed analog and RF circuitsDevice modeling, CAD and test methodologyInterface circuits for emerging applications

SS

G1

G2

D1

D2



Outline

Hot topicsDesign & Modeling Methodology

→ Analog / RF / mm-wave standard cellsTest → Scribe-line RF performance screening circuitsCircuit → RF front-end, continuous-time equalizer

Cool ideasHealth monitoring silicon

Summary



Recent Evolution for RF SoC

(S. Mehta, et al. ISSCC 2005.)0.18-μm CMOS RF + baseband DSP

(D. Su, et al. ISSCC 2002.)0.25-μm CMOS5-GHz RF transceiver

But difficult to migrate towards 0.13-μm or 90-nm…

Lower power, cost and size

RFFront-end

Baseband DSP



Challenges for RF/mm-wave SoC in Scaled CMOS

High mask cost ($0.5M – $1M)Lack of a streamline RF/mm-wave design flowNegative impact of technology scaling

DeviceProcess variationsRF/mm-wave model uncertaintyInterconnect parasitic variations

CircuitLow voltage headroom due to reduced Vdd

Strongly depend on layout

Develop a parasitic-aware RF/mm-wave modeling/design methodology



Overcome RF/mm-wave Modeling Uncertainty

Stand-alone single device model is insufficientAccuracy limited by digital RC extractionRF/mm-wave model layout ≠ actual circuit layout

Model Scalability Model Accuracy

Design Flexibility Design Automation

SubSub--Circuit CellsCircuit Cells

ScalableScalableAnalog/RFAnalog/RF

Leverage the insight to optimal RF/mm-wave device layoutExploit the modularity of RF/mm-wave circuits at the sub-circuit level



A Digital-Like Standard Cell Library for RF Design

Assemble like Lego blocksSimilar to digital standard cell based design flow

Optimized cell libraryDiff pair, cross-coupled, cascodeInductors and varactorsInterconnects

Parameterized cells (P-Cells)SKILL code based

Process independentImport design rules from tech files

Equivalent circuit models



Single-Transistor RF Cell Layout

Gate

Source

Drain

Bulk

Folded multi-finger gateReduce gate resistance

Dummy poly-silicon gateReduce mismatch

Substrate contact ringSubstrate resistanceModeling uncertainty

Highly regular for better manufacturability

Includes dummies in the cell template



Parameterized RF/mm-wave Sub-Circuit Cells

No RC extraction needed within cell boundaryEach cell has an equivalent circuit model including RC

S

G1

G2

D

Mergeddiffusionnode

D1&G2 D2&G1

SSSS

D1 D2

G1 G2

Differential pair Cross-coupled pairCascode devices

G1

G2

S BB

DD

SS

D1&G2

D2&G1BB

SS

D1 D2

G1 G2 BB



Cell Test Structures in 0.13-μm CMOS

5.0 mm

2.5 mmACTIVE & PASSIVEDEVICES INTERCONNECTS



Cell-Based RF Design MethodologySpecifications

System-Level Design

Layout

Layout-Parasitic Extracted (LPE)

Simulation

Circuit-Level Design

Tapeout / Fab / Chip Testing

Final Verification

RF Sub-Circuit CellPlace & RouteSilicon

re-spins

Iterationsbetweenschematic and layout

RF Circuit Synthesis



RF Performance Screening Using Cell-Based LC Oscillator Array

LC oscillators with different loadings as process variation monitoring vehicles in scribe-lineScreening individual parasitic components to identify yield hitters

1 2 3 4 5 6 74

4.5

5

5.5

6

6.5

7

Oscillator Case ID Number

Osc

illat

ion

Freq

uenc

y (G

Hz)

SS @ 110CTT @ 60CFF @ 0C

Oscillation FrequenciesOver PVT Corners



MovingProbe2

5000 μm80 μm

GNDVbias Vtune Vout GND

PMOS VariableResistorInductor BufferVaractor

: Component: I/O Pad

80 μm

VDD800 μm

Zoom in on a single oscillator

Oscillator 1 (800 μm)GND VDDVbias Vtune Vout GND

Oscillator 2 (700 μm)Vout GND VDD

Probe2Probe1

During bench testing

Scribe-Line Oscillator Array Layout and Testing



Outline




Summary



UWB (3−5-GHz) RF Front-End

Integrate the components between antenna and the transceiverKey to cost-effective, small form-factor multi-mode or MIMO systems

LO+

GND

LO-

RF+ GND RF-

IF+

GND

IF-

GND

Vdd

LOdc

RFdc

Vbias

Down-conversionMixer

AntennaSwitch

Wideband LNA



CMOS T/R Switch with LC-tuned Substrate Bias



UWB LNA with On-Chip Transformer Matching Network

Input matching → source degeneration inductor→ wide-band transformer

KRFin

LsLssLpsCp

VDD

Cc

Rload

Lload

M2

M1

RFoutVBIAS

Cd

M3

Operate from 2.8 – 4.8 GHz, draws 6.7 mW from 1.2-V VddNF < 4.7 dB, S21 > 13.7 dB, S11 < − 10.4 dB, S22 < −13.1 dB



A 1-V, 3.3-mW, UWB Mixer (Cell-Based)

Double balanced folded topology PMOS LO switchesBroadband RF chokeDifferential pair, inductor and interconnect sub-circuit cells

LO+

GND

LO-

RF+ GND RF-

IF+

GND

IF-

GND

Vdd

LOdc

RFdc

Vbias

Active chip area : 200μmX500μm

1-V Vdd

LO+

RL

IF+ IF-

LO+LO-

RF+ RF-

L2

RL

Vbias

L1 k12



High-Speed Adaptive Passive Equalizer

Passive filter for low-power operationContinuous-time (frequency domain) compensationNo dependency on recovered clock

PassiveEQ Filter

LimitingAmplifierLPF

output

Adaptive Control Loop

Control voltage: VC

inputZ0

LossyChannel

DifferentialPower

Detector



Tunable Differential Passive Filter

Broadband input and output matchingPMOS in triode region for adjustable resistanceLC components can be low-Q (~3 at 3 GHz)Self-resonance frequency > 30 GHz

Out+In+

In− Out−

VC M0 (450 μ / 0.25 μ)

210 fF

210 fF

44 Ω44 Ω

44 Ω44 Ω

540 pH

540 pH

S

S

G

S

S

G

VC

Z0Z0



Channelattenuation

Combined responsehas 8-dB gain differencebetween dc and 5 GHz

Channel + Equalizer Frequency Response

Equalizerresponse(for 10 Gbps)

10-dB GC



20-Gb/s Eye Diagrams Over CAT-5 CablesEqualizer Input Equalizer Output

2 m (10-dB loss at 10GHz)

5 m (20-dB loss at 10GHz)



Outline




Summary



Interface Circuits for Structural Health Monitoring Devices

Power Transmission Inductors- Near-field magnetic coupling

Active Sensing Patch- Dual sensing and actuation- Surface-mountable- Noninvasive and conformable

Wireless Sensor Interface IC- Actuation and sensing circuits- Multiplexing of senor array- Wireless data transmission- Rectifier for AC to DC power conversion



Implantable Bio-Chip for Communication Prosthesis

Open questions for a wireless power delivery interfaceWhat is the optimal frequency to use?How much power can be transferred wirelessly?



M

Pin POUT

on chip

(MHz)

P out

/Pin

(dB

)

10 102 103 104-55

-45

-35

-25

No TissueWith TissueTheoreticalLimit

Power Transfer vs. Frequency



Operate at self-resonance as a LC-tank(Qtank = 11)

Match Rtank to Rload for max power

2x3 inductor array

Strapped metalsNo skin effectM4 thru RDL

5-μm metal2.5-μm oxide

RDLM8M7M6M5M4

810 μm

SGS Pad

Turns 13Width 9 μmSpacing 5 μm

Ls 167 nHRs 19 ΩCp 3.7 pF

Optimized Wireless Power Delivery Inductor at 200 MHz



SummaryCMOS scaling offers many research opportunity due to paradigm shifts in design, modeling, and test methodologies

Higher integration level is needed for multi-mode/MIMO RF front-ends

Channel equalization become important for >10-Gbps I/Os

Increasing need for wireless data/power interface circuits for emerging applications

hot topics and cool ideas in scaled cmos analog … topics and cool ideas in scaled cmos analog...

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