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Honors project Switched capacitor filter design for mixed signal applications

-12V

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0 0

-12V

-12V

J1BC264A

J2BC264A

J3BC264A

J4BC264A

J5BC264A

J6BC264A

J7BC264A

J8BC264A

J9BC264A

J10BC264A

J11BC264A

J12BC264A

J13BC264A

J14BC264A

J15BC264A

J16BC264A

J17BC264A

J18BC264A

J19BC264A

J20BC264A

C1

10n

C2

10n

C3

50p C450p

C5

50pC650p

C7

50p C850p

C9

31.25pC1031.25p

C11

31.25pC1231.25p

C13

50pC1450p

C15

45.5pC1645.5p

C17

50pC1850p

C19

50pC2050p

C21

50pC2250p

Q1

0 0

0

Q1 0

0

0

0

0

Q1

0

0 0

0

0

Q1

Q1

0

Q1

Q1

Q1

Q2

Q1

Q1 Q1

Q2

Q2

Q2 Q2

V412Vdc

V512Vdc

0

+12V

-12VQ2

Q2

+3

-2

V+4

V-11

OUT1

U1A

TL084

Q2

+5

-6

V+4

V-11

OUT7

U1B

TL084

+10

-9

V+4

V-11

OUT8

U1C

TL084

Q2

VD

B

VD

B

VD

B

VD

B

+12

-13

V+4

V-11

OUT 14

U1D

TL084

Q2 Q2

+12V

+12V

+12V

+12V

-12V

Switch Capacitor Filter Parallel and SeriesLow-passHigh-passBand-passBand-reject-3dB-52dB

1000 10000 100000 1000000 10000000

110

100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

By

Klaus Jørgensen

Napier No. 04007824

Electronic & Communication Engineering

1 May 2006

Supervisor Dr. Mohammad Y. Sharif

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Abstract

This project report presents the theory of Switch Capacitors (SC) technology and its

advantages, disadvantages and different implementations methods. The report provides a

short review, of three State Variable (SV) SC filters from Maxim, National Semiconductors

and Texas Instruments. The guidelines on how to construct a SV filter with Low-pass,

High-pass, Band-pass and Band-reject filter response are provided. Simulations have

been carried out to clarify the theory.

A SV filter has been implemented using SC method. Simulations have been carried out

using OrCAD software development tool and the results have been compared with filters

from Maxim, National Semiconductors and Texas Instruments.

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Table of Contents

1. Introduction......................................................................................................................4 2. Theory .............................................................................................................................5

2.1 Metal Oxide Semiconductor Capacitors .....................................................................5 2.2 Parasitic Capacitors ...................................................................................................6 2.3 Metal Oxide Semiconductor Field Effect Transistors Switches ..................................7 2.4 Resistor by Switch Capacitors ...................................................................................8

2.4.1 Resistor by Switch Capacitors sub conclusion ....................................................8 2.5 Switch Capacitor setup ..............................................................................................9

2.5.1 Switch Capacitor setup sub conclusion .............................................................10 3. Applications ...................................................................................................................11

3.1 Texas Instruments UAF42 .......................................................................................11 3.2 Maxim MAX7490 and MAX7491 ..............................................................................12 3.3 National Semiconductor LMF100.............................................................................13

4. State Variable Filter .......................................................................................................14 4.1 Calculations .............................................................................................................14 4.2 Simulations ..............................................................................................................16

4.2.1 Simulations sub conclusion ...............................................................................19 5. Switch Capacitor Filter...................................................................................................20

5.1 Test of different programs ........................................................................................22 5.1.1 Sub Conclusion .................................................................................................23

5.2 Switch Capacitor Filter parallel & Setup of the PSpice model ..................................24 5.3 Switch Capacitor Filter Series ..................................................................................26 5.4 Switch Capacitor Filter Parallel and Series ..............................................................27

5.4.1 Switch Capacitor Filter Parallel and Series sub conclusion ...............................28 5.5 Switch Capacitor Filter Bilinear ................................................................................29 5.6 Negative Switch Capacitor Trans-resistance Realization.........................................30 5.7 Positive Switch Capacitor Trans-resistance Realization ..........................................31 5.8 Switch Capacitor Filter Conclusion...........................................................................32

6. State Variable Filter with Switch Capacitor ....................................................................33 6.1 State Variable Filter with Parallel or Series Switch Capacitor ..................................33 6.2 State Variable Filter with Parallel and Series Switch Capacitor ...............................37

7. Conclusion.....................................................................................................................39 8. References ....................................................................................................................40 9. Bibliography...................................................................................................................40 10. Appendix......................................................................................................................41

10.1 Project Proposal.....................................................................................................41 10.2 Time Plans .............................................................................................................42 10.3 Derivation of equation ............................................................................................43 10.4 Vpulse in OrCAD....................................................................................................44 10.5 State Variable Filter with Parallel or Series Switch Capacitor ................................45 10.6 State Variable Filter with Parallel and Series Switch Capacitor .............................46

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1. Introduction

A SC filter used in an Integrated Circuit (IC) product, and usually implemented by using

Metal Oxide Semiconductor Field Effect Transistors (MOSFET) and capacitors to simulate

the behavior of a resistor, because the resistors are expensive and not easily controlled,

this means that a circuit can be built without the use of resistors, and this is very useful,

many places in the industry today, because that there is build a lot of IC today and a

resistor use a lot of space in a IC. A MOSFET or a capacitor do not use that much room,

also a resistor in a IC is very dependent of the temperature is very stable or else the value

of the resistor will change, the capacitor value in a IC is much more reliable and the value

of a capacitor can be set very accurately, typically around 0,1% accurate and it can be any

value that is required, mostly in a range from 0,1pF to 100pF, and are generally less costly

than resistors. The sampling clock frequency (fS) in a SC filter usually has to be 50 to 100

times bigger then the cut-off frequency at -3dB (fC) to minimize the effects of time-sampling

and charge-sharing, but the frequency area typically in the range from 100kHz to 2MHz,

therefore the SC filter is particularly useful in the voice and audio frequency area, because

that the clock frequency of the switches must be 50 to 100 times bigger then the signal

frequency, and therefore it is very useful in Digital Signal Processor (DSP) technology

which is often used for voice and audio applications. Figure 1.1 shows how a resistor (R) is

replaced with a capacitor (CS) and a switch MOSFET [1].

Figure 1.1 [1]

C

R

0

Cs

0

C

R

0

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2. Theory

In this chapter the general theory of a SC resistor and the basic ways to construct and

calculate a SC resistor is described along with some of the problems there is by using a

SC resistor.

2.1 Metal Oxide Semiconductor Capacitors

Capacitance voltage measurements of Metal Oxide Semiconductor (MOS) capacitors

provide a wealth of information about the structure, which is of direct interest when one

evaluates an MOS process. Since the MOS structure is simple to fabricate, the technique

is widely used.

To understand capacitance-voltage measurements one must first be familiar with the

frequency dependence of the measurement. This frequency d ependence occurs primarily

in inversion since a certain time is needed to generate the minority carriers in the inversion

layer. Thermal equilibrium is therefore not immediately obtained.

The low frequency or quasi-static measurement maintains thermal equilibrium at all

times. This capacitance is the ratio of the change in charge to the change in gate voltage,

measured while the capacitor is in equilibrium. A typical measurement is performed with

an electrometer, which measures the charge added per unit time as one slowly varies the

applied gate voltage.

The high frequency capacitance is obtained from a small-signal capacitance

measurement at high frequency. The bias voltage on the gate is varied slowly to obtain the

capacitance versus voltage. Under such conditions, one finds that the charge in the

inversion layer does not change from the equilibrium value at the applied dc voltage. The

high frequency capacitance therefore reflects only the charge variation in the depletion

layer and the (rather small) movement of the inversion layer charge [2].

Figure 2.1 [2]

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2.2 Parasitic Capacitors

In MOS technology the capacitor CR has unfortunately some disadvantage, and these are

called parasitic capacitances, these appears because of the closeness between the

connecting terminals, and the small dimensions of the device layers. The capacitor Cp

appears from the capacitances mainly between the terminal connecting metal (a, b), and

the substrate (c). The value of this capacitor is usually around 1% of CR. The capacitor Cb

appears from the capacitances between bottom poly-silicon and the substrate (c), this has

usually a value of 10% of the CR [1].

Figure 2.2 [1]

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2.3 Metal Oxide Semiconductor Field Effect Transistors Switches

The most basic element in the design of a large scale IC is the transistor. The transistors

are made of semiconductor layers, usually a slice, or wafer, from a single crystal of silicon,

a layer of silicon dioxide and a layer of metal. These layers are patterned in a manner

which permits transistors to be formed in the semiconductor material. Silicon dioxide is a

very good insulator, so a very thin layer, typically only a few hundred molecules thick, is

required. The MOSFET transistor has three areas, labeled the source, the gate and the

drain. The area labeled as the gate region is actually a part of the original substrate

material, which is a single crystal of semiconductor material witch usually are silicon, a thin

insulating layer, usually silicon dioxide, and an upper metal layer. Electrical charge, or

current, can flow from the source to the drain depending on the charge applied to the gate

region. The semiconductor material in the source and drain region are a different type of

material than in the region under the gate, so an NPN or PNP type structure exists

between the source and drain region of a MOSFET. The source and drain regions are

quite similar, and are labeled depending on to what they are connected. The source is the

terminal, or node, which acts as the source of charge carriers; charge carriers leave the

source and travel to the drain. In the case of an N channel MOSFET, the source is the

more negative of the terminals; in the case of a P channel device, it is the more positive of

the terminals. The area under the gate oxide is called the channel. Figure 2.3 shows a

simplified diagram of a MOSFET transistor [1].

Figure 2.3 [1]

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2.4 Resistor by Switch Capacitors

In figure 2.4 there is shown a simplified version, on how a capacitor can work as a resistor.

By charting and recharges the capacitor, by using a switch, when CS is connected to

terminal 1, the capacitor is being charged by the voltage sours E1, and when the switch is

connected to terminal 2 the capacitor is recharging on to the voltage sours E2 [1].

SS Cf1

IE2-E1R

×== (2.1)

In practice the switch in figure 2.4 is replaced with two MOSFET, the gates of the

MOSFETs are controlled by two clock pulses that doesn’t overlap each outer, as shown in

figure 2.5. In order to switch the MOSFET on, the gate needs to be set “high” (a few volts),

and in the off stage the gate of the MOSFET is “low” (0 volts).

Figure 2.4 [1]

Figure 2.5 [1]

2.4.1 Resistor by Switch Capacitors sub conclusion

One of reason construct a switch capacitor resistor is because it requires a very small

silicon area to create a very large resistor value, actually the silicon area decreases as the

resistor value increases, if implement a resistant of 10MΩ, a good value of the capacitor

will be in the range of 1pF to 10pF and a sample frequency around 100kHz [1].

10MΩ100k1p1

fC1R

SS

=×

⇒×

= (2.2)

A capacitor of 1pF requires a silicon area around 0.01mm2, where a resistor at 10MΩ

requires a silicone area there is at least 100 times bigger.

Cs

Cs

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2.5 Switch Capacitor setup

There are six different ways to construct a SC, to make it acts as a resistor, three which

use two switches and three which use four switches.

In the SC parallel setup (figure 2.6) the CS

is en parallel with C on the output, and the

size of the equivalent resistor is calculated

in equation 2.3 [1].

SS fC1R×

= (2.3)

Figure 2.6

In the SC series setup (figure 2.7) Cs is

placed in series between the MOSFET A

gate and source, the equation for the size

of the equivalent resistor is the same as

the parallel setup in equation 2.3.

Figure 2.7

The setup of the SC parallel and series

(figure 2.8) is there a capacitor in series

(Cs1) and one in parallel (CS2) these two

capacitors make on equivalent resistor.

( ) SSS f2C1C1R

×+= (2.4)

Figure 2.8

The setup of the SC bilinar (figure 2.9) the

CS is placed between 4 MOSFETs this

means that there always will be two

MOSFETs ON at the same time (A, D)

and (B, C).

SS fC41R××

= (2.5)

Figure 2.9

Input

Cs628p

C10n

0 0

Mos A Mos B

Q1 Q2

Mos A Mos B

Cs

628p

C10n

0

Q2Q1

Input

Mos A Mos B

Cs1

528p

Cs2100p

C10n

0

0

Q2Q1Input

Mos A Mos B

Mos C Mos D

Cs157p

C10n

0

Q2

Q2

Q1

Q1

Input

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In the negative trans-resistance

realization SC setup (figure 2.10) uses

four MOSFETs and the CS is placed in

series. When Q1 is high “1” the CS is

being charts and when Q2 is high “1” CS

is discharging, the equation for CS is the

same as in equation 2.3. Figure 2.10

In the positive trans-resistance realization

SC setup (figure 2.11) uses four

MOSFETs and the CS is placed in series.

When Q2 is high “1” CS transfer the

current from the input on to the capacitor

at the output. When Q1 is high “1” CS is

connected to ground and it is discharging.

The equation for CS is the same as in

equation 2.3. Figure 2.11

2.5.1 Switch Capacitor setup sub conclusion

The SC setups there uses two MOSFETs, has its advantage and disadvantages as well

dos the SC setups there uses four MOSFETs. The advantages of only using two

MOSFETs is that it dose not use that much space in the IC, one of the disadvantage is

that is dos not cancel out the parasitic capacitances there will be in an IC. One of the

advantages of using four MOSFETs is, that is eliminating the parasitic capacitances there

will be in an IC. The disadvantage is that this will take up more space in an IC, which can

be a problem in some cases.

C10n

0

Mos A Mos B

Mos DMos C

Cs

628p

0 0

Q2

Q2

Q1

Q1

Input

Mos A Mos B

Mos C Mos D

0 0

Cs

628p

C10n

0

Input

Q2 Q2

Q1 Q1

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3. Applications

There are several electronic companies’s who creates good SV filters in IC, and some of

them are being investigated in this chapter. Some of the company’s who manufacture SV

filters are National Semiconductor, Maxim, Analog, Texas Instruments and Burr-Brown.

3.1 Texas Instruments UAF42

The UAF42 IC is a universal active filter from Texas Instruments, which can be setup in

many different ways with Low-pass, High-pass and Band-pass filters outputs. It uses a

classical state-variable analog architecture with an inverting amplifier and two integrators.

The last opamp in figure 3.1 can be used to make the Band-reject filter with a summing of

the Low-pass and High-pass outputs. The integrators include on-chip 1nF capacitors

trimmed to 0.5%. This solves one of the most difficult problems of active filter design

obtaining tight tolerance, Low-loss capacitors, and the slew rate of the UAF42 is only

10V/ms. the open-loop voltage gain is typical 126dB at a supply voltage of ±10V and a RL

at 2kΩ, the maximum value of Q is 400, the gain bandwidth is 4MHz [3].

Figure 3.1 [3]

Figure 3.2 shows a SV filter with a Low-pass, High-pass and Band-pass filter outputs, the

external resistors can be set by the user to what the demands are for the SV filter, RF1 and

RF2 determine the centre frequency, RG determine the gain of the SV filter, RQ determine

the Q value of the SV filter.

Figure 3.2 [3]

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3.2 Maxim MAX7490 and MAX7491

The MAX7490/MAX7491 IC’s from Maxim consist of two equal 2nd-order SC building

blocks, with Rail-to-Rail output. Each of the two filter sections, together with two to four

external resistors, can produce a standard 2nd-order filter functions such as Low-pass,

High-pass, Band-pass, and Band-reject. Three of these functions are simultaneously

available. Fourth-order filters can be obtained by cascading the two 2nd-order filter

sections. In the same way a higher order filters can easily be constructed by cascading

several MAX7490/MAX7491s. There are two ways to make the clock for the IC’s available.

One is an internal clock build in the IC with the use of an external capacitor to determine

the clock frequency, or external clocking for tighter cutoff frequency control. Sampling is

done at twice the clock frequency, further separating the cutoff frequency and Nyquist

frequency. The MAX7490/MAX7491 has an internal rail splitter that establishes an

accurate common voltage needed for single-supply operation. The MAX7490 operates

from a single +5V supply and the MAX7491 operates from a single +3V supply. Both

devices feature a low-power shutdown mode which only use 1μA supply current, and can

operate with a center frequency from 10Hz up to 40kHz, they also has a very high

accuracy for the Q value which is ±0.2% and the Clock-to-Centre Frequency Error is only

±0.2%. Figure 3.3 shows a block diagram of the MAX7490/MAX7491 IC. Figure 3.4 shows

a 2nd-Order state variable filter providing High-pass, Band-pass, and Low-pass outputs

[4].

Figure 3.3 [4]

Figure 3.4 [4]

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3.3 National Semiconductor LMF100

The LMF100 IC from National Semiconductor contains two independent SV filters with

high performance SC. With an external clock and 2 to 4 resistors, a wide range of second-

order and first-order filtering functions can be carried out by each filter block. Each block

has 3 outputs. One output can be setup to perform a High-pass, or Band-reject filter

function. The other two filter outputs makes a Band-pass and Low-pass filter functions.

The center frequency of each filter function is setup by using an external clock or a

combination of a clock and resistor ratio. A higher order of the filters can be implemented

by cascading more LMF100 IC’s, and all the classical filters, such as Butterworth, Bessel,

Elliptic, and Chebyshev, can be realized. The LMF100 IC has a very low offset, a wide

supply range from ±4V to ±15 but it can also operate with a single supply from 4V to 15V.

It can operate up to 100 kHz, the offset voltage is typically from ±5 mV to ±15 mV is hat a

very low crosstalk witch is in the range of −60dB the clock to center frequency ratio

accuracy is typically in the range of ±0.2%. Figure 3.5 shows a block diagram of the

LMF100 IC. Figure 3.6 shows LMF100 IC setup for a SV filter with a High-pass, Band-

pass, Low-pass and Band-reject filter with the use of an external operational amplifier [5].

Figure 3.5 [5]

Figure 3.6 [5]

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4. State Variable Filter

A SV filter is a filter there contains all filter types implanted in to one circuit, i.e. Low-pass,

High-pass, Band-pass and Band-reject filter in one circuit (figure 4.1), the outputs of the

filters is accessible at the same time. To create a SV filter circuit there are required four

operational amplifiers, two of the amplifiers performs as summing function, the two outer

performs as integrators. The passive component values is chosen by the designer, but

must be consistent with the amplifier operating range and input signal [6, 7].

4.1 Calculations

R3R2R1 == (4.1)

R5R4 = (4.2)

R9R8 = (4.3)

C2C1= (4.4)

R1R2Gain Lowpass = (4.5)

R1R3 Gain Highpass = (4.6)

C2C1R5R4R2R3

π21fC ××××

××

= (4.7)

⎟⎠⎞

⎜⎝⎛ ++××

+=

31

21

R11R7R1

R7R6 Gain Bandpass

RR

(4.8)

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×+

=C2R5R3R2

C1R4

R31

R21

R11

1R7

R7R6Q (4.9)

To calculate the value of R4 and R5 the program MathCAD where used to drive the

formula for R4 and R5, R5 is typed as R4 in equation 4.10, so MathCAD can drive a

formula for R4 shown in equation 4.11.

fc12π

R3R2 R4⋅ R4⋅ C1⋅ C2⋅

⋅

R4

12 π R2 C1 C2⋅⋅⋅⋅

R2 C1 C2 R3⋅⋅⋅( )1

2

fc⋅

1−2 π R2 C1 C2⋅⋅⋅⋅

R2 C1 C2 R3⋅⋅⋅( )1

2

fc⋅

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

:=

(4.10)

(4.11)

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To be able to calculate the values for the resistors in the SV filter some of them have to be

chosen before it is possible [6, 7].

Ω=== 10kR3R2R1 (4.12)

10kΩR7 = (4.13)

Ω== 10kR9R8 (4.14)

1nFC2C1 == (4.15)

vv1Gain = (4.16)

0.707Q = (4.17)

10kHzfC = (4.18)

When this values is been chosen it is possible to calculate the value of R4 and R5

( )

( )15.9kΩ

10k1n1n10k10k

1n1n10kπ21R4

fC2C1R3R2

C2C1R2π21R4

C

=⎟⎟⎠

⎞⎜⎜⎝

⎛ ××××⎟⎠⎞

⎜⎝⎛

××××=

⇒⎟⎟⎠

⎞⎜⎜⎝

⎛ ××××⎟⎠⎞

⎜⎝⎛

××××=

(4.19)

The relations between R6 and R7 defines the value of Q, the bigger R6 is then R7 the

bigger the value of Q will be, the value of R7 and Q has been chosen so now the value of

R6 can be calculated (equation 4.20). In appendix 10.3 the whole derivation of equation

4.20 is shown.

( )

( ) 11.21kΩ10k

1n15.9k10k10k1n15.9k

10k1

10k1

10k1

1

10k0.707R6

R7

C2R5R3R2C1R4

R31

R21

R11

1R7QR6

C2R5R3R2C1R4

R31

R21

R11

1R7

R7R6Q

=−

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×=

−

⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×=⇒

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×+

=

(4.20)

R10 is chosen to 10kΩ like R8 and R9, because the gain is chosen to be 1v/v. The signals

from the High-pass and Low-pass filter is added together to produce the Band-reject

output, and the gain of the Band-reject filter is 1v/v. Therefore all the resistors of the Band-

reject filter have to bee the same value (R8, R9 and R10).

of 46

4.2 Simulations

Figure 4.1 shows the SV filter circuit with all four types of filters, High-pass (U1A), Low-

pass (U1C), Band-pass (U1B) and Band-reject (U1D), and the output signals from the

filters is shown in figure 4.2 U1A and U1D performs as summing function, and U1B and

U1C performs as integrators. One of the advantages of a SV filter is that by changing the

value of only a few components the parameters for the whole circuit is changed. If the

value of R1 is changed the gain is changed, the ratio between R4 and R5 determined

where the fC should bee, and the ratio between R6 and R7 specifics the value of Q.

+3

-2

V+4

V-11

OUT1

U1A

TL084

+5

-6

V+4

V-

11

OUT7

U1B

TL084

+10

-9

V+4

V-

11

OUT 8

U1C

TL084

C1

1n C2

1nR1

10k

R2

10k

R3

10k

R4

16k R5

16k

R6

11k

R710k

VD

B

VD

B

VD

B

VDB

0

00

V112V

V212V0

+12V

-12V

+12V

+12V

+12V

-12V

-12V

-12V

V31Vac0Vdc

0

+12

-13

V+4

V-

11

OUT 14

U1D

TL084

R810k

R9

10k

R10

10k

0 +12V

-12V

Figure 4.1 [7]

State Variable Filter

Low-passHigh-passBand-passBand-reject-3db-40dB

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 4.2

of 46

R1 controls the gain for all four filters but the

filters losses some of there sharpness. In figure

4.3 R1 has been change to 1kΩ, which give a

gain of 20dB, which is equal to a gain 10 times.

102020Log

20dBLogAv 1010 =⇒⎟

⎠⎞

⎜⎝⎛= (4.21)

Figure 4.3

R2 controls the gain of the Low-pass filter, in

figure 4.4 R2 is changes to 100kΩ which gives

a gain of 20dB which is equal to 10 times

(equation 4.21)

Figure 4.4

R3 controls the gain of the High-pass filter, in

figure 4.5 R3 is changes to 100kΩ which gives

a gain of 20dB which is equal to 10 times

(equation 4.21)

Figure 4.5

R10 controls the gain of the Band-reject filter,

in figure 4.6 R10 is changes to 100kΩ which

gives a gain of 20dB which is equal to 10 times

(equation 4.21)

Figure 4.6

State Variable Filter (Low-pass gain of 20dB)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

State Variable Filter (All gain of 20dB)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

State Variable Filter (High-pass gain of 20dB)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

State Variable Filter (Band-pass gain of 20dB)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

of 46

The relationship between R6 and R7

determinant the Q value for all four filters, in

figure 4.7 R7 has been changes to 1kΩ, this

gives a Q of 4, see equation 4.22 [7].

41n16k10k10k

1n16k

10k1

10k1

10k1

11k

1k11kQ =⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×+

=

(4.22)

Figure 4.7

R4 and R5 have an equal influence on the fC

frequency, in figure 4.8 R4 has been changes

to 6kΩ which gives an fC of 16,24kHz if

equation 4.7 on page 14 is used.

16.24kHz1n1n6k16k10k

10kπ2

1fC =××××

××

=

(4.23)

Figure 4.8


frequency, in figure 9 R4 has been changes to

26kΩ which gives an fC of 7,8kHz if equation

4.7 on page 14 is used.

7,8kHz1n1n16k6k210k

10kπ2

1fC =××××

××

=

(4.24)

Figure 4.9


frequency, in figure 10 R5 has been changes

to 6kΩ which gives an fC of 16,24kHz if

equation 4.7 on page 14 is used.

16.24kHz1n1n6k6k110k

10kπ2

1fC =××××

××

=

(4.25)

Figure 4.10

State Variable Filter (All Q of 4)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

State Variable Filter (R4 at 6kohm)Low-passHigh-passBand-passBand-reject

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB


1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB


1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dB

of 46


1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

frequency

dBR4 and R5 have an equal influence on the fC

frequency, in figure 11 R5 has been changes to

26kΩ which gives an fC of 7,8kHz if equation

4.7 on page 14 is used.

7,8kHz1n1n6k26k110k

10kπ2

1fC =××××

××

=

(4.26)

Figure 4.11

To find out how good performance the SV filter have, the value of Q is going to be tester

for the Low-pass filter section, the test values of Q is chosen to 0.5, 5, 10, 50 and 200 to

se how the filter will handle these values. To calculate R6 equation 4.20 on page 15 is

going to be used. Table 4.1 shows the values of R6. Figure 4.12 shows the result of

simulated values of Q.

Value of Q. Value of R6

0.5 5kΩ

5 140kΩ

10 290kΩ

50 1.49MΩ

200 5.99MΩ

Table 4.1

Figure 4.12

4.2.1 Simulations sub conclusion

The reason that SV filter response for the High-pass and Band-reject, begins to go down

at roughly 2MHz is that there is used a TL084 [8] opamp from Texas Instrument in the

simulations which have a bandwidth of 3MHZ, this is don because nothing is ideal in this

world, so it was chosen to use the TL084 opamp in steed off a ideal opamp, that will give a

impossible result to achieve in reel life.

State Variable Filter (Q from 0.5 to 200)Q = 0.5Q = 5Q = 10Q = 50Q = 200

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

40

50

frequency

dB

of 46

5. Switch Capacitor Filter

There is created a passive Low-pass filter, there is used as a reference to how the filter

response for the SC filter should lock like. The center frequency for the Low-pass filter is

chosen to be 10kHz, this frequency is going to be used for all the simulations in this

chapter.

Chosen values, fC = 10kHz, C = 10nF

CRπ21fC ×××

= (5.1)

1,592kΩ10n10kπ2

1Cfπ2

1RC

=×××

⇒×××

= (5.2)

On figure 5.1 and 5.2 the results of equation 5.2 are shown, the circuit on figure 5.1 is

converted into a SC filter (figure 5.3).

R

1.592kC10n

00

V11Vac0Vdc

VDB

Figure 5.1

Switch CapacitorLow-pass

-3dB

1000 10000 100000 1000000 10000000

-50

-40

-30

-20

-10

0

frequency

dB gain

Figure 5.2

of 46

To calculate the value of CS in the SC filter, equation 5.3 has to be rewritten, so that the

value of CS can be found, fS >> fC, fs has to be 50 to 100 times bigger then fC to avoid anti-

aliasing in the SC filter.

Cπ2Cff SS

C ×××

= (5.3)

1MHz10010k100ff CS =×⇒×= (5.4)

628,3pF1M

10nπ210kC

Cπ2Cff

S

SSC

=×××

=

⇒××

×=

(5.5)

The whole divagation of equation 5.5 is shown in appendix 10.3

1,592kΩ1M628,3p

1fC

1RSS

=×

⇒×

= (5.6)

Figure 5.3 shows the SC filter circuit and figure 5.4 shows the frequency response, as it is

shows the fC is at 45.8kHz and not at 10kHz as it should be, the reason for this is mainly

that the capacitors inside the MOSFET has not been taken in to considering for this circuit.

The setup of switching pulses V2 and V3 are shown in appendix 10.4

Cs628p

C10n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0 0

00

J1BC264A

J2BC264A

VD

B

Figure 5.3

Switch Capacitor Filter responce

filter responce-3dB

1000 10000 100000 1000000

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.4

of 46

5.1 Test of different programs

In steed of using MOSFET transistors, where there is small capacitance inside, there has

to be taken into considerations. And since there is no ideal MOSFET transistors in OrCAD

10.0 there was tried to use ideal switches in steed off (figure 5.5), but it is was not possible

to generate a correct frequency response with ideal switches as shown on figure 5.6.

VD

B

Cs1628p

C110n

V41Vac0Vdc

0 00

1 2U1

01 2U2

0

Figure 5.5

Switch Capacitor Filter response with switches

filter responce

1000 10000 100000 1000000

110

100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 5.6

The program Tina Pro was tried, except there is no ideal MOSFET in Tina Pro either. The

output from the circuit in figure 5.7 is shown in figure 5.8 with a frequency at 10kHz at the

input. It is only possible to do this simulation at one frequency and not over a wide range to

create a frequency response. Figure 5.8 showns which affect the switches has on the

output signal. The input has the value of 1Volt peek to peek and the frequency is set to

10kHz which means that the output signal has to have a value of 0.707 Volt peek to peek,

because 10kHz is at the -3dB point (equation 5.7).

707.0203-Log anti

20dBLog anti3dB =⎟

⎠⎞

⎜⎝⎛⇒⎟

⎠⎞

⎜⎝⎛=− (5.7)

C2

628p

-+

Input

tSW1

tSW2 Output

C1

10n

Figure 5.7

of 46 T

Input

Output

0.749

-0.693

Time (s)0.00 50.00u 100.00u 150.00u 200.00u

Vol

tage

(V)

-1.00

-500.00m

0.00

500.00m

1.00

-0.693

0.749

Input Output Input

Output

Figure 5.8

Also the program Multisim 7 from Electronics Workbench was used to simulate a switch.

However that did not give a very good result, figure 5.9 shows two of the diagrams there

was tried to simulade in Multisim 7.

V2

1 V 1 V 0.5usec 1usec

J11 V 0mV

V112 V

R11kOhm

R2

1kOhm

R3

1kOhm

R41kOhm

V312 V

J21mV 0mV

V4

5 V 5 V 0.5usec 1usec

Figure 5.9

5.1.1 Sub Conclusion

None of the three programs gave a relay good result, the one there presented the best

result was OrCAD 10.0. Therefore is was decided to try to fix the problem in that program,

and because that was the program there is used most until now.

of 46

5.2 Switch Capacitor Filter parallel & Setup of the PSpice model

In the SC parallel Low-pass filter circuit in figure 5.10 the C1 is en parallel with C on the

output and the size of the C1 to make the equivalent resistor is calculated in equation 5.8.

628,3pF1M

10n10kπ2f

Cfπ2CS

C1 =

×××⇒

×××= (5.8)

The filter response is shown on figure 5.11 with the cutoff frequency at -3dB, at 45.8kHz

and not at 10kHz as it should be the main reason for this is all the values there are in the

PSpice model of the BC246A MOSFET, these values are shown in figure 5.12. These

values can be adjusted to make a more ideal MOSFET, and to obtain a better frequency

response.

J1BC264A

J2BC264A

C1628p

C210n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

00 0

0 0

VD

B

Figure 5.10

Switch Capacitor Filter responce

filter responce-3dB

1000 10000 100000 1000000

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.11

of 46

Figure 5.12

After the PSpise model figure 5.12, hade been adjusted to the best possible (figure 5.14) a

new frequency response is created as shown in figure 5.13, this frequency response is not

ideal, but it was not possible to obtain a better frequency response. Therefore a decision

was made, to use this PSpice model (figure 5.14) for the rest of the simulations in this

paper. Switch Capacitor Filter response with ideal MOSFET

filter responce-3dB

1000 10000 100000 1000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 5.13

Figure 5.14

BC264A PSpice model

.model BC264A NJF(Beta=2m Betatce=-.5 Rd=1 Rs=1

+ Lambda=2.667m Vto=-1.249 Vtotc=-2.5m Is=33.57f

+ Isr =322.4f N=1 Nr=2 Xti=3Alpha=311.7u Vk=243.6

+ Cgd=3.35p M=.3622 Pb=1 Fc=.5 Cgs=3.598p

+ Kf=14.38E-18 Af=1)

New BC264 PSpice model

.model BC264A NJF(Beta=0.285m Betatce=-1.5 Rd=1

+ Rs=1 Lambda=1p Vto=-2.249 Vtotc=0 Is=0.1f

+ Isr=0.1f N=1 Nr=2 Xti=0 Alpha=0p Vk=0 Cgd=0 M=0

+ Pb=1 Fc=0 Cgs=0 Kf=0 Af=0)

of 46

5.3 Switch Capacitor Filter Series

In the SC series circuit figure 5.15, the C1 is placed in series between the MOSFET J1’s

gate and source, the equation for the size of the equivalent resistor is the same as for the

parallel setup in equation 5.2 (1.592kΩ) the size of C1 is calculated in equation 5.9 and

equation 5.10 [6] is a control equation. The filter response in figure 5.16 is not ideal

because of the MOSFET is not ideal, because of the PSpice model in figure 5.14 has been

modified.

628,3pF1M

10n10kπ2f

Cfπ2CS

2CS =

×××⇒

×××= (5.9)

1.592kΩ1M628.3p

1fC

1RSS

=×

⇒×

= (5.10)

J1BC264A

J2BC264A

C1

628p

C210n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0 0

0 0

VD

B

Figure 5.15

Switch Capacitor Filter Series

filter response-3dB

1000 10000 100000 1000000

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.16

of 46

5.4 Switch Capacitor Filter Parallel and Series

The circuit of the SC parallel and series 5.17, is one capacitor placed in series (C1) and

one in parallel (C2) these two capacitors creates one equivalent resistor. The equation for

the size of the equivalent resistor is the equal to equation 5.2 (1.592kΩ) used in the

parallel circuit. The size of C1 and C2 together, is calculated in equation 5.11 [6]. The value

of C1 and C2 can be any size, as long as the total value produce a capacitor size of

628.3pF (equation 5.11) and equation 5.12 [6] is a control equation. In figure 5.18 C1 =

528pF and C2 = 100pF. In figure 5.19 C1 = 100pF and C2 = 528pF. In figure 5.20 C1 =

314pF and C2 = 314pF.

628,3pF1M

10n10kπ2f

Cfπ2CS

2CS =

×××⇒

×××= (5.11)

( ) ( ) Ω=×+

⇒×+

= kMpp

592.11100528

1fCC

1RS21

(5.12)

J1BC264A

J2BC264A

C1

528p C310n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0

0

0

C2100p

0

VD

B

Figure 5.17

Switch Capacitor Filter Parallel and Seriesfilter response-3dB

1000 10000 100000 1000000

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.18

of 46 Switch Capacitor Filter Parallel and Series

filter response-3dB

1000 10000 100000 1000000

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.19

Switch Capacitor Filter Parallel and Series

filter response-3dB

1000 10000 100000 1000000

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.20

5.4.1 Switch Capacitor Filter Parallel and Series sub conclusion

Figure 5.18 and 5.19 don’t show an ideal filter response, the two filter responses in figure

5.18 and 5.19 is opposite each other. That is because C1 and C2 have different values in

each case, if C1 and C2 have the same value as in figure 5.20 the two capacitors cancel

each other out and generate and perfect filter response as shown in figure 5.20. But

another reason that the filter response in figure 5.18 and 5.19 is not ideal could be

because of the MOSFET is not ideal, because of the PSpice model in figure 5.14 has been

modified.

of 46

5.5 Switch Capacitor Filter Bilinear

In the SC bilinear circuit the capacitor C1 is placed between four MOSFETs, in figure 5.21,

this means that there always will be two MOSFETs ON at the same time (J1, J4) and (J2,

J3). This will eliminate the effect from parasite capacitors in the circuit. The equation for

the size of the equivalent resistor is the same as for the parallel circuit in equation 5.2

(1.592kΩ) and with C2 at 10nF the -3dB point should be at 10kHz but it is at 20kHz in

figure 5.22. If the sample frequency fS is changes to 2MHz the value of C1 becomes

78.5pF and the result of this gives a -3dB point at 20kHz. If the same test is don with a

sample frequency fS of 500kHz the value of C1 becomes 314pF and the result of this gives

a -3dB point at 20kHz. If the original PSpice file (figure 5.12) is used the -3dB point moves

up to 94kHz [6].

157pF1M1.592k4

1fR4

1fC4

1RSSS

=××

⇒××

=⇒××

= SC (5.13)

J1BC264A

J2BC264A

C1157p

C210n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0 0

J3BC264A

J4BC264A

0

Q1Q2

Q1 Q2

VD

B

Figure 5.21

Switch Capacitor Filter Bilinear

filter response-3dB

1000 10000 100000 1000000

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

frequency

dB

Figure 5.22

of 46

5.6 Negative Switch Capacitor Trans-resistance Realization

In the negative trans-resistance realization SC circuit, figure 5.23 there is uses four

MOSFETs and the C1 is placed in series between the sours of J1 and the drain of J2.

When Q1 is high “1” the C1 is being charts and when Q2 is high “1” C1 is discharging on to

C2, the equation for C1 is the same as for the SC in parallel in equation 5.2. But as the filter

response on figure 5.24 shows, dos the SC circuit on figure 5.23 not make a Low-pass

filter response but a Band-pass response, with the -3dB points from max -36.5dB at

9.5kHz and 347kHz. If the cutoff frequency fC is changes to 100kHz then C1 becomes

6.28nF and the -3dB points from max -19.5dB moves to 6kHz and 54kHz. Then if the

cutoff frequency fC is decreased to 1kHz then C1 becomes 62.8pF and the -3dB points

from max -56dB moves to 10kHz and 3.28MHz. If the original PSpise file figure 5.12, is

used, the -3dB points from the max -36.5dB moves to 44kHz and 1.59MHz [6].

628,3pF1M

10n10kπ2f

Cfπ2CS

C1 =

×××⇒

×××= (5.14)

C210n

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0

0

0

C1

628pJ1BC264A

J2BC264A

J3BC264A

J4

BC264A

VD

B

0

Figure 5.23

Negative Switch Capacitor Transresistance Realizationfilter responseMax -36.5dB-3dB

1000 10000 100000 1000000

-75

-70

-65

-60

-55

-50

-45

-40

-35

frequency

dB

Figure 5.24

of 46

5.7 Positive Switch Capacitor Trans-resistance Realization

In the positive trans-resistance realization SC circuit figure 5.25 there is uses four

MOSFETs, as well as in the negative trans-resistance realization SC circuit and the C1 is

placed in the same way, the difference is that when V1 is high “1” the C1 is being

discharge and when V2 is high “1” C1 is transferring the signal on to C2, the equation for C1

is the same as for the negative trans-resistance realization equation 5.15. And the filter

response in figure 5.26 shows the same result as the negative trans-resistance realization

SC circuit in figure 5.24. The same test has been made on the positive SC trans-

resistance realization as on the negative and gave exactly the same results as on page 30.

628,3pF1M

10n10kπ2f

Cfπ2CS

C1 =

×××⇒

×××= (5.15)

J1BC264A

J2

BC264A

J3BC264A

J4BC264A

C1

628p

C210n

V1

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V2

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

V31Vac0Vdc

0

0

0

0

0

VD

B

Figure 5.25

Positive Switch Capacitor Transresistance Realization

filter responseMax -36.5dB-3dB

1000 10000 100000 1000000

-75

-70

-65

-60

-55

-50

-45

-40

-35

frequency

dB

Figure 5.26

of 46

5.8 Switch Capacitor Filter Conclusion

The Low-pass filter response figure 5.2 from the passive filter in figure 5.1 page 20 is used

as reference for all the SC filter simulations in this chapter. The first simulation of the

parallel SC filter figure 5.3 on page 21 did not provide the expected result, one of the

reasons for this, were that there is not used a ideal MOSFET transistor for the simulations,

and since that there is no ideal MOSFET transistor in OrCAD 10.0, some other programs

were tested, however non of them produced a ideal result either, as concluded in the 5.1.1

sub conclusion on page 23. The use of the modified PSpice file figure 5.14 on page 25 for

these simulations will have a small effect on the results. The simulation of the parallel SC

filter figure 5.13 has a small error, because the filter response does not produce a linear

response as it should. This error can be an error created by the modified PSpice model.

The simulation of the series SC filter figure 5.16 page 26 also generate a small error but

not as bad as the parallel SC filter. The simulation of the parallel and series SC filter also

generate a small error if the two SC don’t have the same size. If they have the same size

the filter response of the filter is perfect, as it is concluded in 5.4.1 sub conclusion. In the

simulation of the bilinear SC filter figure 5.22 page 29 the filter response -3dB point is

placed at 20kHz which is 10kHz above the calculated point. This error can be explained by

the modified PSpice model, it can furthermore be explained by the fact that a capacitor act

different, when it is used in a circuit where there is used high frequency as the switching

frequency there are used on the MOSFETs. The frequency response of the bilinear on

figure 5.22, shows that there are no parasitic capacitances, because the response is very

linear. That is exactly what the use of four MOSFET transistors should prevent. The

simulations of the negative and positive trans-resistance realization SC filters produce the

same results and are very fare from the expected result, which is the filter response from

figure 5.2. The reason for this is again that a capacitor act very different at high

frequencies. This concludes that the easiest and most ideal SC setup is the parallel and

series setup figure 5.17. Although the parallel SC setup figure 5.10 and the series SC

setup figure 5.15, can also be used with the knowledge of that they give a small error.

of 46

6. State Variable Filter with Switch Capacitor

The SV filter there are constructed in chapter 4, figure 4.1 is being converted into a SV

filter using the SC technology, there was found most use full in chapter 5 which is the

parallel (figure 5.10) or series (figure 5.15) and the parallel and series (figure 5.17) SC

technologies.

6.1 State Variable Filter with Parallel or Series Switch Capacitor

In figure 6.1 all the resistors except R4 and R5 has been converted in to a SC resistor

using only the parallel or the series technology, the result of this is shown in figure 6.2

which is very close to the result from the SV filter figure 4.2, which is used as the final

result. The clock frequency for the MOSFETs are chosen to be 1MHz, because of the

choice of resistors in the SV filter (figure 4.1), many of the capacitors in the SV SC filter is

going to have the same value, even if it is used in parallel or a series SC technology. C1

and C2 was chosen to be 1nF in the SV filter, this are not change, and since the equation

for the size of the SC is the same for the parallel or the series technology there is only on

equation (equation 6.1) [7].

SS

SS fR1C

fC1R

×=⇒

×= (6.1)

There are seven resistors there have a size of 10kΩ (R1, R2, R3, R7, R8, R9 and R10) in the

SV filter in figure 4.1, this will produce the same capacitor size which is calculated in

equation 6.2, this is the size of C3, C4, C5, C6, C7, C8, C9.

100pF1M10k

1fR

1CS

3 =×

⇒×

= (6.2)

R6 has been calculated to provide a resistor size of 11kΩ in equation 4.20. The size of the

capacitor C10 is calculated to 91pF in equation 6.3 [7].

91pF1M11k

1fR

1CS

10 =×

⇒×

= (6.3)

of 46

+3

-2

V+4

V-

11

OUT 1

U1A

TL084

+5

-6

V+

4V-

11

OUT7

U1B

TL084

+10

-9

V+4

V-

11

OUT 8

U1C

TL084

+12

-13

V+4

V-11

OUT 14

U1D

TL084

Q1

C1

1n

C2

1n

V11Vac0Vdc

V2

12Vdc

V3

12Vdc

V4

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V5

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

00 0

00

0

0

0

0

Q2

J7BC264A

J8BC264A

0

C6100p

R4

16k

+12Vcc

R5

16k

-12Vcc

-12Vcc

J17BC264A

J18BC264A

-12Vcc

C9100p

-12Vcc

J3BC264A

J4BC264A

-12Vcc

C4

100p

+12Vcc+12Vcc

+12Vcc

J11BC264A

Q1

+12Vcc

J12BC264A

Q2

Q1 Q2

Q2Q1

C7100p

J19BC264A

0

J20BC264A

C1091p

J5BC264A

J6BC264A

C5100p

J1BC264A

Q1

0

J2BC264A

Q2

Q1

C3

100p

0

Q2

Q1

Q2

Q2

Q1

Q1

Q2

VD

B

VD

B

VD

B

VD

B

C8100p

J15BC264A

J16BC264A

Figure 6.1

When the outputs of the SV SC filter on figure 6.1 is compared with the outputs of the SV

figure 4.2 page 16, they are very alike, however there is a very little difference. Tthe Low-

pass response goes down to roughly -70dB at 600kHz witch is -10dB lower then in figure

4.2. The Band-pass and Band-reject responses is more sharp then in figure 4.2, this is

because both the High-pass and Low-pass responses has a bigger damping in the end of

the response roughly around -70dB where in figure they ends ad roughly -50dB. State Variable with Switch Capacitors

Low-passHigh-passBand-passBand-reject-3dB-40dB

1000 10000 100000 1000000 10000000

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 6.2

of 46

In figure 6.3 R4 and R5 is converted in to SC resistors using the series technology

although the parallel theory is just as good and will produce the same result. The problem

by converting these two resistors to SC resistors is that they are placed next to C1 and C2

as have the value of 1nF each, and this moves the center frequency one decade up from

10kHz to 100kHz, as shown on figure 6.4. By increasing the value of C1 and C2 to 10nF

each the centre frequency is moved back to 10kHz, as shown in figure 6.6. R4 and R5

have been calculated to give 16kΩ in equation 4.19. The size of capacitor C11 and C12 is

calculated to 62.5pF in equation 6.3 [7].

62.5pF1M16k

1fR

1CS

11 =×

⇒×

= (6.4)

+3

-2

V+4

V-

11

OUT1

U1A

TL084

J23BC264A+5

-6

V+

4V-

11

OUT 7

U1B

TL084

+10

-9

V+

4V-

11

OUT 8

U1C

TL084

+12

-13

V+

4V-

11

OUT 14

U1D

TL084

Q1

J24BC264A

C1

1n

C1162.5p

C2

1n

V11Vac0Vdc

V2

12Vdc

V3

12Vdc

C1262.5p

V4

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V5

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

00 0

0

0

0

0

0

0

Q2

J7BC264A

J8BC264A

0

C6100p

Q1

Q1

Q2

+12Vcc

-12Vcc

Q2

-12Vcc

J17BC264A

J18BC264A

-12Vcc

C9100p

-12Vcc

J3BC264A

-12Vcc

J4BC264A

C4

100p

+12Vcc+12Vcc

+12Vcc

J11BC264A

Q1

+12Vcc

J12BC264A

Q2

Q1 Q2

Q2Q1

C7100p

0

J19BC264A

J20BC264A

C1091p

VD

B

VD

B

VD

B

VD

B

J5BC264A

J6BC264A

C5100p

Q1

J1BC264A

0

J2BC264A

Q2

Q1

C3

100p

Q2

0

Q1

Q2

Q2

Q1

Q1

Q2

C8100p

J15BC264A

J21BC264A

J22BC264A

J16BC264A

Figure 6.3


1000 10000 100000 1000000 10000000

120

110

100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 6.4

of 46

Figure 6.6 shows the final test of the SV SC filter with parallel or series technology. A

larger diagram of figure 6.5 with the final values of C1 and C2 can be found in appendix

10.5.

+3

-2

V+4

V-

11OUT 1

U1A

TL084

+5

-6

V+

4V-

11

OUT7

U1B

TL084

J23BC264A

+10

-9

V+4

V-

11

OUT 8

U1C

TL084

+12

-13

V+4

V-11

OUT 14

U1D

TL084

Q1

J24BC264A

C1

10n

C1162.5p

C2

10n

V11Vac0Vdc

V2

12Vdc

V3

12Vdc

C1262.5p

V4

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V5

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

00 0

0

0

0

0

0

0

Q2

J7BC264A

J8BC264A

0

C6100p

Q1

Q1

Q2

+12Vcc

-12Vcc

Q2

-12Vcc

J17BC264A

J18BC264A

-12Vcc

C9100p

-12Vcc

J3BC264A

-12Vcc

J4BC264A

C4

100p

+12Vcc+12Vcc

+12Vcc

J11BC264A

Q1

+12Vcc

J12BC264A

Q2

Q1 Q2

Q2Q1

C7100p

0

J19BC264A

J20BC264A

C1091p

J5BC264A

J6BC264A

C5100p

Q1

J1BC264A

0

J2BC264A

VD

B

VD

B

VD

B

VD

B

Q2

Q1

C3

100p

Q2

0

Q1

Q2

Q2

Q1

Q1

Q2

C8100p

J15BC264A

J21BC264A

J22BC264A

J16BC264A

Figure 6.5


1000 10000 100000 1000000 10000000

120

110

100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 6.6

of 46

6.2 State Variable Filter with Parallel and Series Switch Capacitor

The SV SC filter in figure 6.7 is created only by using the SC parallel and series

technology, which was concluded in chapter 5 to be the best way to produce an SC

resistor. All the capacitors in figure 6.5 is divided by two to make two equal capacitors to

the parallel and series technology, as used in figure 6.7 C3 to C8, C13, C14 and C17 to C22 is

calculated to be 50pF (equation 6.5), and C9 to C12 is calculated to be 31.25pF (equation

6.6), and C15and C16 is calculated to be 45.5pF (equation 6.7) [7].

50pF2

1M10k1

2fR

1

C S3 =

⎟⎠⎞

⎜⎝⎛

×⇒⎟⎟⎠

⎞⎜⎜⎝

⎛×

= (6.5)

31.25pF2

1M16k1

2fR

1

C S9 =

⎟⎠⎞

⎜⎝⎛

×⇒⎟⎟⎠

⎞⎜⎜⎝

⎛×

= (6.6)

45.5pF2

1M11k1

2fR

1

C S15 =

⎟⎠⎞

⎜⎝⎛

×⇒⎟⎟⎠

⎞⎜⎜⎝

⎛×

= (6.7)

In appendix 10.6 is there a larger diagram of figure 6.7 which is the final diagram. And the

filter response is shown on figure 6.8.

-12V

V11Vac0Vdc

V2

TD = 0

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5V3

TD = 500n

TF = 0PW = 500nPER = 1u

V1 = 0

TR = 0

V2 = 5

0

0 0

-12V

-12V

J1BC264A

J2BC264A

J3BC264A

J4BC264A

J5BC264A

J6BC264A

J7BC264A

J8BC264A

J9BC264A

J10BC264A

J11BC264A

J12BC264A

J13BC264A

J14BC264A

J15BC264A

J16BC264A

J17BC264A

J18BC264A

J19BC264A

J20BC264A

C1

10n

C2

10n

C3

50p C450p

C5

50pC650p

C7

50p C850p

C9

31.25pC1031.25p

C11

31.25pC1231.25p

C13

50pC1450p

C15

45.5pC1645.5p

C17

50pC1850p

C19

50pC2050p

C21

50pC2250p

Q1

0 0

0

Q1 0

0

0

0

0

Q1

0

0 0

0

0

Q1

Q1

0

Q1

Q1

Q1

Q2

Q1

Q1 Q1

Q2

Q2

Q2 Q2

V412Vdc

V512Vdc

0

+12V

-12VQ2

Q2

+3

-2

V+4

V-11

OUT1

U1A

TL084

Q2

+5

-6

V+4

V-11

OUT7

U1B

TL084

+10

-9

V+4

V-11

OUT8

U1C

TL084

Q2

VD

B

VD

B

VD

B

VD

B

+12

-13

V+4

V-11

OUT 14

U1D

TL084

Q2 Q2

+12V

+12V

+12V

+12V

-12V

Figure 6.7

of 46

Figure 6.8 shows the filter response of figure 6.7, the filter response on figure 6.8 is almost

identical to the filter response from the SV filter in figure 4.2 page 16, which is used as

result reference for the SV SC filter response. One of the larger differences between the

two filter responses is that the Band-reject on figure 6.8 goes down to -52dB, but this is not

a major error because it is the Band-reject response, and because in the Band-reject

response a larger damping is in most cases a good thing. The important part is that the -

3dB point is exactly on the place it have to be. Switch Capacitor Filter Parallel and Series

Low-passHigh-passBand-passBand-reject-3dB-52dB

1000 10000 100000 1000000 10000000

110

100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency

dB

Figure 6.8

of 46

7. Conclusion

The SV filter in chapter 4 figure 4.1 is constructed with a TL084 opamp and this creates

some limitations of the SV filter operation area. The bandwidth of the TL084 is only 3MHz

and this means that the fC frequency of the filter roughly can go up to 100kHz which is

more than enough for the filter to be used for audio applications. The Q value of the filter

was tested up to 200, this produce a value of R6 in figure 4.1 of 5.99MΩ, which is a very

large resistor. However it will be a very small capacitor of 0.17pF with a clock frequency of

1MHz, which is achievable in a SC filter. In chapter 5 it was found out that the parasitic

capacitors in the MOSFET has a very large influence on the filter response and to avoid

this the PSpice model in figure 5.12 was modified to produce a more accurate filter

response. The PSpice model used is provided in figure 5.14 on page 25. With the new

PSpice model all the SC circuits was tested, and the result of this is that the SC parallel

and series in figure 5.17 provides the best result with two equal capacitors, as concluded

in 5.8 SC filter conclusion on page 32. In chapter 6 the SV filter from chapter 4 figure 4.1 is

converted in to a SV filter using SC resistors, the first filter figure 6.5 uses parallel or series

technology and the result is shown in figure 6.6 the second SV SC filter uses the parallel

and series technology and the result is shown in figure 6.8 and is very similar to figure 6.6

but the second filter figure 6.7, is a little better then the first one figure 6.5. There was also

tried to simulate a SV filter using only the SC bilinear technology but this was not possible

to archive a result from OrCAD 10.0 and the same happened when the negative and

positive SC trans-resistance realization was tried. The SV filter in figure 4.1 uses the

TL084 opamp which has its disadvantages, it only has a bandwidth of 3MH and is has to

use ±12V, but it can easily be replaced with another opamp that has a bigger bandwidth

and a lot smaller supply voltage, and a mush better slew rate which is typically 13V/µs in

the TL084 opamp. If the SV filter is to be build in practice. The SV SC filter is almost

impossible to build in practice, because of all the MOSFET, if it was to be build in practice

it will use a lot of space and the MOSFET has to have some very similar parameters

before it will work, the only reasonable way to construct a SV SC filter is to do it in a IC i.e.

a DSP, PIC or FPGA. In appendix 10.2 there is provided two timetables one from befor the

project began and on after the project was finished, and the two timetables is very similar,

some of the dates have been changes but all in all the timetable have been followed to

satisfaction.

_________________________________

23/04/2006 Klaus Jorgensen

of 46

8. References

[1]. Analog Filters 5th edition 1996, by. Kendall L. Su

ISBN: 0-412-63840-1

[2]. http://www.mtmi.vu.lt

[3]. http://focus.ti.com/lit/ds/symlink/uaf42.pdf

[4]. http://pdfserv.maxim-ic.com/en/ds/MAX7490-MAX7491.pdf

[5]. http://cache.national.com/ds/LM/LMF100.pdf

[6]. Operational Amplifiers 5th edition, by. George Clayton & Steve Winder

ISBN: 07506-5914-9

[7]. Mixed-Signals Design Seminar, by. Analog Devices

ISBN: 0-916550-08-7

[8]. http://www.datasheetarchive.com/search.php?search=TL084&sType=part

9. Bibliography

• Allen/Holberg: Chapter 9 (12/19/97)

http://www.ece.utexas.edu/~holberg/lecture_notes/bk9.pdf

• Analog Filters 5th edition 1996, by. Kendall L. Su

ISBN: 0-412-63840-1

• Analog MOS integrated circuits, by. Paul R. Gray, David A. Hodges and Robert W.

Brodersen.

ISBN: 0-87942-142-8

• Mixed-Signals Design Seminar, by. Analog Devices

ISBN: 0-916550-08-7

• Operational Amplifiers 5th edition, by. George Clayton & Steve Winder

ISBN: 07506-5914-9

of 46

10. Appendix

10.1 Project Proposal

of 46

10.2 Time Plans

Time plan from the 20 of October 2005

Final time plane from the 1 of May 2006

of 46

10.3 Derivation of equation

Derivation of equation 4.20

( )( )

( ) R7

C2R5R3R2C1R4

R31

R21

R11

1R7QR6

C2R5R3R2C1R4

R31

R21

R11

1R7QR7R6

R7Q

C2R5R3R2C1R4

R31

R21

R11

1

R7R61

Q

C2R5R3R2C1R4

R31

R21

R11

1

R7R6R7

C2R5R3R2C1R4

R31

R21

R11

1R7R6

R7Q

C2R5R3R2C1R4

R31

R21

R11

1R7

R7R6Q

−

⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×=

⇒

⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×=+

⇒×

⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

=+

⇒

⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

=+

⇒⎟⎠⎞

⎜⎝⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

=+

×

⇒⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

××××

×⎟⎠⎞

⎜⎝⎛ ++

×+

=

Derivation of equation 5.5

SS

C

SSC

SSC

Cf

Cπ2fCfCπ2f

Cπ2Cff

=×××

⇒×=×××

⇒××

×=

of 46

10.4 Vpulse in OrCAD

Setting the part parameters of the Vpulse in OrCAD

Double click on the resistance or capacitor, and the corresponding value of a resistance or

a capacitance can be changed. Double click on the pulse voltage source. Set the

following parameters for the source.

V1: The minimum voltage of the pulse

V2: The maximum voltage of the pulse

TD: The delay from time zero of the first rising edge

TR: Rise time

TF: Fall time

PW: Pulse width

PER: Period time

of 46

10.5 State Variable Filter with Parallel or Series Switch Capacitor

+3

-2

V+4V-11

OU

T1

U1A

TL08

4

J23

BC26

4A+

5

-6

V+4V-11

OU

T7

U1B

TL08

4

+10

-9

V+4V-11

OU

T8

U1C

TL08

4

+12

-13

V+4V-11

OU

T14

U1D

TL08

4

Q1

J24

BC

264A

C1

10n

C11

62.5

p

C2

10n

V11V

ac0V

dc

V2

12V

dc

V3

12V

dc

C12

62.5

p

V4

TD =

0

TF =

0P

W =

500

nP

ER =

1u

V1

= 0

TR =

0

V2

= 5

V5

TD =

500

n

TF =

0PW

= 5

00n

PER

= 1

u

V1 =

0

TR =

0

V2 =

5

00

0

00

0

0

0

0

Q2

J7 BC

264A

J8 BC26

4A

0

C6

100p

Q1

Q1

Q2

+12V

cc

-12V

cc

Q2

-12V

cc

J17

BC26

4AJ1

8B

C26

4A

-12V

cc

C9

100p

-12V

cc

J3 BC26

4AJ4 B

C26

4A

-12V

cc

C4

100p

+12V

cc+1

2Vcc

+12V

cc

J11

BC26

4A

Q1

+12V

cc

J12

BC

264A

Q2

Q1

Q2

Q2

Q1

C7

100p

J19

BC

264A

0

J20

BC26

4AC

1091

p

J5 BC

264A

J6 BC26

4AC

510

0p

J1 BC

264A

Q1

0

J2 BC

264A

VDB

VDB

VDB

VDB

Q2

Q1

C3

100p

0

Q2

Q1

Q2

Q2

Q1

Q1

Q2

C8

100p

J15

BC26

4A

J21

BC

264A

J22

BC

264A

J16

BC

264A

of 46

10.6 State Variable Filter with Parallel and Series Switch Capacitor

-12V

V1

1Vac

0Vdc

V2

TD =

0

TF =

0PW

= 5

00n

PE

R =

1u

V1

= 0

TR =

0

V2

= 5

V3

TD =

500

n

TF =

0PW

= 5

00n

PE

R =

1u

V1 =

0

TR =

0

V2 =

5

0

00

-12V

-12V

J1 BC26

4AJ2 BC

264A

J3 BC26

4AJ4 BC

264A

J5 BC26

4AJ6 BC

264A

J7 BC

264A

J8 BC26

4AJ9 B

C26

4AJ1

0BC

264A

J11

BC26

4AJ1

2BC

264A

J13

BC

264A

J14

BC26

4A

J15

BC

264A

J16

BC26

4AJ1

7BC

264A

J18

BC26

4A

J19

BC26

4AJ2

0BC

264A

C1

10n

C2

10n

C3

50p

C4

50p

C5

50p

C6

50p

C7

50p

C8

50p

C9

31.2

5pC

1031

.25p

C11

31.2

5pC

1231

.25p

C13

50p

C14

50p

C15

45.5

pC

1645

.5p

C17

50p

C18

50p

C19

50p

C20

50p

C21

50p

C22

50p

Q1

00

0

Q1

0

0

0

0

0

Q1

0

00

0

0

Q1

Q1

0

Q1

Q1

Q1

Q2

Q1

Q1

Q1

Q2

Q2

Q2

Q2

V4

12Vd

c

V5

12Vd

c0

+12V

-12V

Q2

Q2

+3

-2

V+

4

V-

11

OU

T1

U1A

TL08

4

Q2

+5

-6

V+

4

V-

11

OU

T7

U1B

TL08

4

+10

-9

V+

4

V-

11

OU

T8

U1C

TL08

4

Q2

VDB

VDB

VDB

VDB

+12

-13

V+

4

V-

11

OU

T14

U1D

TL08

4

Q2

Q2

+12V

+12V

+12V

+12V

-12V

honours project - switched capacitor filter design for ... project... · honors project switched...

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