homework 6: printed circuit board layout design … 477 digital systems senior design project spring...

ECE 477 Digital Systems Senior Design Project Spring 2008

Homework 6: Printed Circuit Board Layout Design NarrativeDue: Friday, February 22, at NOON

Team Code Name: Agatha Group No. 4

Team Member Completing This Homework: Zachary Dicklin

e-mail Address of Team Member: zdicklin @ purdue.edu

Evaluation:

SCORE DESCRIPTION

10 Excellent – among the best papers submitted for this assignment. Very fewcorrections needed for version submitted in Final Report.

9 Very good – all requirements aptly met. Minor additions/corrections needed forversion submitted in Final Report.

8 Good – all requirements considered and addressed. Several noteworthyadditions/corrections needed for version submitted in Final Report.

7 Average – all requirements basically met, but some revisions in content shouldbe made for the version submitted in the Final Report.

6 Marginal – all requirements met at a nominal level. Significant revisions incontent should be made for the version submitted in the Final Report.

* Below the passing threshold – major revisions required to meet reportrequirements at a nominal level. Revise and resubmit.

* Resubmissions are due within one week of the date of return, and will be awarded a score of“6” provided all report requirements have been met at a nominal level.

Comments:


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1.0 Introduction

The development of our PCB was an iterative process that placed and replaced components

and traces based on a number of requirements. Organized component placement and signal

routing was a major concern. As more traces were routed, additional factors like power,

interference, and component sensitivity became factors as well. Numerous redesigns with these

factors in mind led to a safe and well-spaced layout.

2.0 PCB Layout Design Considerations – Overall

The PCB layout evolved naturally out of the design schematic [Appendix A]. Components

are generally placed relative to their location on the microcontroller [Appendix B]. By placing

components in this manner we reduce the complications of longer traces and the need for

additional vias. This should not to suggest that component placement was straightforward, and

several design iterations were required to develop an organized, well-spaced layout that satisfies

device requirements.

A number of components in our design use a large amount of power, in particular the

5.7” LCD and the RFID reader, but these components are not located on or powered by the PCB.

In fact, PCB is not expected to consume large amounts of power- far less than the 2A provided

by the voltage regulator [1] - and uses 60 mil power and ground traces. This exceeds the absolute

minimum width of 40 mils [2]. Logic traces are drawn 12 mils wide, a suitable size for these

low-power signals. The device is not intended for operation above or below room temperature,

so resistance at extreme operating temperatures was not considered.

The Freescale 9S12NE64 microcontroller is placed near the top center of the board for

convenient access to power, ground, and the peripheral devices it integrates. Careful attention

was given to fanning out signals as much as possible from the microcontroller. Our notes

recommend a minimum spacing of 12 mils, but our signals are spread much further wherever

possible. Spreading these signals intends to reduce interference and became an influence on

component selection and placement. The GPIO header, for example, was reduced from 20 pins

to 10 pins to facilitate a greater fan out.

The Ethernet controller is one of the more sensitive components in our design and can

easily be affected by interference. Close attention was paid to the Freescale 9S12NE64 PCB

design recommendations. Large portions of our PCB were designed with the Ethernet controller


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in mind to minimize harmful effects. For example, the power and ground traces, originally at the

top right of the board, were moved to the lower left to avoid the Ethernet components.

Differential RX and TX pairs are drawn in short (about 1”), straight traces from the

microcontroller to the RJ45 jack. The differential pairs are the only exceptions to the fan out

rules followed for most signals: these signals are kept as close together as possible, about 10

mils. The sets of pairs, however, are kept as far apart as possible. These signals are kept at nearly

equal lengths [3].

In order to avoid vias, the RJ45 jack is mounted to the bottom of the PCB rather than the

top. The pins from the microcontroller do not correctly correspond to the pins on the RJ45 jack,

but are actually entirely reversed. Mounting the jack to the bottom reduces wiring complexity

and does not add any significant difficulty to PCB or package manufacturing.

The Max3322 level shifter and RS232 jacks were placed at the bottom of the board. The

RS232 jacks need to be placed off the edge of the board, and because of the placement of the SCI

pins on the Freescale 9S12NE64, the bottom portion of the board is a convenient place for these

devices. Like the RJ45 jack, the Max3322 level shifter was placed on the bottom of the board

because its TTL level input and output signal pins are opposite to their corresponding pins on the

microcontroller. On the bottom of the PCB, the signals require fewer vias and, as the RS232

jacks are through-hole devices, the Max3322 can connect its RS232 jacks without vias. Bottom

placement also conveniently lines up the signals to an SCI header used for debugging.

Decoupling capacitors for the Max3322 were selected and placed and placed as close to the chip

as possible, as per the manufacturer’s specification [4].

The SD card reader, accessed through the SPI module, is not mounted on the PCB but is

instead connected through an SPI header. This configuration saves board space, eliminates a

complicated network of traces and vias, improves debugging support, and is likely more suitable

to the product’s packaging.

A 10-pin header located on the top left of the board provides connections to additional

general-purpose I/O pins. Their use is not yet defined, but provide options for debugging,

additional input, or backup pins in the event that a part of the board breaks or fails to function.


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3.0 PCB Layout Design Considerations - Microcontroller

The microcontroller layout followed the PCB design recommendations provided in Appendix

B of the Freescale 9S12NE64 data sheet [3]. Decoupling capacitors are connected as near as

possible to their corresponding supply pairs, either directly to the side or underneath the

microcontroller. Aside from these capacitors, no other signals are run underneath the

microcontroller in order to avoid interference. The same attention is paid to the oscillator circuit:

the oscillator was kept on the top of the board as close to the microcontroller as possible, and no

power traces or signals are routed beneath.

Power traces are routed to avoid crossing certain sections of the microcontroller. The

microcontroller requires power and ground connections from all sides, but sensitive circuits, like

the Ethernet and the oscillator circuit, limit the options of large power traces. 30 mil power and

ground traces are provided where convenient and appropriate. The microcontroller is kept to the

right of the power and ground traces, and VCC and VDD pins from the top, left, and bottom

were routed with little difficulty. To avoid interference with the Ethernet and oscillator circuits,

supply pins from the right side are routed to decoupling capacitors underneath the

microcontroller.

4.0 PCB Layout Design Considerations - Power Supply

The power supply was designed with the criteria in mind to provide power to all necessary

components while not interfering with signals or creating loops. The device is not expected to

draw large quantities of power, so power and ground traces are drawn 60 mils wide. At 90

degrees F, a 60 mil trace can allow a maximum amperage of 2.248A, which is well above our

current requirements. The largest power trace on the board is less than 8” in length. 60 mil

copper traces have a resistance of .00466 ohm/in [5]. Even at the maximum 2A current, this is a

drop of .07V.

At These traces often taper to 30 mils when reaching a component likely to use a good deal

of power, and taper again to certain components- in particular ICs- with smaller pins.

The main traces are drawn near each other, as recommended in the Motorola AN1259

Application Note [6], and placed on the left side of the board. This area is reserved for non-

critical components like surface mount LEDs and GPIO. By routing power and ground from top

to bottom and branching off where necessary, we avoid loops that could result in EMI. Wherever


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possible, power traces avoid routes underneath or parallel to signals or other components. More

sensitive circuits, like Ethernet and the oscillator, are intentionally avoided [2]. Smaller power

and ground traces sprout out where necessary for individual components.

The Freescale 9S12NE64 and the Max3322 both connect to the ground traces through

bypass capacitors. Where possible, capacitors are placed to sit between and as close as possible

to these traces their respective component. Shorter trace length reduces interference. Larger

traces, 30 mils, are routed when connecting larger groups of bypass capacitors.

All components on the device operate at 3.3V, only a single network of power traces is

routed. This network is kept regulated by a Fairchild KA278R33 low dropout voltage regulator

[1]. This component can provide up to 2A at 3.3V, which is well above our current requirements.

A surface-mount fuse is attached near the power header to protect the device from shorts. Both

of these devices are located close to the power headers.

5.0 Summary

The pin configuration of the microcontroller and organization of the device schematic

helped to guide the general component placement, and a number of significant design choices

were made to accommodate these components’ requirements. Safely routing power, ground, and

logic traces to avoid sensitive components, interference, and overall confusion became an

iterative process leading to a clean and well-spaced PCB. Apart from the maximum size of 60

in2, the design was not limited by size, but efforts were made to make the best possible use of our

area.


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List of References

[1] Fairchild Semiconductor, “KA278RXXC-Series 2A Output Low Dropout VoltageRegulators,” [Online Document], 2005, [cited 21 February 2008], Available:http://www.fairchildsemi.com/ds/KA/KA278R05C.pdf

[2] Meyer, D.G., “PCB Fabrication Process and Layout Basics,” [Online Document], 2007,[cited 20 February 2008], Available:http://cobweb.ecn.purdue.edu/~dsml/ece477/Notes/PDF/Mod9.pdf

[3] Freescale Semiconductor, “MC9S12NE64,” [Online Document], 2004, [cited 21 February2008], Available: http://www.freescale.com/files/microcontrollers/doc/fact_sheet/

MC9S12NE64FS.pdf. [

[4] Maxim, “MAX3322E/MAX3323E,” [Online document], February 2003, [cited 20 February2008], Available: http://pdf1.alldatasheet.com/datasheet-

pdf/view/125433/MAXIM/MAX3322E/datasheet.pdf

[5] Joez Garage, “PCB Trace Amperage Chart,” [Online Document], [cited 21 February 2008],Available: http://www.joezgarage.com/PCB%20Trace%20Width%20Calculator.htm

[6] Motorola, “Application Note AN1259: System Design and Layout Techniques for NoiseReduction in MCU-Based Systems,” [Online Document], 1995, [cited 21 February 2008],Available:http://cobweb.ecn.purdue.edu/~dsml/ece477/Homework/CommonRefs/AN1259.pdf


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Appendix A: Design Schematic (2/21/08)


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Appendix B: PCB Layout (2/21/08)

homework 6: printed circuit board layout design … 477 digital systems senior design project spring...

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