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Homework #5A bit error rate tester (BERT)

Chris Allen (callen@eecs.ku.edu)

Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm

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A bit error rate tester (BERT)A Bit Error Rate Tester (BERT), also known as Bit Error Ratio Tester is

an electronic test instrument used to test a component or system’s signal transmission fidelity.

Using a sequence of logical ones and zeros generated by a pseudo-random binary sequencer, a BERT compares the received signals against the know binary sequence to detect bit errors.

The main building blocks of a Bit Error Rate Tester are:

• Pattern Generator, which transmits a defined test pattern to the DUT or test system

• Error Detector connected to the DUT or test system, to count the errors generated by the DUT or test system

• Clock signal generator to synchronize the pattern gen-erator and the error detector

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A bit error rate tester (BERT)Design shows implementation using GigaBit Logic componentsAssignment requires use

of Synergy/Micrel ECL components

Assignment involvesSchematicBoard stackupLayoutTiming analysis, max clock freqSupply current analysisBill of materialsCooling analysis