Hitendra DivechaSr. Product Marketing Manager

SSV SummitNovember 21st, 2013

QRC Extraction

2 © 2013 Cadence Design Systems, Inc. All rights reserved.

Foundry Certified, Signoff Extraction Tool

QRC Extraction

One Tool Supports Digital and Transistor FlowsUsing

Single Technology File

Best and Fastest Convergence in Encounter® and Virtuoso®

Leader in Custom/Analog Designs Extraction

Production Proven; Better Accuracy down to FF in 13.1

Fastest Single Corner and Multi-Corner Extraction Performance in 13.1

Leader in supporting technology nodes down to 16/14nm FinFET Extraction

3 © 2013 Cadence Design Systems, Inc. All rights reserved.

Tightly Integrated in EDI Providing Best TATand Convergence

Turbo QRC (TQRC)

• Not a signoff quality!• Run multi-corner extraction• Upto 2-3x faster than signoff

Integrated QRC (IQRC)

• Used for ECOs/Incremental extraction

• Faster than signoff—extract only changed nets

• Used for accurate CLK/NDR nets for 28nm designs and below

• Multi-corner extraction

Signoff QRC• Full blown, Foundry Qualified including QRC Field Solver (QRCFS)

• Multi-corner extraction

Same QRC

Engine

Silicon Virtual Prototype

Power Routing

Clock Tree Synthesis

Post-CTS Optimization

Placement

Power Grid Synthesis

Routing

Post-Route Timing/SI Optimization

Signoff Extraction

Timing, SI, PowerSign-off

Signoff Extraction

Post-Route Timing/SI Optimization

Single-click execution within EDI for all extraction modes!

4 © 2013 Cadence Design Systems, Inc. All rights reserved.

Integrated with Virtuoso®

Faster design closure for custom blocks and top level

QRC Extracted ViewUltimate design / debug environment for custom designers

Extracted View•Integrated with Virtuoso®•LVS View Supports PVS, Assura, Calibre

Design Debug Environment•Back Annotation•Schematic-Layout Cross-probing

Simulation Analysis•Integrated with Virtuoso ADE•Easy simulation debug

EMIR Analysis• Accurate IR Drop Analysis • Gen models for cell based analysis• Supports VPS-L

5 © 2013 Cadence Design Systems, Inc. All rights reserved.

Supports all Design Types with Industry-Leading Functionality

Substrate Noise Analysis (SNA)• Full 3D substrate model• Full chip and block level• Tightly integrated in Virtuoso

Inductance Extraction• Support PEEC method• Sweep from DC100GHz• Supports mutual and Self inductance

MeshR• Used for PowerMos/LCD • Better accuracy for all irregular or wide metal shapes

RLCK Reduction• Supports RC and RCLK redux• 20x simulation time reduction,

with 5% accuracy• 2.4x total TAT—good accuracy

Custom/Analog and RF Designs

Serdes

IP/SRAM/Bitcell Characterization

Memory, PowerMos, Image Sensors, etc.

6 © 2013 Cadence Design Systems, Inc. All rights reserved.

QRC Extraction—Complete FinFET Extraction Solution

• Strong collaboration with TSMC to deliver parasitic models to our mutual customers

• Key differentiators1. Unmatched accuracy

− Built upon robust 3D modeling framework

− Best cap. and timing accuracy vs TSMC Golden

2. Unmatched post layout simulationturnaround time (TAT)

− Best netlist size and simulation time for a VCO design− 2X smaller netlist− 2.5X faster simulation runtime

3. Tight integration in Virtuoso for faster design convergence

QRC Extraction & QRC Field Solver (QRCFS)

16nm FinFET

SRAMCharacterizati

on

QR

CF

S Bitcell Characterizati

onQ

RC

Std. Cells

Characterization

Signoff for

Digital & Custom/Analog Designs

DAC 2013

16FF V0.5 Techfiles Available Now!

8 © 2013 Cadence Design Systems, Inc. All rights reserved.

Key Benefits of EXT13.1 Release

Delivers ~1.5X-2X better performance than competition- Including ~4X improvement over 12.1.01

Delivers tighter accuracy against field solver for all advanced node designs- Slightly conservative with mean, on average, closer to 0 for most advanced node designs

Delivers industry-leading functionality to support FinFET/FDSOI designs- Unmatched accuracy vs Golden at TSMC- 2.5X faster simulation runtime- Faster design convergence in Virtuoso using Cgs flow

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