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HTG-A100 User Manual
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HiTech Global Arria10™ PCI Express Development Platform
HTG-A100 User Manual
Version 1.0 January 2016 Copyright © HiTech Global 2002-2016
HTG-A100 User Manual
www.HiTechGlobal.com
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Disclaimer
HiTech Global does not assume any liability arising out of the application or use of any product described or shown
herein; nor does it convey any license under its patents, copyrights, or mask work rights or any rights of others.
HiTech Global reserves the right to make changes, at any time, in order to improve reliability and functionality of
this product. HiTech Global will not assume responsibility for the use of any circuitry described herein other than
circuitry entirely embodied in its products. HiTech Global provides any design, code, or information shown or
described herein "as is." By providing the design, code, or information as one possible implementation of a feature,
application, or standard, HiTech Global makes no representation that such implementation is free from any claims of
infringement. End users are responsible for obtaining any rights they may require for their implementation. HiTech
Global expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation,
including but not limited to any warranties or representations that the implementation is free from claims of
infringement, as well as any implied warranties of merchantability or fitness for a particular purpose.
HiTech Global will not assume any liability for the accuracy or correctness of any engineering or software support
or assistance provided to a user. HiTech Global products are not intended for use in life support appliances, devices,
or systems. Use of a HiTech Global product in such applications without the written consent of the appropriate
HiTech Global officer is prohibited.
The contents of this manual are owned and copyrighted by HiTech Global Copyright. HiTech Global All Rights
Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished,
downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic,
mechanical, photocopying, recording, or otherwise, without the prior written consent of HiTech Global. Any
unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Revision History
Date Version Notes
1/15/2016 1.0
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Table Of Contents
Chapter 1 - Introduction to HTG-A100 4
1.1) Overview 4
Chapter 2 – Development Platform Introduction 5
2.1) Introduction 5
2.2) Features & Block Diagram 5
2.3) Clock Distribution 7
2.4) PCI Express 9
2.5) DDR 4 Memory 12
2.6) FPGA Mezzanine Card Interfaces (FMC) 17
2.7) Z-RAY High-Speed Serial Bus 30
2.8) QSE Board-To-Board Port 34
2.9) USB To UART Bridge 35
2.10) LEDs, GPIO Headers & Pushbuttons 36
2.11) I2C Bus Switch 36
2.12) Configuration 37
2.13) IP Protection 38
Chapter 3 – Mezzanine Cards 39
3.1) Z-RAY Modules 39
3.2) FMC Modules 40
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Chapter 1: Introduction to Altera Arria 10FPGAs
1.1) Overview
The Arria® 10 device family includes three variants:
Arria 10 GT FPGAs: Up to 96 full-duplex optimized transceivers with data rates up to 28.1 Gbps chip-to-
chip, and up to 1150K equivalent logic elements (LEs)
Arria 10 GX FPGAs: Up to 96 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0
Gbps backplane, and up to 1150K equivalent LEs
Arria 10 SX SoCs: Integrated ARM® Cortex
®-A9 hard processor systems (HPS) with up to 48 full-duplex
transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 660K equivalent
LEs
Table (1) illustrates key features of the Arria10 devices supported by the HTG-A100 platform.
GX 570 GX 660 GX 900 GX 1150
SX 570 SX 660
Part number reference 10AX057 /
10AS057
10AX066 /
10AS066 10AX090 10AX115
Logic elements (K) 570 660 900 1,150
Adaptive logic modules (ALMs) 217,080 250,540 339,620 427,200
Registers 868,320 1,002,160 1,358,480 1,708,800
M20K memory blocks 1,800 2,133 2,423 2,713
M20K memory (Mb) 35 42 47 53
MLAB memory (Mb) 5.0 5.7 9.2 12.7
Hardened single-precision floating-
point multipliers/adders 1,523/1,523 1,688/1,688 1,518/1,518 1,518/1,518
18 x 19 multipliers 3,046 3,376 3,036 3,036
Peak GMACS 3,351 3,714 3,340 3,340
Peak giga floating-point operation
per second (GFLOPS) 1,371 1,519 1,366 1,366
Regional clocks 8 16 16 16
Maximum LVDS channels (1.6 G) 270 270 384 384
Maximum user I/O pins 624 624 768 768
Transceiver count (17.4 Gbps) 48 48 96 96
Transceiver count (28 Gbps) – – – –
PCI Express® hard IP blocks (Gen3) 2 2 4 4
Maximum 3 V I/O pins 48 48 – –
Table (1): Summary of Arria 10 FPGA Features
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Chapter 2: HTG-A100 Development Platform Introduction
◙ 2.1) Introduction
Supported by Altera Arria 10AX057, 10AX066, 10AX090, 10AX115, 10AS057 and 10AS066 FPGA devices and
wide variety of expansion modules, the HTG-A100 platform is ideal for all applications requiring high performance
Altera FPGA programmability.
Modular architecture of the HTG-A100 Arria 10 platform provides great level of versatility through two industry
standard Vita57.1 FPGA Mezzanine Connectors (FMC) and one Z-RAY High-Speed Bus using Samtec Z-Ray
connector (ZSP). Two High-Pin-Count (HPC) FMC connectors provide access to 320 single-ended I/Os and 20
high-speed Serial Transceivers of the onboard Arria 10 FPGA. The Z-RAY High-Speed Serial Bus provides access
to sixteen Serial Transceivers, single-ended I/O pins for control functions, programmable clock and adjustable
power supplies for daughter cards such as Hybrid Memory Cube (HMC), QSFP+, SFP+, SMA breakout, and re-
timer/gearbox interfaces (CFP4, QSFP28, etc.)
HiTech Global also offers 100Gig Ethernet MAC and PCS (10x10 and 4x28) IP core for high-speed networking
applications.
◙ 2.2) Features
The key features of the HTG-A100 platforms include:
►Altera Arria 10 GX570, GX660, GX900, GX1150, SX570, and SX660
►x8 PCI Express Gen3
► x2 FPGA Mezzanine Connector (FMC) High Pin Count (HPC) each with 160 single-ended I/Os (total of 320)
and 10 (total of 20) Serial Transceivers
► High Speed bus with 16 Serial Transceivers, control I/Os, and 12.V and 3.3V power pins
- Available Modules:
Hybrid Memory Cube (HMC), SFP+, QSFP+, 100G Gearbox (QSFP28, CFP4,
CFP2), SMA breakout, Samtec FireFly
► DDR4 Components (2.5GB)
► Configuration Flash
► USB/UART
► Programmable Clocks
► GPIO Headers
► JTAG Header
► PCI Express or Standalone operational modes
► Size: 6.6" x 4.25"
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High-level block diagram of the HTG-A100 platforms are illustrated by figure (1).
Figure (1): Block Diagram
Common footprint of the GX570, GX660, GX900, GX1150, SX570, and SX660 package allows usage of one PCB
for all 4 devices. FPGA bank assignment for each interface is illustrated by figure (3).
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Figure (3): Arria 10FPGA Bank Assignment
◙ 2.3) Clock Distribution
For effective utilization of the FPGA resources, the HTG-A100 platforms are supported by different low-jitter /
high-performance crystal oscillators. Figure (4) and table (2) illustrate the platform’s clock diagram.
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Figure (4): Clock Diagram
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Reference Designator Oscillator Part Number Oscillator Description
U13 8N4Q001LG-0055CDI Z-RAY Bus /FMC I2C Programmable XO
with default value of 156.25MHz
U22 8N4Q001LG-0139CDI FPGA Reference I2C Programmable XO
with default value of 200MHz
U20 8N4Q001LG-0078CDI DDR4 I2C Programmable XO with default
value of 300MHz
U36 CFPS-31-100.0MHz CPLD Clock (100MHz)
Table (2): Clock Summary
◙ 2.4) PCI Express
Altera Arria 10FPGAs support Integrated Root Port and Endpoint for PCI Express solution. The unified architecture
of the blocks provides easy migration and design reuse across all supported devices.
The HTG-A100 provides 8 lanes of PCI Express Gen3 (with hard macro controller inside the FPGA) interface
through eight serial transceivers.
Table (3) illustrates FPGA pins assignment for the PCI Express signals.
FPGA Signal Name FPGA Pin Number
PCIE_CLK0_MGT_N AE28
PCIE_CLK0_MGT_P AE29
PCIE_CLK1_MGT_N AA28
PCIE_CLK1_MGT_P AA29
PCIE_PERST_N_F AU4
PCIE_RX[0]_N AE32
PCIE_RX[0]_P AE33
PCIE_RX[1]_N AD30
PCIE_RX[1]_P AD31
PCIE_RX[2]_N AD34
PCIE_RX[2]_P AD35
PCIE_RX[3]_N AC32
PCIE_RX[3]_P AC33
PCIE_RX[4]_N AB30
PCIE_RX[4]_P AB31
PCIE_RX[5]_N AB34
PCIE_RX[5]_P AB35
PCIE_RX[6]_N AA32
PCIE_RX[6]_P AA33
PCIE_RX[7]_N Y34
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PCIE_RX[7]_P Y35
PCIE_TX[0]_N AG36
PCIE_TX[0]_P AG37
PCIE_TX[1]_N AF38
PCIE_TX[1]_P AF39
PCIE_TX[2]_N AE36
PCIE_TX[2]_P AE37
PCIE_TX[3]_N AD38
PCIE_TX[3]_P AD39
PCIE_TX[4]_N AC36
PCIE_TX[4]_P AC37
PCIE_TX[5]_N AB38
PCIE_TX[5]_P AB39
PCIE_TX[6]_N AA36
PCIE_TX[6]_P AA37
PCIE_TX[7]_N Y38
PCIE_TX[7]_P Y39
PCIE_WAKE_N_F AW5
Table (3): PCI Express FPGA Pin Assignments
2.4.1) PCI Express Clock
To provide a clean clock with the lowest possible jitter for the PCI Express interface, the HTG-A100 platform is
supported by IDT PCI Express Jitter Attenuator chip (ICS871S1022EKLF). The chip (U1) provides cleaned / jitter-
reduced 100MHz or 250MHz clocks for the PCI Express interface. Figure (5) illustrates clock circuit of the PCI
Express components.
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Figure (5): PCI Express Clock Circuit
Output clock frequency of the PCI Express Jitter Attenuator (U1) is controlled by logic state of the N0 (through
R281 and R283 resistors) and N1(through R282 and R284 resistors) as shown by table (4) and figure (6).
Inputs Outputs
In (MHz) N1:N0 N Divider
100 00 5 100MHz
100 01 4 125MHz
100 10 2 250MHz
100 11 1 500MHz
Table (4): Jitter Attenuator Mode Selection
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Figure (6): Jitter Attenuator Mode Select Resistor Setting
◙ 2.5) DDR-4 Memory Interface
The HTG-A100 platform is populated with five 256 Mb x 16 DDR4 components (Micron EDY4016AABG-DR-F)
providing total memory density of 2.5GB. The memory components are connected to the FPGA’s banks 3F, 3G and
3FH
Table (5) illustrates the FPGA bank assignment for the DDR4 interface.
FPGA Signal Name FPGA Pin Number
DDR4_A[0] H6
DDR4_A[1] J6
DDR4_A[10] H8
DDR4_A[11] H9
DDR4_A[12] E6
DDR4_A[13] D4
DDR4_A[14] D5
DDR4_A[15] E7
DDR4_A[16] F7
DDR4_A[2] G7
DDR4_A[3] H7
DDR4_A[4] G5
DDR4_A[5] G6
DDR4_A[6] J8
DDR4_A[7] K8
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DDR4_A[8] F9
DDR4_A[9] G9
DDR4_ACT_N J10
DDR4_ALERT_N M5
DDR4_BA[0] D3
DDR4_BA[1] C3
DDR4_BG[0] C4
DDR4_CK_C K11
DDR4_CK_T J11
DDR4_CKE M12
DDR4_CS_N J9
DDR4_DM_DBI_N[0] N6
DDR4_DM_DBI_N[1] F4
DDR4_DM_DBI_N[2] L3
DDR4_DM_DBI_N[3] P9
DDR4_DM_DBI_N[4] K12
DDR4_DM_DBI_N[5] H13
DDR4_DM_DBI_N[6] G12
DDR4_DM_DBI_N[7] B12
DDR4_DM_DBI_N[8] C7
DDR4_DQ[0] K7
DDR4_DQ[1] L4
DDR4_DQ[10] E2
DDR4_DQ[11] E1
DDR4_DQ[12] D1
DDR4_DQ[13] F2
DDR4_DQ[14] G2
DDR4_DQ[15] G1
DDR4_DQ[16] J3
DDR4_DQ[17] J5
DDR4_DQ[18] H1
DDR4_DQ[19] H3
DDR4_DQ[2] L7
DDR4_DQ[20] K3
DDR4_DQ[21] H4
DDR4_DQ[22] J1
DDR4_DQ[23] J4
DDR4_DQ[24] M9
DDR4_DQ[25] N8
DDR4_DQ[26] L8
DDR4_DQ[27] L9
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DDR4_DQ[28] R10
DDR4_DQ[29] P10
DDR4_DQ[3] K5
DDR4_DQ[30] R11
DDR4_DQ[31] P11
DDR4_DQ[32] J14
DDR4_DQ[33] P14
DDR4_DQ[34] L12
DDR4_DQ[35] L13
DDR4_DQ[36] J13
DDR4_DQ[37] P15
DDR4_DQ[38] M14
DDR4_DQ[39] N14
DDR4_DQ[4] N7
DDR4_DQ[40] C13
DDR4_DQ[41] H14
DDR4_DQ[42] D13
DDR4_DQ[43] C14
DDR4_DQ[44] D14
DDR4_DQ[45] G14
DDR4_DQ[46] F13
DDR4_DQ[47] F14
DDR4_DQ[48] F12
DDR4_DQ[49] C11
DDR4_DQ[5] M4
DDR4_DQ[50] E11
DDR4_DQ[51] E10
DDR4_DQ[52] G11
DDR4_DQ[53] D10
DDR4_DQ[54] D11
DDR4_DQ[55] C12
DDR4_DQ[56] B11
DDR4_DQ[57] B10
DDR4_DQ[58] C9
DDR4_DQ[59] A9
DDR4_DQ[6] K6
DDR4_DQ[60] A10
DDR4_DQ[61] A8
DDR4_DQ[62] B9
DDR4_DQ[63] A7
DDR4_DQ[64] F8
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DDR4_DQ[65] B5
DDR4_DQ[66] D8
DDR4_DQ[67] B7
DDR4_DQ[68] E8
DDR4_DQ[69] A5
DDR4_DQ[7] L5
DDR4_DQ[70] C8
DDR4_DQ[71] A4
DDR4_DQ[8] C1
DDR4_DQ[9] G4
DDR4_DQS_C[0] M7
DDR4_DQS_C[1] F3
DDR4_DQS_C[2] K2
DDR4_DQS_C[3] R8
DDR4_DQS_C[4] L15
DDR4_DQS_C[5] E13
DDR4_DQS_C[6] G10
DDR4_DQS_C[7] A13
DDR4_DQS_C[8] C6
DDR4_DQS_T[0] M6
DDR4_DQS_T[1] E3
DDR4_DQS_T[2] K1
DDR4_DQS_T[3] P8
DDR4_DQS_T[4] L14
DDR4_DQS_T[5] E12
DDR4_DQS_T[6] F10
DDR4_DQS_T[7] A12
DDR4_DQS_T[8] B6
DDR4_ODT M10
DDR4_PAR L10
DDR4_RST_N N12
DDR4_TEN N11
SYS_CLK_DDR4_N F5
SYS_CLK_DDR4_P E5
Table (5): DDR4 Memory FPGA Pin Assignment
2.5.1) DDR4 Clock
As illustrated by figure (7), clock for the DDR4 interface is generated by the high-performance low-jitter IDT
8N4Q001LG-0078CDI programmable crystal (U20). This oscillator holds up to four factory pre- programmed
frequencies that are selectable through resistor settings of the FSEL [1:0] pins as shown by table (6). The default
frequency of the U20 is set to 300MHz. The oscillator can also be programmed by the FPGA for different
frequencies through the associated I2C bus.
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FSEL [1:0] =00
(R158 & R157)
FSEL [1:0] =01
(R158 & R157)
FSEL [1:0] =10
(R158 & R157)
FSEL [1:0] =11
(R158 & R157)
1st Frequency 2
nd Frequency 3
rd Frequency 4
th Frequency
100 200 300 (default) 400
Table (6): DDR4 Pre-Programmed Frequency Selection
Figure (7): DDR4 Clock Circuit
The ICS8N4Q001 is a Quad-Frequency Programmable Clock Oscillator with very flexible frequency programming
and delivers excellent phase noise performance at <0.5 ps rms 1kHz - 20MHz. The device uses IDT’s fourth
generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance,
combined with high power supply noise rejection. The device accepts 2.5V or 3.3V supply and is packaged in a
small, lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package. Besides the 4 default power-up
frequencies set by the FSEL0 and FSEL1 pins, the ICS8N4Q001 can be programmed via the I2C interface to output
clock frequencies between 15.476 to 866.67MHz and from 975 to 1,300MHz to a very high degree of precision with
a frequency step size of 435.9Hz ÷ N (N: PLL post divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL M and N divider registers (P, MINT, MFRAC and N), reprogramming those registers to other
frequencies under control of FSEL0 and FSEL1 is supported.
Additional product information is available at http://www.idt.com/document/dst/idt8n4q001-datasheet
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◙ 2.6) FPGA Mezzanine Card Interfaces
The HTG-A100 platform is populated with two 400-pin Samtec connectors (J6 & J4) for High Pin Count (HPC)
implementation of Vita 57.1 FPGA Mezzanine Card (FMC) interface. The Vita57.1 calls for fixed location of I/Os,
Power, Clocks, and Jtag signals so any compliant module can easily be pluggable into any compliant carrier card.
Each HPC FMC connector provides access to 160 singled ended I/Os, 10 Serial Transceivers , JTAG signals,
Voltage adjustable supplies, I2C signals, and multiple differential clocks.
J4 is located at the front panel side and J6 at the upper right corner of the platform.
HiTech Global provides the following add-on FMC modules with CX4, SFP, SFP+, QSFP28, QSFP+, SATA, SMA,
RJ45, PCI Express Root, AD/DA, and high-end processor. Additional information for the HiTech Global’s FMC
modules is available at:
http://www.hitechglobal.com/Accessories/FMC_Modules.htm
Figure (8) illustrates FPGA Carrier Card connector (Samtec Part # ASP-134486-01) grid labeling (used on the
HTG-A100 platform)
Figure (8): Carrier Card Connector Grid Labeling
Figure (9) illustrates FMC Module connector (Samtec Part # ASP-134488-01) grid labeling (used on the HTG-
FMC-xxx modules)
Figure (9): FMC Module Connector Grid Labeling
The ASP-134488-01 connectors are available for purchase at:
https://hitechglobal.us/index.php?route=product/product&path=25&product_id=59
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FMC to FMC cables are also available for connecting the HTG-A100 platforms to each other or similar Vita57.1
compliant carrier boards or modules. The FMC to FMC cables are available with lengths of 5” and 9”.
Additional information is available at http://hitechglobal.com/FMCModules/FMC_Cable.htm
Image (1) illustrates approximate bend radius for a 9” FMC to FMC cable.
Image (1): FMC To FMC Cable
Table (7) illustrates the exact location of the fixed functional pins on a High Pin Count (HPC) FMC connector.
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K J H G F E D C B A
VREF_B_M2C GND VREF_A_M2C GND PG_M2C GND PG_C2M GND CLK_DIR GND
GND CLK3_BIDIR_P PRSNT_M2C_L CLK1_M2C_P GND HA01_P_CC GND DP0_C2M_P GND DP1_M2C_P
GND CLK3_BIDIR_N GND CLK1_M2C_N GND HA01_N_CC GND DP0_C2M_N GND DP1_M2C_N
CLK2_BIDIR_P GND CLK0_M2C_P GND HA00_P_CC GND GBTCLK0_M2C_P GND DP9_M2C_P GND
CLK2_BIDIR_N GND CLK0_M2C_N GND HA00_N_CC GND GBTCLK0_M2C_N GND DP9_M2C_N GND
GND HA03_P GND LA00_P_CC GND HA05_P GND DP0_M2C_P GND DP2_M2C_P
HA02_P HA03_N LA02_P LA00_N_CC HA04_P HA05_N GND DP0_M2C_N GND DP2_M2C_N
HA02_N GND LA02_N GND HA04_N GND LA01_P_CC GND DP8_M2C_P GND
GND HA07_P GND LA03_P GND HA09_P LA01_N_CC GND DP8_M2C_N GND
HA06_P HA07_N LA04_P LA03_N HA08_P HA09_N GND LA06_P GND DP3_M2C_P
HA06_N GND LA04_N GND HA08_N GND LA05_P LA06_N GND DP3_M2C_N
GND HA11_P GND LA08_P GND HA13_P LA05_N GND DP7_M2C_P GND
HA10_P HA11_N LA07_P LA08_N HA12_P HA13_N GND GND DP7_M2C_N GND
HA10_N GND LA07_N GND HA12_N GND LA09_P LA10_P GND DP4_M2C_P
GND HA14_P GND LA12_P GND HA16_P LA09_N LA10_N GND DP4_M2C_N
HA17_P_CC HA14_N LA11_P LA12_N HA15_P HA16_N GND GND DP6_M2C_P GND
HA17_N_CC GND LA11_N GND HA15_N GND LA13_P GND DP6_M2C_N GND
GND HA18_P GND LA16_P GND HA20_P LA13_N LA14_P GND DP5_M2C_P
HA21_P HA18_N LA15_P LA16_N HA19_P HA20_N GND LA14_N GND DP5_M2C_N
HA21_N GND LA15_N GND HA19_N GND LA17_P_CC GND GBTCLK1_M2C_P GND
GND HA22_P GND LA20_P GND HB03_P LA17_N_CC GND GBTCLK1_M2C_N GND
HA23_P HA22_N LA19_P LA20_N HB02_P HB03_N GND LA18_P_CC GND DP1_C2M_P
HA23_N GND LA19_N GND HB02_N GND LA23_P LA18_N_CC GND DP1_C2M_N
GND HB01_P GND LA22_P GND HB05_P LA23_N GND DP9_C2M_P GND
HB00_P_CC HB01_N LA21_P LA22_N HB04_P HB05_N GND GND DP9_C2M_N GND
HB00_N_CC GND LA21_N GND HB04_N GND LA26_P LA27_P GND DP2_C2M_P
GND HB07_P GND LA25_P GND HB09_P LA26_N LA27_N GND DP2_C2M_N
HB06_P_CC HB07_N LA24_P LA25_N HB08_P HB09_N GND GND DP8_C2M_P GND
HB06_N_CC GND LA24_N GND HB08_N GND TCK GND DP8_C2M_N GND
GND HB11_P GND LA29_P GND HB13_P TDI SCL GND DP3_C2M_P
HB10_P HB11_N LA28_P LA29_N HB12_P HB13_N TDO SDA GND DP3_C2M_N
HB10_N GND LA28_N GND HB12_N GND 3P3VAUX GND DP7_C2M_P GND
GND HB15_P GND LA31_P GND HB19_P TMS GND DP7_C2M_N GND
HB14_P HB15_N LA30_P LA31_N HB16_P HB19_N TRST_L GA0 GND DP4_C2M_P
HB14_N GND LA30_N GND HB16_N GND GA1 12P0V GND DP4_C2M_N
GND HB18_P GND LA33_P GND HB21_P 3P3V GND DP6_C2M_P GND
HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N GND 12P0V DP6_C2M_N GND
HB17_N_CC GND LA32_N GND HB20_N GND 3P3V GND GND DP5_C2M_P
GND VIO_B_M2C GND VADJ GND VADJ GND 3P3V GND DP5_C2M_N
VIO_B_M2C GND VADJ GND VADJ GND 3P3V GND RES0 GND
LPC Connector LPC Connector LPC Connector LPC
Connector
Table (7): Vita57.1 FMC Pin Assignment
Table (8) illustrates FPGA pin assignment for the FMC_A (J4) connector located at the front panel side:
FPGA Signal Name FPGA Pin Number
FMC_A_CLK[0]_M2C_N AL10
FMC_A_CLK[0]_M2C_P AM10
FMC_A_CLK[1]_M2C_N AM5
FMC_A_CLK[1]_M2C_P AN4
FMC_A_DP[0]_C2M_N AP38
FMC_A_DP[0]_C2M_P AP39
FMC_A_DP[0]_M2C_N AK34
FMC_A_DP[0]_M2C_P AK35
FMC_A_DP[1]_C2M_N AN36
FMC_A_DP[1]_C2M_P AN37
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FMC_A_DP[1]_M2C_N AJ32
FMC_A_DP[1]_M2C_P AJ33
FMC_A_DP[2]_C2M_N AR36
FMC_A_DP[2]_C2M_P AR37
FMC_A_DP[2]_M2C_N AL32
FMC_A_DP[2]_M2C_P AL33
FMC_A_DP[3]_C2M_N AT38
FMC_A_DP[3]_C2M_P AT39
FMC_A_DP[3]_M2C_N AM34
FMC_A_DP[3]_M2C_P AM35
FMC_A_DP[4]_C2M_N AP34
FMC_A_DP[4]_C2M_P AP35
FMC_A_DP[4]_M2C_N AK30
FMC_A_DP[4]_M2C_P AK31
FMC_A_DP[5]_C2M_N AV38
FMC_A_DP[5]_C2M_P AV39
FMC_A_DP[5]_M2C_N AP30
FMC_A_DP[5]_M2C_P AP31
FMC_A_DP[6]_C2M_N AV34
FMC_A_DP[6]_C2M_P AV35
FMC_A_DP[6]_M2C_N AR32
FMC_A_DP[6]_M2C_P AR33
FMC_A_DP[7]_C2M_N AW32
FMC_A_DP[7]_C2M_P AW33
FMC_A_DP[7]_M2C_N AU32
FMC_A_DP[7]_M2C_P AU33
FMC_A_DP[8]_C2M_N AW36
FMC_A_DP[8]_C2M_P AW37
FMC_A_DP[8]_M2C_N AT30
FMC_A_DP[8]_M2C_P AT31
FMC_A_DP[9]_C2M_N AU36
FMC_A_DP[9]_C2M_P AU37
FMC_A_DP[9]_M2C_N AN32
FMC_A_DP[9]_M2C_P AN33
FMC_A_GBTCLK[0]_M2 AJ29
FMC_A_GBTCLK[0]_M2 AJ28
FMC_A_GBTCLK[1]_M2 AN29
FMC_A_GBTCLK[1]_M2 AN28
FMC_A_HA[0]_CC_N AG6
FMC_A_HA[0]_CC_P AG5
FMC_A_HA[1]_CC_N AG7
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FMC_A_HA[1]_CC_P AH7
FMC_A_HA[10]_N AF10
FMC_A_HA[10]_P AF9
FMC_A_HA[11]_N AK5
FMC_A_HA[11]_P AL5
FMC_A_HA[12]_N AL4
FMC_A_HA[12]_P AL3
FMC_A_HA[13]_N AM4
FMC_A_HA[13]_P AN3
FMC_A_HA[14]_N AE11
FMC_A_HA[14]_P AE10
FMC_A_HA[15]_N AE8
FMC_A_HA[15]_P AF8
FMC_A_HA[16]_N AE7
FMC_A_HA[16]_P AF7
FMC_A_HA[17]_CC_N AH6
FMC_A_HA[17]_CC_P AJ5
FMC_A_HA[18]_CC_N AJ4
FMC_A_HA[18]_CC_P AK3
FMC_A_HA[19]_N AJ6
FMC_A_HA[19]_P AK6
FMC_A_HA[2]_N AH3
FMC_A_HA[2]_P AJ3
FMC_A_HA[20]_N AK2
FMC_A_HA[20]_P AK1
FMC_A_HA[21]_N AC11
FMC_A_HA[21]_P AD10
FMC_A_HA[22]_N AD9
FMC_A_HA[22]_P AD8
FMC_A_HA[23]_N AC9
FMC_A_HA[23]_P AC8
FMC_A_HA[3]_N AF5
FMC_A_HA[3]_P AF4
FMC_A_HA[4]_N AG4
FMC_A_HA[4]_P AH4
FMC_A_HA[5]_N AH2
FMC_A_HA[5]_P AJ1
FMC_A_HA[6]_N AL2
FMC_A_HA[6]_P AM2
FMC_A_HA[7]_N AN1
FMC_A_HA[7]_P AM1
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FMC_A_HA[8]_N AR2
FMC_A_HA[8]_P AR1
FMC_A_HA[9]_N AN2
FMC_A_HA[9]_P AP1
FMC_A_HB[0]_CC_N AN26
FMC_A_HB[0]_CC_P AP26
FMC_A_HB[1]_N AM24
FMC_A_HB[1]_P AL24
FMC_A_HB[10]_N AR26
FMC_A_HB[10]_P AT26
FMC_A_HB[11]_N AV28
FMC_A_HB[11]_P AW28
FMC_A_HB[12]_N AU27
FMC_A_HB[12]_P AU28
FMC_A_HB[13]_N AV26
FMC_A_HB[13]_P AV27
FMC_A_HB[14]_N AK26
FMC_A_HB[14]_P AL26
FMC_A_HB[15]_N AL25
FMC_A_HB[15]_P AM25
FMC_A_HB[16]_N AU25
FMC_A_HB[16]_P AU26
FMC_A_HB[17]_CC_N AP23
FMC_A_HB[17]_CC_P AP24
FMC_A_HB[18]_N AJ23
FMC_A_HB[18]_P AJ24
FMC_A_HB[19]_N AK23
FMC_A_HB[19]_P AL23
FMC_A_HB[2]_N AJ25
FMC_A_HB[2]_P AK25
FMC_A_HB[20]_N AH23
FMC_A_HB[20]_P AH24
FMC_A_HB[21]_N AH25
FMC_A_HB[21]_P AJ26
FMC_A_HB[3]_N AF25
FMC_A_HB[3]_P AG25
FMC_A_HB[4]_N AT24
FMC_A_HB[4]_P AT25
FMC_A_HB[5]_N AN23
FMC_A_HB[5]_P AN24
FMC_A_HB[6]_CC_N AT23
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FMC_A_HB[6]_CC_P AU24
FMC_A_HB[7]_N AV24
FMC_A_HB[7]_P AW24
FMC_A_HB[8]_N AW25
FMC_A_HB[8]_P AW26
FMC_A_HB[9]_N AV23
FMC_A_HB[9]_P AW23
FMC_A_LA[0]_CC_N AP11
FMC_A_LA[0]_CC_P AR11
FMC_A_LA[1]_CC_N AN13
FMC_A_LA[1]_CC_P AN12
FMC_A_LA[10]_N AT10
FMC_A_LA[10]_P AT9
FMC_A_LA[11]_N AL12
FMC_A_LA[11]_P AM12
FMC_A_LA[12]_N AM11
FMC_A_LA[12]_P AN11
FMC_A_LA[13]_N AU9
FMC_A_LA[13]_P AV9
FMC_A_LA[14]_N AU11
FMC_A_LA[14]_P AU10
FMC_A_LA[15]_N AJ15
FMC_A_LA[15]_P AK15
FMC_A_LA[16]_N AL14
FMC_A_LA[16]_P AL13
FMC_A_LA[17]_CC_N AK10
FMC_A_LA[17]_CC_P AL9
FMC_A_LA[18]_CC_N AU2
FMC_A_LA[18]_CC_P AU1
FMC_A_LA[19]_N AP5
FMC_A_LA[19]_P AP4
FMC_A_LA[2]_N AK12
FMC_A_LA[2]_P AK11
FMC_A_LA[20]_N AP3
FMC_A_LA[20]_P AR3
FMC_A_LA[21]_N AM7
FMC_A_LA[21]_P AN7
FMC_A_LA[22]_N AT5
FMC_A_LA[22]_P AT4
FMC_A_LA[23]_N AT3
FMC_A_LA[23]_P AT2
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FMC_A_LA[24]_N AK8
FMC_A_LA[24]_P AL8
FMC_A_LA[25]_N AK7
FMC_A_LA[25]_P AL7
FMC_A_LA[26]_N AM6
FMC_A_LA[26]_P AN6
FMC_A_LA[27]_N AP6
FMC_A_LA[27]_P AR5
FMC_A_LA[28]_N AJ11
FMC_A_LA[28]_P AJ10
FMC_A_LA[29]_N AH8
FMC_A_LA[29]_P AJ8
FMC_A_LA[3]_N AT8
FMC_A_LA[3]_P AT7
FMC_A_LA[30]_N AG11
FMC_A_LA[30]_P AH11
FMC_A_LA[31]_N AH9
FMC_A_LA[31]_P AJ9
FMC_A_LA[32]_N AF12
FMC_A_LA[32]_P AG12
FMC_A_LA[33]_N AG10
FMC_A_LA[33]_P AG9
FMC_A_LA[4]_N AU7
FMC_A_LA[4]_P AV7
FMC_A_LA[5]_N AP8
FMC_A_LA[5]_P AR8
FMC_A_LA[6]_N AN9
FMC_A_LA[6]_P AP9
FMC_A_LA[7]_N AP10
FMC_A_LA[7]_P AR10
FMC_A_LA[8]_N AW10
FMC_A_LA[8]_P AW9
FMC_A_LA[9]_N AV8
FMC_A_LA[9]_P AW8
FMC_A_PG_M2C_F AV6
FMC_A_PRSNT_M2C_L_ AU5
Table (8): FMC_A Mezzanine Connector FPGA Pin Assignment
Table (9) illustrates FPGA pin assignment for the FMC_B (J6) connector located at the upper right side of the
platform.
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FPGA Signal Name FPGA Pin Number
FMC_B_CLK[0]_M2C_N W6
FMC_B_CLK[0]_M2C_P W5
FMC_B_CLK[1]_M2C_N AB6
FMC_B_CLK[1]_M2C_P AB5
FMC_B_DP[0]_C2M_N T38
FMC_B_DP[0]_C2M_P T39
FMC_B_DP[0]_M2C_N V30
FMC_B_DP[0]_M2C_P V31
FMC_B_DP[1]_C2M_N P38
FMC_B_DP[1]_C2M_P P39
FMC_B_DP[1]_M2C_N T34
FMC_B_DP[1]_M2C_P T35
FMC_B_DP[2]_C2M_N R36
FMC_B_DP[2]_C2M_P R37
FMC_B_DP[2]_M2C_N U32
FMC_B_DP[2]_M2C_P U33
FMC_B_DP[3]_C2M_N U36
FMC_B_DP[3]_C2M_P U37
FMC_B_DP[3]_M2C_N V34
FMC_B_DP[3]_M2C_P V35
FMC_B_DP[4]_C2M_N V38
FMC_B_DP[4]_C2M_P V39
FMC_B_DP[4]_M2C_N W32
FMC_B_DP[4]_M2C_P W33
FMC_B_DP[5]_C2M_N W36
FMC_B_DP[5]_C2M_P W37
FMC_B_DP[5]_M2C_N Y30
FMC_B_DP[5]_M2C_P Y31
FMC_B_DP[6]_C2M_N AH38
FMC_B_DP[6]_C2M_P AH39
FMC_B_DP[6]_M2C_N AF34
FMC_B_DP[6]_M2C_P AF35
FMC_B_DP[7]_C2M_N AJ36
FMC_B_DP[7]_C2M_P AJ37
FMC_B_DP[7]_M2C_N AF30
FMC_B_DP[7]_M2C_P AF31
FMC_B_DP[8]_C2M_N M38
FMC_B_DP[8]_C2M_P M39
FMC_B_DP[8]_M2C_N R32
FMC_B_DP[8]_M2C_P R33
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FMC_B_DP[9]_C2M_N N36
FMC_B_DP[9]_C2M_P N37
FMC_B_DP[9]_M2C_N T30
FMC_B_DP[9]_M2C_P T31
FMC_B_GBTCLK[0]_M2 W29
FMC_B_GBTCLK[0]_M2 W28
FMC_B_GBTCLK[1]_M2 AG29
FMC_B_GBTCLK[1]_M2 AG28
FMC_B_HA[0]_CC_N D24
FMC_B_HA[0]_CC_P C24
FMC_B_HA[1]_CC_N E23
FMC_B_HA[1]_CC_P D23
FMC_B_HA[10]_N F23
FMC_B_HA[10]_P F24
FMC_B_HA[11]_N C23
FMC_B_HA[11]_P B22
FMC_B_HA[12]_N C21
FMC_B_HA[12]_P C22
FMC_B_HA[13]_N B21
FMC_B_HA[13]_P A22
FMC_B_HA[14]_N G25
FMC_B_HA[14]_P G26
FMC_B_HA[15]_N J24
FMC_B_HA[15]_P H24
FMC_B_HA[16]_N E25
FMC_B_HA[16]_P D25
FMC_B_HA[17]_CC_N G24
FMC_B_HA[17]_CC_P F25
FMC_B_HA[18]_CC_N J25
FMC_B_HA[18]_CC_P J26
FMC_B_HA[19]_N M25
FMC_B_HA[19]_P L25
FMC_B_HA[2]_N A25
FMC_B_HA[2]_P A26
FMC_B_HA[20]_N L26
FMC_B_HA[20]_P K26
FMC_B_HA[21]_N P25
FMC_B_HA[21]_P N25
FMC_B_HA[22]_N L24
FMC_B_HA[22]_P K25
FMC_B_HA[23]_N N24
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FMC_B_HA[23]_P M24
FMC_B_HA[3]_N F26
FMC_B_HA[3]_P E26
FMC_B_HA[4]_N C26
FMC_B_HA[4]_P B26
FMC_B_HA[5]_N A23
FMC_B_HA[5]_P A24
FMC_B_HA[6]_N A19
FMC_B_HA[6]_P A20
FMC_B_HA[7]_N B24
FMC_B_HA[7]_P C25
FMC_B_HA[8]_N B19
FMC_B_HA[8]_P B20
FMC_B_HA[9]_N A18
FMC_B_HA[9]_P A17
FMC_B_HB[0]_CC_N L19
FMC_B_HB[0]_CC_P K18
FMC_B_HB[1]_N C18
FMC_B_HB[1]_P C17
FMC_B_HB[10]_N P20
FMC_B_HB[10]_P N20
FMC_B_HB[11]_N L22
FMC_B_HB[11]_P K22
FMC_B_HB[12]_N G21
FMC_B_HB[12]_P G20
FMC_B_HB[13]_N J19
FMC_B_HB[13]_P J18
FMC_B_HB[14]_N N22
FMC_B_HB[14]_P N23
FMC_B_HB[15]_N M21
FMC_B_HB[15]_P M22
FMC_B_HB[16]_N L23
FMC_B_HB[16]_P K23
FMC_B_HB[17]_CC_N G22
FMC_B_HB[17]_CC_P F22
FMC_B_HB[18]_N J23
FMC_B_HB[18]_P H23
FMC_B_HB[19]_N M20
FMC_B_HB[19]_P L20
FMC_B_HB[2]_N F20
FMC_B_HB[2]_P E20
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FMC_B_HB[20]_N J20
FMC_B_HB[20]_P J21
FMC_B_HB[21]_N K20
FMC_B_HB[21]_P K21
FMC_B_HB[3]_N D20
FMC_B_HB[3]_P D21
FMC_B_HB[4]_N F17
FMC_B_HB[4]_P E17
FMC_B_HB[5]_N D19
FMC_B_HB[5]_P C19
FMC_B_HB[6]_CC_N E22
FMC_B_HB[6]_CC_P E21
FMC_B_HB[7]_N H19
FMC_B_HB[7]_P H18
FMC_B_HB[8]_N G19
FMC_B_HB[8]_P F19
FMC_B_HB[9]_N G17
FMC_B_HB[9]_P F18
FMC_B_LA[0]_CC_N U4
FMC_B_LA[0]_CC_P T4
FMC_B_LA[1]_CC_N V4
FMC_B_LA[1]_CC_P V3
FMC_B_LA[10]_N U2
FMC_B_LA[10]_P U1
FMC_B_LA[11]_N P6
FMC_B_LA[11]_P P5
FMC_B_LA[12]_N U6
FMC_B_LA[12]_P U5
FMC_B_LA[13]_N W4
FMC_B_LA[13]_P W3
FMC_B_LA[14]_N T5
FMC_B_LA[14]_P R5
FMC_B_LA[15]_N U10
FMC_B_LA[15]_P U9
FMC_B_LA[16]_N U7
FMC_B_LA[16]_P T7
FMC_B_LA[17]_CC_N Y3
FMC_B_LA[17]_CC_P Y2
FMC_B_LA[18]_CC_N AC4
FMC_B_LA[18]_CC_P AC3
FMC_B_LA[19]_N Y10
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FMC_B_LA[19]_P AA9
FMC_B_LA[2]_N N4
FMC_B_LA[2]_P N3
FMC_B_LA[20]_N W8
FMC_B_LA[20]_P Y8
FMC_B_LA[21]_N AC1
FMC_B_LA[21]_P AD1
FMC_B_LA[22]_N W1
FMC_B_LA[22]_P Y1
FMC_B_LA[23]_N Y7
FMC_B_LA[23]_P Y6
FMC_B_LA[24]_N Y5
FMC_B_LA[24]_P AA5
FMC_B_LA[25]_N AA4
FMC_B_LA[25]_P AB4
FMC_B_LA[26]_N AB2
FMC_B_LA[26]_P AB1
FMC_B_LA[27]_N AA3
FMC_B_LA[27]_P AA2
FMC_B_LA[28]_N AA8
FMC_B_LA[28]_P AA7
FMC_B_LA[29]_N AD5
FMC_B_LA[29]_P AD4
FMC_B_LA[3]_N M2
FMC_B_LA[3]_P M1
FMC_B_LA[30]_N AB7
FMC_B_LA[30]_P AC7
FMC_B_LA[31]_N AE6
FMC_B_LA[31]_P AE5
FMC_B_LA[32]_N AB10
FMC_B_LA[32]_P AB9
FMC_B_LA[33]_N AB11
FMC_B_LA[33]_P AA10
FMC_B_LA[4]_N N2
FMC_B_LA[4]_P N1
FMC_B_LA[5]_N R1
FMC_B_LA[5]_P P1
FMC_B_LA[6]_N P4
FMC_B_LA[6]_P P3
FMC_B_LA[7]_N T3
FMC_B_LA[7]_P T2
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FMC_B_LA[8]_N R3
FMC_B_LA[8]_P R2
FMC_B_LA[9]_N V2
FMC_B_LA[9]_P V1
FMC_B_PG_M2C_F AU6
FMC_B_PRSNT_M2C_L_ AW4
Table (9): FMC_B Mezzanine Connector FPGA Pin Assignment
2.6.1.) V_Adjust
V_Adjust is provided on the FMC connector to simplify the power management on the FMC module so that the
limited space on the module can be fully used for the I/O functionality and to minimize any noise that would come
from a power supply onboard the module.
With the wide range of I/O that may exist on a FMC module, it is difficult to specify a single universal voltage that
would not need conversion to suit the devices on the modules. Therefore, this flexible mechanism of obtaining a
preconditioned power source from the carrier card and defined by the IPMI provides a powerful feature for
simplified system design.
V_Adjust for the FMC_A and FMC_B is generated and controlled by U2 ( Linear Tech LTM4644) and setting
value of the R28 and R30 resistors using the following formula:
R= [30.2] / [(V_Adjust / 0.6) -1]
Default setting of the V_Adjust for the FMC_A and FMC_B is 1.8V.
◙ 2.7) Z-RAY High-Speed Serial Bus
Z-Ray® micro array interposer is ultra-low profile, high density, highly customizable solution for board-to-board,
IC-to-board, and cable-to-board applications. With performance of 20GHz, this interface is ideal for serial
transceivers and signals running at 28Gbps.
The Z-RAY High-Speed Serial bus of the HTG-A100 platform provides access to sixteen serial transceivers, control
signals, clock, and voltage pins for additional daughter card interface. HiTech Global provides Z-RAY daughter
cards with SFP+, QSFP+, Hybrid Memory Cube (HMC), Gearbox CFP4, and QSFP28 ports.
Table (10) and (11) illustrate Z-RAY pinouts and FPGA pin assignment for the Z-RAY interface.
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Table (10): Z-RAY Bus Pinouts
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FPGA Signal Name Z-RAY Pin Number FPGA Pin Number
L2RX[0]_N H5 M34
L2RX[0]_P G5 M35
L2RX[1]_N H1 P30
L2RX[1]_P G1 P31
L2RX[2]_N E3 N32
L2RX[2]_P D3 N33
L2RX[3]_N H3 P34
L2RX[3]_P G3 P35
L2RX[4]_N H9 K30
L2RX[4]_P G9 K31
L2RX[5]_N E7 L32
L2RX[5]_P D7 L33
L2RX[6]_N E9 K34
L2RX[6]_P D9 K35
L2RX[7]_N H7 M30
L2RX[7]_P G7 M31
L2RX[8]_N H15 H34
L2RX[8]_P G15 H35
L2RX[9]_N E13 J32
L2RX[9]_P D13 J33
L2RX[10]_N E15 F30
L2RX[10]_P D15 F31
L2RX[11]_N H13 G32
L2RX[11]_P G13 G33
L2RX[12]_N H17 H30
L2RX[12]_P G17 H31
L2RX[13]_N E19 E32
L2RX[13]_P D19 E33
L2RX[14]_N H19 B30
L2RX[14]_P G19 B31
L2RX[15]_N H21 D30
L2RX[15]_P G21 D31
L2TX[0]_N E5 H38
L2TX[0]_P D5 H39
L2TX[1]_N E1 K38
L2TX[1]_P D1 K39
L2TX[2]_N L3 J36
L2TX[2]_P K3 J37
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L2TX[3]_N L1 L36
L2TX[3]_P K1 L37
L2TX[4]_N L11 E36
L2TX[4]_P K11 E37
L2TX[5]_N L7 F38
L2TX[5]_P K7 F39
L2TX[6]_N L9 F34
L2TX[6]_P K9 F35
L2TX[7]_N L5 G36
L2TX[7]_P K5 G37
L2TX[8]_N L17 D34
L2TX[8]_P K17 D35
L2TX[9]_N L13 D38
L2TX[9]_P K13 D39
L2TX[10]_N L15 A36
L2TX[10]_P K15 A37
L2TX[11]_N H11 B38
L2TX[11]_P G11 B39
L2TX[12]_N E17 C36
L2TX[12]_P D17 C37
L2TX[13]_N L19 B34
L2TX[13]_P K19 B35
L2TX[14]_N E21 A32
L2TX[14]_P D21 A33
L2TX[15]_N L21 C32
L2TX[15]_P K21 C33
MGT_ZSP_REFCLK0_N - E28
MGT_ZSP_REFCLK0_P - E29
MGT_ZSP_REFCLK1_N - J28
MGT_ZSP_REFCLK1_P - J29
MGT_ZSP_REFCLK2_N - N28
MGT_ZSP_REFCLK2_P - N29
ZSP_REFCLK_N D11 -
ZSP_REFCLK_P E11 -
ZSP_IO1_F B9 R6
ZSP_IO2_F B10 U11
ZSP_IO3_F B11 R7
ZSP_IO4_F B13 W9
ZSP_IO5_F B15 T9
ZSP_IO6_F B17 T8
ZSP_IO7_F B19 W10
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Table (11): Z-RAY FPGA Pin Assignment
Figure (10) illustrates mechanical dimension of mating Z-RAY connector (Samtec : ZSP⁃184731⁃01⁃ZA8⁃D) for
daughter card development.
Figure (10): Z-RAY Mating Connector’s Mechanical Dimensions
For faster and easier procurement process, the Z-RAY connector is available for purchase through HiTech Global’s
online store at https://hitechglobal.us/index.php?route=product/product&path=25&product_id=186
◙ 2.8) QSE Board-To-Board Port
The HTG-A100 platform provides one Samtec QSE connector with four Serial Transceivers for board-to-board
communication. The connector can also be used for additional daughter card interface requiring access to high speed
seral transceivers of the FPGA. Part number of the Samtec QSE connector is QSE-020-01-F-D-A. The mating
cables should use QST-020-01-F-D-A connector on each end. The following site provides ordering information for
the cable assembly:
http://datasheet.octopart.com/HQCD-090-07.00-TBR-TTL-1-Samtec-datasheet-11779106.pdf
Table (12) illustrates FPGA pin assignment for the QSE port.
FPGA Signal Name FPGA Pin Number
QSE_CLK_N AL28
QSE_CLK_P AL29
QSE_RX0_N AM30
QSE_RX0_P AM31
QSE_RX1_N AH30
QSE_RX1_P AH31
ZSP_IO8_F B21 V11
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QSE_RX2_N AH34
QSE_RX2_P AH35
QSE_RX3_N AG32
QSE_RX3_P AG33
QSE_TX0_N AT34
QSE_TX0_P AT35
QSE_TX1_N AM38
QSE_TX1_P AM39
QSE_TX2_N AL36
QSE_TX2_P AL37
QSE_TX3_N AK38
QSE_TX3_P AK39
Table (12): QSE Board-To-Board FPGA Pin Assignment
◙ 2.9) USB To UART Bridge
The HTG-A100 platform provides one UART port through a peripheral USB connector. The port is supported by
the Silicon labs CP2103 USB to UART controller chip.
The CP2103 is a highly-integrated USB-to-UART Bridge Controller providing a simple solution for updating RS-
232/RS-485 designs to USB using a minimum of components and PCB space. The CP2103 includes a USB 2.0 full-
speed function controller, USB transceiver, oscillator, EEPROM, and asynchronous serial data bus (UART) with
full modem control signals. No other external USB components are required.
The on-chip EEPROM may be used to customize the USB Vendor ID, Product ID, Product Description String,
Power Descriptor, Device Release Number, and Device Serial Number as desired for OEM applications. The
EEPROM is programmed on-board via the USB, allowing the programming step to be easily integrated into the
product manufacturing and testing process.
Royalty-free Virtual COM Port (VCP) device drivers provided by Silicon Laboratories allow a CP2103-based
product to appear as a COM port to PC applications. The CP2103 UART interface implements all RS-232/RS-485
signals, including control and handshaking signals; so, existing system firmware does not need to be modified. The
device also features up to four GPIO signals that can be user-defined for status and control information.
Direct access driver support is available through the Silicon Laboratories USBXpress driver set.
Driver for the CP2103 device is available at following site for download or upgrade :
https://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx
Table (13) illustrates FPGA pin assignment for the USB-TO-UART interface:
FPGA Signal Name FPGA Pin Number
UART_CTS AN22
UART_RST_N AP21
UART_RTS AU22
UART_RXD AT22
UART_SUSPEND_N AR21
UART_TXD AR22
Table (13): USB To UART FPGA Pin Assignment
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◙ 2.10) LEDs, GPIO Headers & Pushbuttons
Table (14) illustrates FPGA pins assignments for the user LEDs, Push Buttons, Switches, and XADC interfaces.
Signal Name Location FPGA Pin #
USER_IO1 J9 -1 AF14
USER_IO2 J9 -3 AF15
USER_IO3 J9 -5 AG14
USER_IO4 J9 -7 AG15
USER_IO5 J9 -9 AH14
USER_IO6 J9 -11 AJ13
USER_IO7 J9 -13 AJ14
USER_IO8 J9 -15 AK13
USER_LED1_G_F D1 AE3
USER_LED2_G_F D2 AF3
USER_LED3_G_F D3 AE2
USER_LED4_G_F D4 AE1
USER_LED5_R_F D5 AF2
USER_LED6_R_F D6 AG2
USER_LED7_R_F D7 AG1
USER_LED8_R_F D8 AH1
USER_PB1 PB1 AR12
USER_PB2 PB2 N9
USER_SW1 S3-1 K10
USER_SW2 S3-2 H11
USER_SW3 S3-3 K13
USER_SW4 S3-4 N13
USER_SW5 S3-5 H2
USER_SW6 S3-6 D9
USER_SW7 S3-7 B4
USER_SW8 S3-8 AF14
Table (14): User Interface FPGA pin assignment
◙ 2.11) I2C Bus Switch
As illustrated by figure (11), the onboard devices with I2C signals are controlled by an I2C Bus Switch
(PCA9538APW) and the Arria10 FPGA.
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Figure (11): I2C Bus Switch Diagram
Table (15) illustrates FPGA pin assignment for the I2C control.
Signal Name FPGA Pin Number
I2C_MAIN_RST_N_F AM22
I2C_MAIN_SCL_F AR23
I2C_MAIN_SDA_F AL22
Table (15): I2C Bus Switch FPGA Pin Assignment
◙ 2.12) Configuration
Arria devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data
must be downloaded to Arria GX devices each time the device powers up. Arria GX devices can be configured
using one of five configuration schemes
■ Fast passive parallel (FPP)—A controller supplies the configuration data in a parallel manner to the Arria 10
FPGA. FPP is supported in an 8-bit (FPP ×8), 16-bit (FPP ×16) or 32-bit data width (FPP ×32).
■ Active serial (AS)—The Arria 10 FPGA controls the configuration process and gets the configuration data from a
qual-serial configuration (EPCQ) device. AS is supported in 1-bit (AS ×1) or 4-bit data width (AS ×4).
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■ Passive serial (PS)—An external host supplies the configuration data serially to the Arria 10 FPGA.
■ Joint Test Action Group (JTAG)—Configured using the IEEE Standard 1149.1 interface with a download cable,
or using MAX (MAX II, MAX V, MAX 10) devices, or microprocessor with flash memory
You can enable any specific configuration scheme by driving the Arria 10 device MSEL pins to specific values on
the board. Configuration of the MSEL0, MSEL1, and MSEL2 is controlled by the “S2” switch.
Following document provides details information for configuration of the Arria 10 FPGAs:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/agx/agx_52011.pdf
Upon successful configuration of the FPGA the D14 (DONE) LED illuminates and stays ON.
◙ 2.13) IP Protection
The HTG-A100 platform provides access to a special circuit for protection of intellectual properties loaded to the
FPGA (pin # AW6) by using Maxim DS2432 chip (U25).
The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to
five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip.
Each DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide
a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. The DS2432 has an additional memory area
called the scratchpad that acts as a buffer when writing to the main memory, the register page or when
installing a new secret. Data is first written to the scratchpad from where it can be read back. After the
data has been verified, a copy scratchpad command will transfer the data to its final memory location,
provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the
secret and additional data stored in the DS2432 including the device’s registration number. Only a new
secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute
160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret,
instead of loading it. Applications of the DS2432 include intellectual property security, after-market
management of consumables, and tamper-proof data carriers.
Additional information is available at
http://datasheets.maximintegrated.com/en/ds/DS2432.pdf
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Chapter 3:Mezannine Cards
◙ 3.1) Z-RAY High-Speed Serial Bus Modules
The Z-RAY High-Speed Serial Bus provides access to up to 16 serial transceivers, clock, control signals, and
multiple voltage rails for interfacing high-speed / high-performance (20GHz) expansion modules.
HiTech Global offers series of daughter cards which can be used for expanding functionality of the main platform
through the Z-RAY interface.
3.1.1) Hybrid Memory Cube (HMC)
Each Hybrid Memory Cube (HMC) provides access to 4GB of serial memory. Modules can be connected in daisy
chain for increasing the density.
Image (2): HMC Module
3.1.2) QSFP+ Module
The X2QSFP+ Module provides access to two QSFP+ ports (2x40G)
Image (3): QSFP+ Module
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3.1.3) X3SFP+ Module
The X3SFP+ Module provides access to three SFP+ ports (3x10G)
Image (4): X3 SFP+ Module
◙ 3.2) FMC Vita 57.x Modules
HiTech Global offers a wide range of FMC daughter cards which can be used for expanding functionality of the
main platform.
3.2.1) 4-Channel 16-Bit ADC (Analog to Digital Convertor)
The HTG-ADC16 Module plugs into Vita 57.1 FMC HPC slots on compliant FPGA carrier boards and provides
access to four 16-bit ADC channels.
The module uses two Texas Instruments ADS54J60 ADC devices with JESD204B support.
The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter
(ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for
applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the
JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered
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analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold
glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block.
The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with
very low power consumption.
More information is available at http://hitechglobal.com/FMCModules/16-bit_AD-DA.htm
3.2.2) 2-Channel 16-Bit DAC (Digital To Analog Convertor)
The HTG-X2DAC16 Module plugs into Vita 57.1 FMC slots on compliant FPGA carrier boards and provides
access to two 16-bit DAC channels.
The module uses one Texas Instruments DAC39J84 DAC device with JESD204B support.
The DAC39J84 is a low power, 16-bit, quad-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B
interface.Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to
12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1
SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x
digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction
filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible
and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic
range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ
compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A
programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the
abnormal power behavior of the input data is detected.
More information is available at http://hitechglobal.com/FMCModules/16-bit_AD-DA.htm
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3.2.3) Gearbox / Re-timer QSFP28
The FMC-GB-QSFP28 module is powered by Broadcom 100Gbps Gearbox PHY (BCM82790)that multiplexes and
de-multiplexes four 25 Gbps channels to/from ten 10Gbps channels supporting Ethernet and Optical Transport
Networking (OTN). The module supports one full-duplex 100Gbe port and complies with 100GBASE-
CR4/SR4/LR4 for QSFP28 line-card applications. 100GbE Ethernet support includes CL91 RS FEC as well as
CL92 transmit training, and CL73 auto-negotiation.
Test and debug features included in the Gearbox are PRBS pattern generation and checking, eye monitoring on all
data receive interfaces, programmable loopbacks, as well as JTAG. Every port on the chip is equipped with an eye
monitor. All features are accessed through an IEEE standard MDIO control interface.
More information is available at http://hitechglobal.com/FMCModules/FMC_GB_QSFP28.htm
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3.2.4) Dual SFP+ (with external PHY)
The Dual SFP+ FMC daughter card provides access to two SFP+ ports (10Gbps each) interfacing to total of 8 serial
transceivers (XUAI).
The onboard 10Gig PHY device is a physical layer transceiver with an integrated Electronic Dispersion
Compensation (EDC) engine - compliant with IEEE802.3aq specifications. The device integrates industry-leading
SerDes/PHY technology with low-power EDC engine with up to 5db of margin over the symmetric stress test pulse
sensitivity specifications defined in the 10GASE-LRM standard.
Each PHY device provides full PCS, PMA, and XGXS sub-layer functionality through the consolidation of the
receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment
logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS & Ethernet frame generation &
verification for both the line side and the system side.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_SFP+.htm
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3.2.5) 10-Port SFP+
The X10-SFP+ FMC module is supported by ten SFP/SFP+ ports and high-performance low-jitter Silicon Labs
programmable Si570 oscillator with default frequency value of 156.25MHz. The I2C interface between the
oscillator and FPGA allows direct control of the SFP/SFP+ ports for wide range of different frequencies. The
SFP/SFP+ ports are directly connected to 10 multi-gigabit serial transceivers of the FPGA carrier board (DP0-DP9).
More information is available at http://hitechglobal.com/FMCModules/x10SFP+_FMC_Module.htm
3.2.6) Quad SFP/SFP+
The Quad SFP/SFP+ FMC module is supported by four SFP/SFP+ ports and high-performance low-jitter Silicon
Labs programmable clock (default = 156.25MHz). The I2C interface between the oscillator and FPGA allows direct
control of the SFP/SFP+ ports for wide range of different frequencies. The SFP/SFP+ ports are directly connected to
four multi-gigabit serial transceivers of the FPGA carrier board.
More information is available at http://hitechglobal.com/FMCModules/FMC_4SFP+_Module.htm
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3.2.7) Dual QSFP+
The Dual QSFP/QSFP+ FMC module is supported by two QSFP/QSFP+ ports and high-performance low-jitter
Silicon Labs programmable clock (default = 156.25MHz). The I2C interface between the oscillator and FPGA
allows direct control of the SFP/SFP+ ports for wide range of different frequencies. The QSFP/QSFP+ ports are
directly connected to eight multi-gigabit serial transceivers of the FPGA carrier board.
More information is available at http://hitechglobal.com/FMCModules/FMC_2QSFP+.htm
3.2.8) QSFP/QSFP+ /SFP+
The CPRI/OBSAI FMC module is supported by one QSFP+ and two SFP+ connectors. The required 122.88MHz
and 153.60MHz crystal oscillators for CPRI/OBSAI standards are available on the module. Different gigabit
standards can also be supported by changing crystal value (i.e. 10G and 40G Ethernet)
More information is available at http://hitechglobal.com/FMCModules/FMC_QSFP+.htm
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3.2.9) PCI Express Root Complex
The PCI Express Root FMC daughter card provides access to 8 lanes of PCI Express Gen 1 and port. The module is
supported by 100MHz and 250MHz low-jitter clocks.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_PCIExpress.htm
3.2.10) 8-port SMA/LVDS
The FMC SMA/LVDS (HTG-FMC-SMA-LVDS) is a single-size FPGA Mezzanine Connector (FMC) daughter
card with support for 8 SMA ports through 32 SMA connectors and 33 pairs of LVDS signals through standard pin
headers.
More information is available at http://hitechglobal.com/FMCModules/FMC_SMA_LVDS.htm
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3.2.11) Dual CX4
The dual CX4 FMC daughter card provides access to two CX4 ports (10Gbps) interfacing to total of 8 serial
transceivers (XUAI).
More information is available at http://www.hitechglobal.com/FMCModules/FMC_Dual_CX4.htm
3.2.12) CX4/SATA/SMA Serial Connectivity
The Serial Connectivity FMC daughter card provides access to one CX4, two SATA, and two SMA ports
(interfacing to total of 8 serial transceivers). Each port has its own on-board dedicated clock for maximum flexibility
and ease of use.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_CX4-SMA-SATA.htm
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3.2.13) 8-Port SMA
The 8-Port SMA FMC daughter card provides access to 32 SMA connecters providing access to 8 Serial
Transceivers. The module is supported by on-board and external clocks.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_SMA.htm
3.2.14) Quad SFP/SATA
The Quad SFP/SATA FMC daughter card provides access to four SFP and four SATA connectors. Each interface is
supported by its own independent clock.
More information is available at http://www.hitechglobal.com/FMCModules/FMC_x4SFP_x4SATA.htm
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3.2.15) Quad RJ45 Ethernet
The HTG-4RJ45 FMC module provides access to four RJ45 connectors through Marvel Alaska® Quad family of
single-chip device (88E1240-A0-BAM1C000) with four independent Gigabit Ethernet transceivers. Each transceiver
performs all the physical layer functions for 100BASE-TX and 1000BASE-T full or half-duplex Ethernet on CAT 5
twisted pair cable, and 10BASET full or half-duplex Ethernet on CAT 3, 4, and 5 cable.
The Alaska 88E1240 device supports the Serial Gigabit Media Independent Interface (SGMII) for direct connection
to a MAC/Switch port. The 88E1240 device is fully compliant with the IEEE 802.3 standard. The 88E1240 device
includes the PMD, PMA, and PCS sub layers. The 88E1240 device performs PAM5, 8B/10B, 4B/5B, MLT-3,
NRZI, and Manchester encoding/decoding, digital clock/data recovery, stream cipher scrambling/ descrambling,
digital adaptive equalization for the receiver data path as well as digital filtering for pulse-shaping for the line
transmitter, and Auto-Negotiation and management functions.
More information is available at http://hitechglobal.com/FMCModules/FMC_RJ45.htm
3.2.16) 42-Channel RS485/RS422
The RS485/RS422 FMC module is powered by Linear Tech LTC2854 and provides 42 differential channels using
20Mb RS485/RS422 transceivers.
More information is available at http://hitechglobal.com/FMCModules/FMC_RS485.htm
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Technical Support:
Technical support can be provided by contacting [email protected] Support requests are responded in
less than 24 hours.
Sales Support:
Sales support can be provided by contacting [email protected] or +1 408 781-7778 (8:00 AM – 6:00 PM
Pacific Standard Time)