high_voltage_digital_to_analog_converter_thesis
TRANSCRIPT
BOSTON UNIVERSITY
COLLEGE OF ENGINEERING
Thesis
HIGH VOLTAGE, HIGH RESOLUTION,
DIGITAL-TO-ANALOG CONVERTER FOR DRIVING
DEFORMABLE MIRRORS
by
JEFFREY KITTREDGE
B.S., University of Rhode Island, 2007
Submitted in partial fulfillment of the
requirements for the degree of
Master of Science
2015
c© Copyright byJeffrey Kittredge2014
If you will it, it is no dream.Theodor Herzl
Acknowledgments
I appreciate my thesis advisor professor Horenstein for encouraging me to com-
plete this research. Professor Horenstein brought together a great research team.
I am proud to have worked with them. The environment was fun and I learned a
great deal. Thank you to professor Knepper and professor Hubbard for being on my
Master’s Thesis Committee.
Researcher Chris Woodall was simply critical to the team’s success. Chris brought
creativity, efficiency and dedication. Chris is a promising engineer that will certainly
solve many great challenges. Chris designed the 16 Fine Board and wrote the firmware
to test it. Gaukar Tergemessova was very helpful, especially with Altium. David
Friedman joined to design the 256 channel board and it worked out of the box!
Professor Vladimir Kleptsyn offered advice and test instruments which were useful.
Thank you to Paul Bierdan of Boston Micro Machines for arranging the research.
Paul guided us to make sure the design was compatible with deformable mirrors.
With Paul’s help we were able to demonstrate functionality on an actual deformable
mirror. This research was made possible by NASA Jet Propulsion Lab through SBIR
NNX-10 CE08P. The entire team is grateful for the opportunity.
Pursuing a Master’s in Electrical Engineering was possible with the support of my
family. Thank you to my Mother and Father for helping me learn since I was young.
My brother Andrew was my biggest supporter to pursue a MS. Amy is the greatest,
thank you so much.
v
HIGH VOLTAGE, HIGH RESOLUTION,
DIGITAL-TO-ANALOG CONVERTER FOR DRIVING
DEFORMABLE MIRRORS
JEFFREY KITTREDGE
ABSTRACT
Digital-to-analog converters with a range over 50 volts are required for driving
micro-electro mechanical system deformable mirrors used in adaptive optics. An
existing tested and deployed DM driver has 1024 channels and resolution of 15mV
per Least Significant Bit. DMs used in the search for exoplanets require 3mV per
LSB resolution. A technique is presented to employ a secondary high resolution and
low voltage DAC which has for it’s ground the output of the high voltage DAC. The
entire system then has the range of high voltage DAC yet the resolution of the low
voltage DAC. A method for providing signal and power to the floating system is given.
Rudimentary micro controller firmware and also PC software is presented to achieve
complete functionality. The technique uses all off-the-shelf components. Resolution
of 1.6mV per LSB, 60V range and 36mW of power per channel is achieved.
vi
Contents
1 Introduction 1
1.1 Search for Exoplanets . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 MEMS Deformable Mirrors . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Existing Mirror Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Requirements for Improving Resolution . . . . . . . . . . . . . . . . . 4
2 Floating DAC Architecture 5
2.1 Resolution Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Output Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Method for Incrementing . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Overview of Floating DAC . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 Supply Using Varying Supply Voltage . . . . . . . . . . . . . . . . . . 8
2.5.1 Current Mirror and Zener Diode . . . . . . . . . . . . . . . . . 9
2.5.2 Commercial Low Drop-Out Voltage Regulator . . . . . . . . . 10
2.5.3 Choosing VDD for the Floating DAC . . . . . . . . . . . . . . 11
2.6 Passing Logic Signals to a Changing Potential . . . . . . . . . . . . . 12
2.6.1 Switched PMOS Current Mirror . . . . . . . . . . . . . . . . . 12
2.6.2 Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3 Transformer or Differential Capacitors . . . . . . . . . . . . . 15
2.6.4 Analog Devices iCouplerr . . . . . . . . . . . . . . . . . . . 15
2.7 Considerations for Many Channels . . . . . . . . . . . . . . . . . . . 15
vii
2.8 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8.1 SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8.2 µC vs. FPGA vs. Digital USB I/O Device . . . . . . . . . . . 17
2.8.3 Hardware Based SPI . . . . . . . . . . . . . . . . . . . . . . . 17
2.8.4 PC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Design and Implementation 19
3.1 Partition of Existing LSB . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Example: Choosing n for VREF−FINE = 3.361V . . . . . . . . 20
3.1.2 VLSB at Coarse DAC Increment Boundary . . . . . . . . . . . 21
3.1.3 Fine DAC Offset Relationship to Changes in VDD−FLOAT . . . 22
3.1.4 Observations Related to LSB Partitioning . . . . . . . . . . . 22
3.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Low Voltage DAC . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Voltage Regulator, Low Drop-Out . . . . . . . . . . . . . . . . 24
3.2.3 Signal Level-Shifter . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Single Channel Design . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Prototype Board, Single Channel . . . . . . . . . . . . . . . . 25
3.3.2 Printed Circuit Board, Single Channel . . . . . . . . . . . . . 25
3.4 16 Channel Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 256 Channel Version . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 Test Apparatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6.1 Measuring Milli-Volts Over 100V Range . . . . . . . . . . . . 28
4 Measured Results 29
4.1 Minimum Increment Stepping . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . 29
viii
4.3 DNL Shown by Transfer Function . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Non-monotonic Stepping at Coarse DAC Boundary . . . . . . 32
4.3.2 Non-monotonic Stepping with Constant Coarse DAC . . . . . 33
4.3.3 Possible Causes of Loss of Monotonicity with Constant Coarse
Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Monotinicity of Low Quiescent Current Design . . . . . . . . . . . . . 34
4.5 DNL vs. Fine DAC Code . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 DNL Correlation with ∆iSINK . . . . . . . . . . . . . . . . . . . . . . 36
4.6.1 Changing Floating DAC Quiescent Current . . . . . . . . . . . 36
4.7 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7.1 Power of High Quiescent Current Design Appendix A.1 . . . . 38
4.7.2 Power of Low Quiescent Current Design Appendix A.2 . . . . 38
4.8 16 Channel Version, Functional Check Driving a Mirror . . . . . . . . 39
4.9 1024 Channel Version, Functional Check With Multimeter . . . . . . 39
5 Discussion 41
5.1 ADuM1100 vs. ADuM1300 . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.1 DNL and Monotinicity . . . . . . . . . . . . . . . . . . . . . . 41
5.1.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.3 Foot Print and Cost . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.4 Single Channel PCB Design vs. 16 Channel PCB Design . . . 42
5.2 Minimum Increment LSB . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.1 Implications to Control and Feedback . . . . . . . . . . . . . . 42
5.2.2 Monotonic LSB . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.3 Stepping with Monotonic LSB . . . . . . . . . . . . . . . . . . 43
5.3 n = 16 vs. n = 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1 DNL of Coarse DAC . . . . . . . . . . . . . . . . . . . . . . . 44
ix
5.3.2 Definition of nIDEAL . . . . . . . . . . . . . . . . . . . . . . . 45
5.4 Explanation for DNL to ∆iSINK Correlation . . . . . . . . . . . . . . 45
5.4.1 Non-ideal Coarse DAC Model . . . . . . . . . . . . . . . . . . 46
5.5 Failure Mode of Abrupt Contact To Negative Potential . . . . . . . . 47
5.6 Untested Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.6.1 Integral Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . 48
5.6.2 Update Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.6.3 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.6.4 Coarse DAC Incrementing More Than 1 LSB at a Time. . . . 49
6 Conclusion 51
6.1 Proof of Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Usability and Integration . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3 Summary of Achieved Parameters . . . . . . . . . . . . . . . . . . . . 52
6.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.1 Ladder DAC Concept for High Voltages . . . . . . . . . . . . 53
6.4.2 Floating Power Using Transformer and Rectifier, AD isoPowerr 53
6.4.3 Relaxed Resolution Requirement of HV DAC . . . . . . . . . 54
A Appendix 55
A.1 Single Channel on Prototype Board Schematic, High Quiescent . . . . 55
A.2 Single Channel on PCB Schematic, Low Quiescent . . . . . . . . . . . 56
A.3 Single Channel PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A.4 Test Apparatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A.5 Single Channel Micro-controller Firmware . . . . . . . . . . . . . . . 59
A.6 Single Channel Fine SPI Bus Scope Trace . . . . . . . . . . . . . . . 73
A.7 Single Channel Coarse SPI Scope Trace . . . . . . . . . . . . . . . . . 74
x
A.8 Single Channel UART Scope Trace . . . . . . . . . . . . . . . . . . . 75
A.9 Single Channel MATLAB Code for UART . . . . . . . . . . . . . . . 75
A.10 16 Coarse Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.11 1024 Channel Integration Overview . . . . . . . . . . . . . . . . . . . 85
A.12 1024 Channel Control Board . . . . . . . . . . . . . . . . . . . . . . . 86
A.13 Interferometer Results, 16 Channel Driving DM . . . . . . . . . . . . 87
References 88
Curriculum Vitae 90
xi
List of Tables
2.1 Incrementing Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Incrementing with rounded n. . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Incrementing with floor function n. . . . . . . . . . . . . . . . . . . . 21
4.1 Data showing change in sign of transfer function at coarse boundary. 33
4.2 Data showing change in sign of transfer function with coarse DAC
constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 All non-monotonic codes of design in appendix A.2 . . . . . . . . . . 35
4.4 Power of appendix A.1, VDD−FLOAT = 2.83V . . . . . . . . . . . . . . 38
4.5 Power of appendix A.2, VDD−FLOAT = 3.361V . . . . . . . . . . . . . 39
5.1 Concept of incrementing 2 fine DAC codes at a time, VREF−COARSE =
60, VREF−FINE = 3.361. . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 Results summary, design appendix A.2. . . . . . . . . . . . . . . . . . 53
xii
List of Figures
1·1 Adaptive optics feedback loop to correct wavefront aberrations (Per-
rault et al., 2002). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1·2 MEMS deformable mirror spring and capacitor model (Horenstein et al.,
2011). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2·1 1000’ cranes position a small sign: (a) Large crane does not have fine
enough adjustment, and (b) cranes lifts a small hoist which positions
the sign precisely. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2·2 Stacking digital-to-analog converters. . . . . . . . . . . . . . . . . . . 9
2·3 PNP current mirror combined with Zener diode for floating power supply. 11
2·4 Single channel floated with logic signals level shifted. . . . . . . . . . 12
2·5 PMOS switched current current mirror as logic signal level shifter (only
1 of 3 required SPI signals shown). . . . . . . . . . . . . . . . . . . . 13
2·6 Optical isolation as logical level shifter. . . . . . . . . . . . . . . . . . 14
3·1 Single Channel Floating DAC on prototype board . . . . . . . . . . . 25
3·2 Architecture of 16 floating DAC channels. . . . . . . . . . . . . . . . 26
4·1 Transfer function of Floating DAC. Floating DAC design appendix
A.2, n = 16, starting fine command 200. For comparison VCOARSE−LSB
which was status-quo prior to floating DAC is also shown. . . . . . . 30
xiii
4·2 Differential Non-Linearity measured by appendix A.4 with ammeter
shunted, 10 PLC: (a) Design A.1 functionally implemented as a single
channel of the 16 channel board, fine DAC command incrementing 200
to 220; and (b) Design A.2, fine DAC command incrementing 200 to
216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4·3 High quiescent current design appendix A.1 is not monotonic between
commands C1279+F220 and C1280+F200. . . . . . . . . . . . . . . . 32
4·4 High quiescent current design appendix A.1 is not monotonic between
commands C2447+F209 and C2447+F210. It is non-monotonic with
coarse DAC constant command. . . . . . . . . . . . . . . . . . . . . . 34
4·5 DNL vs. fine DAC code, design appendix A.2, n = 16. fine starting
command of 200, test apparatus A.4 with ammeter shunted. . . . . . 36
4·6 DNL vs. ∆iSINK , low quiescent design appendix A.2, n = 16. fine
starting command of 200, test apparatus A.4. . . . . . . . . . . . . . 37
5·1 Ideal model of AD5504 output copied from the datasheet, annotations
added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5·2 AD5504 output considering non-idealities. . . . . . . . . . . . . . . . 46
xiv
List of Abbreviations
ASIC . . . . . . . . . . . . . Application Specific Integrated CircuitBJT . . . . . . . . . . . . . Bipolar Junction TransistorCLK . . . . . . . . . . . . . ClockCS . . . . . . . . . . . . . Chip Select (active low)DAC . . . . . . . . . . . . . Digital-to-Analog ConverterDIN . . . . . . . . . . . . . Data InDM . . . . . . . . . . . . . Deformable MirrorDNL . . . . . . . . . . . . . Differential NonlinearityFPGA . . . . . . . . . . . . . Field Programmable Gate ArrayFET . . . . . . . . . . . . . Field Effect TransistorHV . . . . . . . . . . . . . High Voltage ( >50V)INL . . . . . . . . . . . . . Integral NonlinearityI/O . . . . . . . . . . . . . Input or OutputLDAC . . . . . . . . . . . . . Load DAC (shift register values)LDO . . . . . . . . . . . . . Low Drop Out (voltage regulator)LSB . . . . . . . . . . . . . Least Significant BitµC . . . . . . . . . . . . . Micro-ControllerMEMS . . . . . . . . . . . . . Microelectro Mechanical SystemsNASA . . . . . . . . . . . . . National Aeronautics and Space AdministrationNMOS . . . . . . . . . . . . . n-Type Metal Oxide Semiconductor transistorNRZ . . . . . . . . . . . . . Non Return to ZeroPC . . . . . . . . . . . . . Personal ComputerPCI . . . . . . . . . . . . . Peripheral Component InterconnectPCB . . . . . . . . . . . . . Printer Circuit BoardPLC . . . . . . . . . . . . . Power Line CyclesPMOS . . . . . . . . . . . . . p-Type Metal Oxide Semiconductor TransistorSBIR . . . . . . . . . . . . . Small Business Innovative ResearchSPI . . . . . . . . . . . . . Serial Peripheral InterfaceUART . . . . . . . . . . . . . Universal Asynchronous Receiver-TransmitterUSB . . . . . . . . . . . . . Universal Serial BusUSCI . . . . . . . . . . . . . Universal Serial Communication InterfaceUSI . . . . . . . . . . . . . Universal Serial Interface
xv
1
Chapter 1
Introduction
1.1 Search for Exoplanets
Humanity has the insatiable desire to understand whether we are alone in the uni-
verse. A prime interest for potentially unlocking this secret lies in the identification
and imaging of exoplanets. Direct observation of exoplanets requires adaptive op-
tics to correct aberrations in the light traveling from these planets towards earth.
Coronagraphs are also required to avoid having the parent star saturate the image
(Macintosh et al., 2006). The method for correcting wavefront aberrations is micro
electromechanical system deformable mirrors.
The DM and its driver is one component of an entire optical path for planet
imagers. The Gemini planet imager uses both a ”woofer” and ”tweeter” Deformable
Mirror (Macintosh et al., 2006). The critical function of the DM is to correct wavefront
aberrations prior to the coronagraph. An adaptive optics feedback loop similar to
figure 1·1 is one component of the Gemini Planet Imager architecture.
One performance limit of DMs is the resolution of the driver. DM drivers are
digital-to-analog converters. As part of a program to create a mirror and driver system
to image exoplanets, NASA funded research through the Small Business Innovative
Research program. This high performance DAC research is one portion of the SBIR
to design a satellite compatible DM and driver system.
2
Figure 1·1: Adaptive optics feedback loop to correct wavefront aber-rations (Perrault et al., 2002).
1.2 MEMS Deformable Mirrors
Deformable Mirrors are inserted in the light path of telescopes and other optical in-
struments to correct wavefront aberrations. The surface of a DM can be altered to
change the path length and reflected angle of incident light. The surface of MEMS
DMs are controlled by a piston deflected by electrostatic force, see figure 1·2. The
mechanical restoring force is overcome by the applied electrostatic force. Separat-
ing Horenstein et al. 2011 equation (1) for displacement y as a function of applied
voltage V yields:
ε0LwV2
2k= [g2y − 2gy2 + y3] (1.1)
Without even solving the cubic, equation (1.1) appears reasonable concerning incre-
mental changes in V and y. Smaller increments of V will result in smaller increments
of y. The focus of this research is to allow smaller ∆V to enable improved optical
performance of smaller ∆y. The smallest increment of which V can be changed is
defined as the Least Significant Bit increment.
3
Figure 1·2: MEMS deformable mirror spring and capacitormodel (Horenstein et al., 2011).
1.3 Existing Mirror Driver
The deliverable of this research was required to integrate to an existing system. The
circuit which reduces LSB increment and increases resolution is a modular add-on
to an existing system. The existing mirror driver is Boston Micro Machines, Kilo
Driver. The Kilo Driver is 1024 Channels and 60V adjustable range with 14.7mV/
LSB. Kilo-Driver is 256 of Analog Devices AD5504 DAC and an FPGA to control
them. A fiber optic link to a PCI card in a PC is supported by the FPGA. Analog
Outputs are on 4 of Samtec GFZ-30X10 connectors. Logic, analog and bias voltages
are supplied by off-board commercial power supplies. Kilo-Driver and power supply
are each in a 2U chassis.
Kilo-Driver and accompanying DM are already commissioned and in service.
Tested control software exists. The entire set-up is used in a feedback loop with
a wavefront sensor to provide aberration correction. Providing a plug-in enhance-
ment known as a daughter card to an existing system significantly reduces scope and
design risk.
4
1.4 Requirements for Improving Resolution
Existing Kilo-Driver outputs are Analog Device AD5504. Each channel of an AD5504
can sink or source a maximum of 1mA. Consequently the entire current required
by the floating DAC side must be less than 1mA. Existing Kilo-Driver has 1024
channels, so the resolution enhancing system must also have 1024 channels. The
eventual exoplanet imager is estimated to require 10pm incremental deflection at the
DM. 10pm mirror surface deflection requires 3mV per LSB at the driver (Boston
Micromachines Corporation, 2010).
The proposed resolution enhancing daughter board connects between the existing
Kilo-Driver and DM. In deployment a large negative ”pre-bend” potential is applied
to the ground of the DM. The 1024 system must have satisfactory connectors for
all 1024 channels. Logic and other device quiescent power is a concern. Essential
requirements of the proposed resolution enhancer are:
1. LSB increment ≤ 3mV
2. Integrate to existing driver
3. Entirely off-the-shelf components
4. Control using SPI
5. Each channel updates at least once per second
5
Chapter 2
Floating DAC Architecture
2.1 Resolution Analysis
The existing Kilo-Driver has 12-bit resolution and a 60V reference. This results in
14.7mV per LSB. Defining VLSB as the output increment when one LSB is changed,
we have:
VLSB ≡VREF
2N=
60V
212= 14.7mv/LSB (2.1)
To achieve the required 3mV/ LSB staying with a 60V reference would require:
N = log2
(VREF
VLSB
)=ln(VREF
VLSB)
ln(2)=ln( 60V
3mV)
ln(2)= 14.3⇒ 15bits (2.2)
The existing driver consists of 12-bit DACs which are commercial items that cannot
be modified. To achieve 15 bit equivalent resolution a secondary DAC is used. The
secondary DAC has for its ground the output of the existing DAC. Any single channel
of the existing Analog Devices AD5504 is named ”Coarse” and the floating, lower
reference DAC is named ”Fine”. If a 3V reference 12-bit Fine-DAC is used, VLSB for
the entire system becomes:
VLSB = VLSB−FINE =VREF−FINE
2N=
3V
212= 0.73mv/LSB (2.3)
For equation (2.3) to be true:
6
1. Output of Coarse-DAC does not change when sinking or sourcing currents
change.
2. Output of Coarse-DAC does not drift when sinking and sourcing currents
are constant.
2.2 Output Analysis
In general the output of a DAC is defined as:
VANALOG =VREF
2N∗ CODE (2.4)
Where N is the number of bits of the DAC and CODE is the value loaded into
the DAC. Technically the maximum value of CODE is 2N − 1 so the DAC cannot
perfectly output VREF . Definitions vary book to book on wether the denominator
of equation (2.4) should be 2N or (2N − 1). This paper uses 2N as shown in (2.4).
The architecture presented here stacks one DAC on the output of another; thus the
voltage’s add giving:
VOUT = VCOARSE + VFINE (2.5)
VOUT =VREF−COARSE
2N∗ CoarseCODE +
VREF−FINE
2N∗ FineCODE (2.6)
This assumes both coarse and fine DAC have the same number of N bits.
7
2.3 Method for Incrementing
The general technique for incrementing through all possible values the coarse DAC -
fine DAC combination can have is as follows:
1. Leave coarse DAC constant.
2. Increment fine DAC code one at a time until the sum of increments of fine
DAC would exceed a single increment of coarse DAC.
3. Decrement fine DAC by the sum of how many times it was incremented
(in one step) and simultaneously increment coarse DAC by one code.
4. Repeat . . .
An example if coarse DAC increments 10V per LSB and fine DAC increments 1V per
LSB is shown in table 2.1.
Table 2.1: Incrementing Concept.
VCOARSE VFINE VOUT
......
...10 0 1010 1 11...
......
10 8 1810 9 1920 0 2020 1 21...
......
2.4 Overview of Floating DAC
The concept of having separate stages provide coarse and fine resolution indepen-
dently is used in other devices. The benefits is the overall system has the range of
8
the coarse stage yet the resolution of the fine stage. Thinking back to High School,
one can remember the “Triple Beam Balance.” An even more applicable example is
a large crane which lifts a small hoist to provide fine adjustment when positioning
small items as seen in figure 2·1. The second example is particularly relevant because
it has the added constraint that the large crane must be perfectly still. The problem
of the coarse stage moving proves to be the Achille’s heal of this methodology.
(a) (b)
Figure 2·1: 1000’ cranes position a small sign: (a) Large crane doesnot have fine enough adjustment, and (b) cranes lifts a small hoistwhich positions the sign precisely.
The concept of stacking digital-to-analog converters is shown in figure 2·2. To
have a functioning floating DAC first power must be supplied and secondly control
signals must be sent to the floating DAC.
2.5 Supply Using Varying Supply Voltage
In general DACs require VDD on the same order or magnitude of Vref . Low voltage
DACs commonly have VDD and VLOGIC be the same. To provide VDD of 3V for the
floating DAC, simply connecting VDD of figure 2·2 to serve as fine DAC’s VDD will
not work. When the coarse DAC has a small output of Vcoarse = 10V , the floating
DAC will have a Vdd of 64V − 10V = 54V which will burn out the fine DAC. A
method for keeping a constant 3V as a supply for the fine DAC over the entire range
9
Figure 2·2: Stacking digital-to-analog converters.
of VCOARSE is needed.
2.5.1 Current Mirror and Zener Diode
Initial attempts used a current mirror to feed a reverse biased Zener diode. Relatively
constant quiescent supply current for for the floating DAC allows that current to be
measured. The current is then made the reference in a 1:1 PNP current mirror. A
Zener diode serves as the precise voltage “regulator” at the floating DAC. Specifying
the Zener as a “regulator” is a bit of an overstatement. The zener in effect provides
a constant VZENER but is open loop. The concept tested feasible yet suffers from two
problems:
1. Early Effect caused current to change as Vce changes.
2. The current required to bias the Zener into constant voltage is substantial
when compared to 1mA.
IC = ICSeVBEVT
(1 +
VceVA
)(2.7)
10
BJT current mirrors rely on relatively constant collector current that is a function
of base current regardless of collector-emitter voltage. This assumes the PNP is in
the active operating region. However even in active region, the Early Effect causes
collector current to change with collector-emitter voltage. This is explicitly seen as
the VCE in (2.7). This caused quiescent current to increase as VCOARSE decreased
which is undesirable. If FET transistors were used channel length modulation would
have caused similar phenomenon.
Reverse biased Zener diodes can maintain a relatively constant voltage if biased
correctly. As mentioned in the previous section the applied current will change thus
VZENER will also change which is undesirable. Assuming biasing is done correctly the
PNP mirror and Zener can be combined to achieve a floating ground and constant
voltage power supply implemented in figure 2·3. This method did test feasible yet did
not perform as well as the LDO regulator. PNP mirror and Zener combo could be
used in higher voltage voltage application where purchasing an LDO is not possible.
2.5.2 Commercial Low Drop-Out Voltage Regulator
In order to keep VDD−FLOAT more constant over the full range of VCOARSE a method
with feedback was sought. Linear voltage regulators provide the needed performance.
Linear voltage regulators are sold in discrete packages as Low Drop-Out regulators.
LDOs usually consist of a band gap voltage reference, pass transistor and feedback
circuit. Due to the pass transistor blocking significant voltage, typically efficiency is
poor.
Fortuitously, we found the Linear Technologies LT-3010 which allows a high-rail
supply of 80V. It was the only LDO we found that met all specifications. LT-3010 has
adjustable output voltage using a resistor divider reference. The functional location
of the LDO is seen in figure 2·4.
11
Figure 2·3: PNP current mirror combined with Zener diode for float-ing power supply.
2.5.3 Choosing VDD for the Floating DAC
Supply voltage for the floating DAC can be chosen to some extent. Readily avail-
able low voltage DACs range from a VDD of approximately 1.8-5V. Choosing higher
VDD increases power in the digital CMOS circuit in the DAC (Ahmed and Johns,
2005). Decreasing VDD often indicated a decrease in max bus and update rates. This
de-rating from decreasing VDD was usually still significantly above the update rate re-
quirements. In order to keep total floating side quiescent current <1mA only discrete
components specifically designed for micro-power or mobile applications were usable.
Most of such components were in the 2.5-3V range. A target of approximately 3V
was chosen for VDD−FLOAT .
12
Figure 2·4: Single channel floated with logic signals level shifted.
2.6 Passing Logic Signals to a Changing Potential
Looking back to figure 2·1 one may wonder how control signals get to a hoist that itself
is moving up and down. Floating DACs have a similar, non-trivial problem. Coarse-
DAC is always referenced ( grounded ) to 0V “earth ground.” Floating DAC ground
is referenced to “Floating Ground” which is a varying potential when compared to
0V earth ground. A method must be devised to pass signal across the change in
potential. The topic is broadly called Level Shifting, although typically a level shift
is of a fixed amount. Here the difference between earth ground and floating ground
varies from 0V to approximately 58V.
2.6.1 Switched PMOS Current Mirror
The first method investigated by the team was a switched PMOS current mirror.
Switched PMOS current mirror is a similar technique as described in Dufort et al.
2002 as seen in figure 2·5. A key difference is the method described in Dufort et al.
2002 has another NMOS with gate driver as logical inverse of QDRIV E with source
13
Figure 2·5: PMOS switched current current mirror as logic signal levelshifter (only 1 of 3 required SPI signals shown).
connected to ground and drain connected to +VLOGIC−IN . Floating DAC applica-
tion does not permit the additional NMOS because the logic input of fine DAC would
experience large negative potentials at the inputs referenced to it’s own ground (Float-
ing Ground) which are not permitted. Also, the Zener would forward bias.
A PMOS current mirror was used which introduces the added headache of negative
signs. To facilitate the following argument take every voltage is an absolute value!
This avoids having to decide if a PMOS with VGS < VTHRESHOLD is active or not. In
this section, all voltages are absolute values!
Figure 2·5 was built with discrete components and tested. The results proved
feasibility but could not achieve nearly high enough bus rates. The system provided
sharp rising edges at VLOGIC−IN over a wide range of VCOARSE values. However, the
falling edge of VLOGIC−IN was more of a droop starting around 500Hz bus rate. The
level shifted signal was marginally usable at most 1kHz.
Satisfactory VLOGIC−IN rising edge yet poor falling edge is explained by the for-
14
mation and break-down of the channel in QLOGIC . Consider, QDRIV E can pull the
QLOGIC Gate node low which causes formation of the channel in QLOGIC because
VGS > VTHRESHOLD. However, when QDRIV E opens desiring logic low at VLOGIC−IN
the Gate of QLOGIC is not driven such that VGS < VTHRESHOLD. QLOGIC node VG
is merely allowed to float. Thus an electric field does not break down the channel
in QLOGIC . The carriers in the channel must diffuse back into the substrate which
is relatively slow. Because QLOGIC channel slowly breaks down, the falling edge
VLOGIC−IN is not abrupt. A switched current mirror is feasible for level shifting but
not fast enough for this application.
2.6.2 Optical Isolation
Optical Isolation is widely used for level shifting. Optical Isolation was implemented
as figure 2·6. Several varieties of available micro-power and battery powered applica-
tion specific optoisolators were tested. All tested models required too much current
on the floating side. The lowest floating side current model was 3mA. This is greater
than the maximum of 1mA sink current of AD5504.
Figure 2·6: Optical isolation as logical level shifter.
15
2.6.3 Transformer or Differential Capacitors
Several wired communications protocols use differential signals. They include RS-
485 and USB. The problem of passing signals across a potential barrier has many
similarities with differential data signals. The methodologies of section 2.6.1 and
section 2.6.2 do not provide sufficient bus rates while maintaining <1mA quiescent
current. Research of differential protocols revealed an established field of level shifting
logic signals using differential capacitance or transformers. A capacitor can pass AC
signals yet not DC. Transformers also pass AC signal only. Protocols which do not
explicitly have DC correctness are call Non-Return-to-Zero.
SPI bus requires DC correctness. To preserve DC correctness using either dif-
ferential capacitors of transformers requires encoding and decoding DC correctness.
To avoid expanding scope of the original research topic an off-the-shelf solution is
required.
2.6.4 Analog Devices iCouplerr
Team member Christopher Woodall suggested Analog Devices iCouplerr technol-
ogy. iCouplerr consists of on-chip spiral transformers, digital encoding and digital
decoding circuits (Chen et al., 2003). NRZ signals passing across a galvanic barrier
are completely transparent to the PCB designer. The chips provide isolated and DC
correct signal level shifting. The floating side current of model ADuM1300 or three of
ADuM1100 is <1mA. Bus rates far exceed required. iCouplerr meets requirements.
2.7 Considerations for Many Channels
The final deliverable requires 1024 floating channels. SPI bus has Clock and Data
signals which are common to all nodes. Each node has an individual Chip Select line.
Most micro controllers do not have 1024 channels. A method for ”row” and ”column”
16
select schemes are built into the 16 and 1024 channel design. This avoids requiring
1024 I/O pins on the selected controller for CS.
To fully demonstrate functionality and for testing AD5504 coarse DACs that are
test bench usable were required. They are not part of the final deployment. To
simplify programming, neither the LDAC nor Clear feature of the AD5504 are used.
They allow separate load and clear commands to be given. Many SPI DACs have a
data-out pin for echoing back the command to check for correctness. Level shifters
which allow bi-directional communication require too much current and were not
used.
2.8 Controller
Demonstrating function and testing requires implementing a controller for both the
coarse DACs and the fine DACs. Both can be controlled with a single devices although
that will not be the case in deployment.
2.8.1 SPI Bus
All controls for both coarse and fine DAC are through SPI bus. SPI is implemented
on chip using shift registers (Davies, 2008). Data bits are clocked on the rising or
falling edge of a Clock signal. Depending on the state of DIN when a CLK edge
occurs either a ”0” or ”1” is clocked into the shift register. A nodes CS input must be
low to allow data to be clocked. Thus, CS is used to specify the intended recipient.
One direction SPI requires three signals; CLK, DIN and CS . By observating the
data line at clock cycles one can decode the frame. See appendix A.6 and A.7.
17
2.8.2 µC vs. FPGA vs. Digital USB I/O Device
A micro-controller, FPGA or Digital USB pod provides the necessary function of
commanding the SPI bus. A Field Programmable Gate Array was not chosen because
the entire team did not know how to program a FPGA. A Digital USB I/O, such as
the National Instruments USB-6009, does not run embedded programs but relies on
the host PC. An USB I/O device programmed strictly with Matlab would provide
a clean solution. The downside of this approach is hardware support for SPI is not
readily available. Controlling SPI in software known as ”bit-banging” and increased
scope.
Micro-controllers such as the Texas Instruments MSP430 family run embedded
code and have hardware SPI support. Using a standard USB to UART micro con-
troller adds another abstraction layer between the PC and the micro controller. Both
host (PC) and device (µC) code is needed. The UART protocol is “user defined” and
this implementation uses ASCII characters. Using ASCII makes the bus inefficient,
yet easy to program and debug. MSP430 was chosen for ease of availability, stan-
dard C language programming, and an excellent reference “MSP430 Microcontroller
Basics.”
2.8.3 Hardware Based SPI
MSP430 offers a hardware assist for SPI the Universal Serial Communication Inter-
face. USCI is setup using control registers. Data is loaded into a register and then
the hardware (not the CPU) automatically clocks out that register synchronized with
CLK. The state machine is managed by hardware and mostly abstracted from the
programmer. The only signal controlled by software is CS .
18
2.8.4 PC Integration
Simple versions of MSP430 which were used do not have direct USB support. USB to
UART conversion is done on the LaunchPad development board. The micro controller
code only sees the UART. MSP430 also has hardware support for UART on another
instance of the USCI. On the PC side, UART is emulated using a serial port, although
a true serial port never physically exists. Matlab was chosen to perform PC software
operations and integrate measurement instruments.
19
Chapter 3
Design and Implementation
3.1 Partition of Existing LSB
Assuming the architecture of floating a DAC off another is valid and will work, a
choice concerning partition of the existing coarse LSB is still needed. In other words,
when and by how much should the coarse DAC be incremented? To decide how many
VLSB−FINE fit in a single VLSB−COARSE examine equation (3.1):
VLSB−COARSE
VLSB−FINE
=
(VREF−COARSE
212
)(
VREF−FINE
212
) =VREF−COARSE
VREF−FINE
= n∗ (3.1)
where n∗ is the number of fine LSBs which fit into a single coarse LSB. As will
be explained in section 3.2.1, references were not used for the floating DAC so
VREF−FINE = VFLOAT . In reality n∗ is not an integer. Only finite numbers of fine
LSBs are available so n∗ cannot be the number of fine LSBs per coarse LSBs. An
integer n must be chosen. Note, fine DAC range spans more than one coarse LSB so
n can be scaled as long as coarse DAC then increments more than one LSB at a time.
Integer n is defined as:
n =Fine DAC increments
Coarse DAC increment(3.2)
Choosing n effects monotinicity and can create increments greater than 1 fine DAC
LSB. Consider the following examples:
20
3.1.1 Example: Choosing n for VREF−FINE = 3.361V
Assume VREF−FINE = VFLOAT−V DD = 3.361V which is the case for appendix A.2.
VREF−COARSE is 60V. Assume VCOARSE happens to be at 15.0000V (code 1024 by
equation (2.4) ) and VFINE is at 1.6411V (code 2000). Coarse DAC is only increment-
ing 1 LSB at a time and we wish to partition coarse LSB (the gap between C1024
and C1025) using fine DAC, thus increasing the resolution. The LSB of the entire
system and n must be determined. Using equation (2.3) for VLSB:
VLSB =3.361V
212= 0.82mv/LSB (3.3)
n∗ =VREF−COARSE
VREF−FINE
=60V
3.361V= 17.85 (3.4)
Rounding n∗ to 18 and choosing n = 18 is a bad choice. To see why, start incrementing
fine DAC as shown in table 3.1 When the coarse DAC increments from 1024 to 1025
Table 3.1: Incrementing with rounded n.
COARSECODE VCOARSE FINECODE VFINE VOUT
......
......
...1024 15.0000 2000 1.6411 16.64111024 15.0000 2001 1.6419 16.64191024 15.0000 2002 1.6428 16.6428
......
......
...1024 15.0000 2016 1.6542 16.65421024 15.0000 2017 1.6551 16.65511024 15.0000 2018 1.6559 16.65591025 15.0147 2000 1.6411 16.65581025 15.0147 2001 1.6419 16.6565
......
......
...
and fine DAC “resets” to 2000, the output actually goes down! This constitutes loss
of monotonicity (Carusone et al., 2012). Said simply, ”the output was expected to go
up, and it went down”.
21
The obvious solution appears to be choosing n = 17, meaning, use a floor function
on n∗ = 17.85 to get n = 17. However, n = 17 has a subtle drawback as well.
Again, increment fine DAC in table 3.2 to see the problem. First, for perfectly
Table 3.2: Incrementing with floor function n.
COARSECODE VCOARSE FINECODE VFINE VOUT
......
......
...1024 15.0000 2000 1.6411 16.64111024 15.0000 2001 1.6419 16.64191024 15.0000 2002 1.6428 16.6428
......
......
...1024 15.0000 2016 1.6542 16.65421024 15.0000 2017 1.6551 16.65511025 15.0147 2000 1.6411 16.65581025 15.0147 2001 1.6419 16.6565
......
......
...
nominal increments the output is strictly monotonic. However when the Fine DAC
”resets” and coarse DAC increments ∆V = 16.6558 − 16.6551 = 0.70mV which is
smaller than the ideal 0.82mV/LSB. Clearly, having 19 fine DAC increments makes
loss of monotonicity more profound. Only having 16 fine DAC increments gives
∆V = 16.6558−16.6542 = 1.6mV is monotonic but brings into question whether the
claim of 0.82mV/LSB can still be made. For now, n with strictly monotonic nominal
steps is chosen as ideal.
n ≡ Floor Function
(VREF−COARSE
VREF−FINE
)= Floor Function
(60V
3.361V
)= 17 (3.5)
3.1.2 VLSB at Coarse DAC Increment Boundary
Assuming that VREF−FINE does not divide evenly into VREF−COARSE then a separate
definition for VLSB is needed for the transition where fine DAC resets and coarse
DAC increments. In section 3.1.1 for n = 17, one out of every seventeen codes has
a different VLSB definition called VLEFT−OV ER. In fact VLEFT−OV ER is not an LSB.
22
Rather, VLEFT−OV ER is a bi-product of the remainder of division of the fine and coarse
reference voltages.
VLEFT−OV ER ≡ VCOARSE−LSB − n ∗ VFINE−LSB (3.6)
3.1.3 Fine DAC Offset Relationship to Changes in VDD−FLOAT
Choosing that starting code for fine DAC is not arbitrary. Inspecting equation (2.6)
reveals unintentional variance in VREF−FINE will cause variation in output as well.
Deciding to forgo a dedicated VREFF INE means the reference is the top rail supply
of fine DAC which is VDD−FLOAT . To minimize overall change in VOUT caused by
changes in VREF−FINE, the fine DAC starting code should be kept minimum. Rather
than choosing 2000 as fine DAC starting code, as in 3.1.1, a better starting code is
200. Choosing 200 and incrementing to 217 then resetting to 200 has the effect only
∼5% of a variation in VREF−FINE will actually be observable in VOUT .
3.1.4 Observations Related to LSB Partitioning
Precisely preserving the exact VLSB of the fine DAC over the entire coarse DAC range
is likely impossible. The previous considerations assume everything to be precisely
nominal. As expected neither coarse nor fine DAC perform precisely at nominal. The
problem of partitioning coarse LSB becomes even more troublesome when allowing
for variation. Unique observations discovered by analyzing nominal values are:
1. A floor function must be used to decide the number of partitions.
2. VLSB will not be precisely preserved throughout the entire coarse DAC
range unless VREF−FINE divides evenly into VREF−COARSE.
3. The offset where fine DAC starts incrementing and decrementing in its
limited range is not arbitrary.
23
3.2 Component Selection
3.2.1 Low Voltage DAC
Floating DAC can be chosen from a plethora of off-the-shelf low voltage DACs. The
critical constraints are SPI control and <300 µA quiescent current. Candidate prod-
ucts were Analog Devices AD5620 and Texas Instruments DAC7512. Having a ref-
erence voltage or merely using the upper rail as the reference must be decided. Ded-
icated separate VREF insures that VOUT will not change if the upper rail which is
VDD−FLOAT changes. Internal band-gap references consume about 40µA and external
references at minimum consume about 30µA. External references increase part count,
cost and footprint, and were not seriously investigated.
A voltage reference was not used because research requirements emphasized mV/
LSB and not absolute accuracy compared to 0V earth ground. Testing was done
on VDD−FLOAT as VCoarse varied using the LDO. Observation showed VDD−FLOAT
changed by only millivolts. The incremental quiescent current of a reference is too
big a loss for minimal, if any benefit to resolution. Texas Instruments DAC7512 is
the lowest power DAC found that has hand solderable leads. DAC7512 is used in all
versions.
Foreshadowing to section 4.6, the most important criteria of Floating DAC is
none of the above! Floating DAC quiescent current must remain absolutely constant
while switching its output. Changing quiescent current has adverse effects on overall
differential nonlinearity. Floating DACs selected were switched resistor architecture.
Quiescent current will change as resistors are switched in and out. A capacitor based
charge redistribution architecture may have provided a more constant quiescent cur-
rent.
24
3.2.2 Voltage Regulator, Low Drop-Out
Few LDO’s are available which meet essential criteria of VDD up to 64V and <300 µA.
Linear Technologies LT-3010 meets all criteria and was used in 16 and 1024 channel
versions. Texas Instruments TPS7A1601-Q1 almost meets the VDD up to 64V and has
only 15µA of quiescent current. To quantify the benefit of lower quiescent current
and consequence of exceeding maximum VDD the TPS7A1601-Q1 was used on the
single channel PCB of appendix A.2. Before final deployment with VDD at 64V on
the TPS7A1601-Q1, more rigorous testing is required.
3.2.3 Signal Level-Shifter
Choosing a single ADuM1300 or three of ADuM1100 for level shifting significantly
affects floating side quiescent current. Analog Devices implements the 3 signal dif-
ferently than merely putting 3 single signals on one chip. Single signal version
ADuM1100 uses a dedicated transformer for rising edges and DC logic high and a sep-
arate transformer for falling edges and DC logic low (Chen et al., 2003). Multi-signal
iCouple isolators use a single transformer for rising and falling edges. Multi-channel
versions rely on additional encoding to differentiate rising and falling edges at both
transmitter and receiver. The reason for using one transformer for both high and low
is not given in Chen et al. 2003. Potential rationale is to decrease space on the die to
fit multiple signals. Testing concludes multi-signal iCouplers require about 3 times
more quiescent current per isolated signal than single signal versions.
Choosing between three single-signal or one three-signal appears discretionary as
both work. In order to gather results from both methods, both were tested. To reduce
part count and cost, the 16 and 1024 channel versions were designed using a single
ADuM1300 per floating DAC.
25
3.3 Single Channel Design
To demonstrate concept a single channel prototype board (”breadboard”) version was
built. The schematic was created by using guidelines in respective data sheets. The
schematic for the first single channel design is in appendix A.1.
3.3.1 Prototype Board, Single Channel
Prototype board version is shown in figure 3·1 using schematic of appendix A.1.
Simple tests of incrementing the Fine DAC were done to show resolution was under
3mV/ LSB. The µC used here is MSP430G2452 and hardware SPI was done using
USI. After this model, the MSP430G2553 was used because hardware UART support
was available. Using G2553 also meant switching from USI to USCI.
Figure 3·1: Single Channel Floating DAC on prototype board
3.3.2 Printed Circuit Board, Single Channel
A single channel version on a PCB was used to examine results if all the lower power
components were used. Texas Instruments TPS7A1601-Q1 voltage regulator, three
of ADuM1100, and DAC7512 were used. As previously noted, the maximum VDD of
26
TPS7A1601-Q1 was knowingly exceeded. The schematic of the PCB version of single
channel can be seen in appendix A.2. Two layer PCB layout of single channel is in
appendix A.3.
3.4 16 Channel Version
USB
CoarseAnalog
DATA
Fine Analog Mirror
PC
HV_DAC_a6 FLOATING_DAC
P25
Ja
J3 J2
Ja
GND
VDD
GND
VDD
MIRROR BIAS
Figure 3·2: Architecture of 16 floating DAC channels.
Prior to designing 1024 channels, a 16 channel floating DAC was made to confirm
multi-channel specific design techniques. The 16 Channel version is broken into 3
modular and stand-alone segments, in figure 3·2. The controller was an off-the-shelf
MSP430 Launch Pad with MSP430G2553 loaded. The controller’s 20 male pins plug
into the custom PCBs female headers. A “16 Coarse Board” receives the MSP430,
high voltage VDD, and has 4 of AD5504 for 16 channels total and 2 shift registers to
expand the I/O to enough for Row and Column select. The coarse board is standalone
and can be independently tested.
16 floating channels were implement on “16 Fine Board.” Fine Board was also
designed so it could be independently developed and tested. Fine Board can optionally
27
use either earth ground or Coarse Board for the floating channel grounds. Fine Board
implements a row and column CS scheme using 0V referenced NAND devised by
Chris Woodall. CLK and DIN are wired identically to each channel. 16 Fine Board
predominantly replicate’s the proto board cell design sixteen times and also includes
a provision for sixteen CS. Researcher Chris Woodall was the lead designer of 16 Fine
Board.
Both boards required some minor post-fabrication rework. 16 Coarse and Fine
were successful and integrated to each other to achieve a 16 channel floating precision
DAC.
3.5 256 Channel Version
To achieve the required 1024 channel, a board with 256 floating channels was designed.
4 of the 256 channel boards are used as the architecture shown in appendix A.11.
Each 256 board has decoders to expand into 256 CS lines from the 10 address lines
of the control board. David Freedman was the lead designer of the 256 board and CS
decoder.
3.6 Test Apparatus
Working with deformable mirrors requires significant expertise, clean room and ad-
vanced optical instrumentation. The scope of this research was limited to testing
which confirmed performance of the output voltage. It was conjectured that if the
driver output has a certain VLSB then the surface of the DM will be moved by a
specified amount.
Measuring single mV changes over a 60V requires select methods and equipment.
Desiring an error which is 10% of 1mV over a 100V range requires about 1 part per
28
million of error in the measuring instrument. This is analogous to having a stack of
nickels a mile high and being able to distinguish each nickel, a formidable challenge!
3.6.1 Measuring Milli-Volts Over 100V Range
Measuring milli-volts over a 60V range was not feasible on an oscilloscope. The noise
floor when using 10X probes (10MΩ total) was about 20mV. If a 1X scope probe was
used then the noise floor decreased but the instrument restricted the vertical scale to
a max offset of 5V.
High accuracy multimeters such as Agilent 34461 and Agilient 34410 are certi-
fied to the required precision. Voltage range of 100V and 10 Power Line Cycles
per measurement are required to deliver 1ppm error and 100µ V accuracy (Agilent
Technologies, 2013). The consequence of 10 PLC is each measurement takes about
1 second (observed) when automated. Using 100 PLCs increases time to automated
measurement to about 6 seconds. These times are large when 4096*17≈70k measure-
ments must be made for a full sweep. The time for a complete sweep of all values is
about 22 hours for 10 power line cycles per measurement.
Test and power supply leads have an effect when only 1ppm error is tolerated.
Test leads for voltage need to be shielded coax with only a small portion of single
wire lead to the probe. Power supply cables need to be kept away from high current
lines or appliances. The distance between V+ and V− probe must be kept to a
minimum. The test apparatus is seen in appendix A.4.
29
Chapter 4
Measured Results
4.1 Minimum Increment Stepping
The goal of this research is to allow analog voltages of smaller increment than the
existing VCOARSE−LSB = 14.7mV . Inspecting figure 4·1 gives the appearance mission
accomplished! Not so fast, this graph is a very small portion of the 4096∗17 = 69, 632
codes which complete the entire range. When the entire range is inspected 1 by 1
using an automated test bench a host of problems appear. The first issue is poor
performance near the extremes of coarse DAC. As a result all further testing and
analysis is restricted to coarse DAC codes from 50 to (4096− 50) = 4046. Problems
of DNL and monotonicity also appear and require more in depth analysis.
4.2 Differential Nonlinearity
Differential Non-Linearity is the most important metric for Deformable Mirror appli-
cations. DNL allows a claim of VLSB to be guaranteed monotonic. Two designs were
presented in chapter 3 with the biggest difference being a single ADuM1300 isolator
or three of ADuM1100 isolators. ISINK is approximately 520µA or 120µA respec-
tively. To determine which design will perform better, the DNL of each is analyzed
over the entire range. DNL for any code i is defined by equation (4.1). Note that i
is a composite of both a coarse and a fine code. DNL said simply is, the amount the
30
Figure 4·1: Transfer function of Floating DAC. Floating DAC designappendix A.2, n = 16, starting fine command 200. For comparisonVCOARSE−LSB which was status-quo prior to floating DAC is also shown.
output actually changed in one LSB increment compared to a perfect VLSB.
DNL(i) = [VOUT (i)− VOUT (i− 1)]− VLSB (4.1)
This textbook definition of DNL needs one correction to be applied to cases where
DACs are stacked on top of each other as in the floating DACs of this research. Look-
ing back to section 3.1.2 for a floating DAC, the expected voltage change is not always
VLSB but sometimes is VLEFT−OV ER. Accordingly, DNL becomes conditionally de-
fined as:
DNL =
[VOUT (i)− VOUT (i− 1)]− VLEFT−OV ER, if VCOARSE(i− 1) 6= VCOARSE(i)
[VOUT (i)− VOUT (i− 1)]− VLSB, otherwise
(4.2)
Two observations are made from figure 4·2:
1. Lower quiescent current design using 3 of ADuM1100 performs better.
31
(a) (b)
Figure 4·2: Differential Non-Linearity measured by appendix A.4 withammeter shunted, 10 PLC: (a) Design A.1 functionally implemented asa single channel of the 16 channel board, fine DAC command increment-ing 200 to 220; and (b) Design A.2, fine DAC command incrementing200 to 216.
2. DNL can exceed -1 LSB
Because designs with lower quiescent perform better most further testing done will
be performed on design shown in appendix A.2. The problem of DNL exceeding -1
LSB of the fine DAC suggests the entire DAC may not be monotonic!
By inspecting equation (4.2) it is apparent that DNL(i) < −VLSB if and only if
[VOUT (i)− VOUT (i− 1)] < 0. However [VOUT (i)− VOUT (i− 1)] < 0 means the output
actually decreased when it was commanded to increase! To conclude; DNL(i) <
−VLSB means a loss of monotonicity. Note in the preceding argument, if step i in
question involves incrementing coarse DAC than VLSB is actually VLEFT−OV ER.
4.3 DNL Shown by Transfer Function
Figure 4·2 (a) implies the ADuM1300 design in not strictly monotonic. DNL exceeds
both VLSB and VLEFT−OV ER so places must exist where the transfer function is not
32
monotonic. To find such a code i the step VSTEP (i) is calculated for each point:
VSTEP (i) ≡ VOUT (i)− VOUT (i− 1) (4.3)
A script then finds and sorts any negative steps. A negative step is not monotonic.
4.3.1 Non-monotonic Stepping at Coarse DAC Boundary
To explicitly see the lack of monotonicity of the ADuM1300 design; the transfer
function is inspected in figure 4·3. An excerpt of the raw data produced by the
automated test bench at the point in question is shown in table 4.1. The natural
suspicion is that this non-monotonic example is at a boundary of coarse DAC values,
namely between command C1279 and C1280. Boundaries of coarse DAC have been
previously noted to be problematic. Perhaps, non-monotonic points at the coarse
DAC boundary could be eliminated by simple decreasing from n = 20 to n = 19.
However, non-monotonic points exist when coarse DAC is kept perfectly constant.
Figure 4·3: High quiescent current design appendix A.1 is not mono-tonic between commands C1279+F220 and C1280+F200.
33
Table 4.1: Data showing change in sign of transfer function at coarseboundary.
Coarse Command Fine Command Measured VOUT
......
...1279 219 18.914611279 220 18.915081280 200 18.914621280 201 18.91535
......
...
4.3.2 Non-monotonic Stepping with Constant Coarse DAC
With the coarse DAC command kept constant, non-monotonic codes still exist. See
figure 4·4 and table 4.2. This is a profound curiosity. Although only one case is shown
about 200 such cases are revealed when querying for negative step size in the complete
data set of high quiescent current design. This design closely copies appendix A.1
but was implemented on a 16 channel board. One channel was completely isolated
for these tests and control firmware and software was identical to the single channel
board.
Table 4.2: Data showing change in sign of transfer function with coarseDAC constant.
Coarse Command Fine Command Measured VOUT
......
...2447 208 36.003552447 209 36.004652447 210 36.002452447 211 36.00606
......
...
4.3.3 Possible Causes of Loss of Monotonicity with Constant Coarse
Command
1. Fine DAC itself is not monotonic.
34
Figure 4·4: High quiescent current design appendix A.1 is not mono-tonic between commands C2447+F209 and C2447+F210. It is non-monotonic with coarse DAC constant command.
2. Coarse DAC output spuriously drifts over time.
3. Coarse DAC output is affected by changes in iSINK .
4.4 Monotinicity of Low Quiescent Current Design
Low quiescent current design in appendix A.2 is almost strictly monotonic. On the
single PCB with n = 17, the coarse DAC boundary change was prone to loosing
monotonicity. However, with n = 16, only 5 data points out of 67932 were not
monotonic! The ideal test conditions were n = 16 and fine DAC starting code of 200.
All 5 of the non-monotonic codes are listed in table 4.3.
The corresponding DNL graph which includes the 5 aforementioned data points
is figure 4·2 (b). A temptation is to look at figure 4·2 and draw the conclusion
that because more than 5 points exist where DNL(i) < VLSB then more than 5
non-monotonic codes must exist. The essential note is that for any given point in
35
figure 4·2 the condition for monotonicity is unclear. Either DNL(i) < −VLSB or
DNL(i) < −VLEFT−OV ER is the condition for monotonicity. Calculating VLEFT−OV ER
from equation 3.6:
VLEFT−OV ER ≡ VCOARSE−LSB−n∗VFINE−LSB =60
212−16∗
(3.361
212
)= 1.5mV (4.4)
Now looking back to figure 4·2 it appears that DNL(i) is never < 1.5mV . Meaning
that any non-monotonic points cannot occur at a coarse DAC boundary. This is
exactly confirmed by table 4.2. However 5 anomalous non-monotonic codes still exist
for this design.
Table 4.3: All non-monotonic codes of design in appendix A.2
Coarse Command Fine Command VSTEP (i) (µV)513 208 -141188 205 -312645 210 -34393 210 -69540 212 -419
4.5 DNL vs. Fine DAC Code
A relationship between fine DAC code and DNL may offer relief from DNL. If certain
fine DAC codes or powers of 2 have high DNL, they could intentionally be avoided.
Figure 4·5 suggests no fine DAC code in the range 200...216 had particularly high
DNL. Figure 4·5 does suggest DNL is high at coarse DAC boundaries when fine DAC
reset to 200 and coarse DAC increments. This is expected and luckily it is not worse!
The datasheet of AD5504 implies typical DNL around 3mV. That would have been
disastrous. VOUT would have had a corresponding DNL anytime the coarse DAC
changed.
36
Figure 4·5: DNL vs. fine DAC code, design appendix A.2, n = 16. finestarting command of 200, test apparatus A.4 with ammeter shunted.
4.6 DNL Correlation with ∆iSINK
Revisiting section 4.3.3 two of the hypothesis are readily dispelled. High precision
multi-meters simultaneously monitored VCOARSE and VFINE and the floating DAC
of appendix A.1 was stepped through a known non-monotonic sequence. VFINE re-
mained monotonic. However, VCOARSE decreased at certain changes in fine DAC
command even when coarse DAC command was held constant. This lead to the sus-
picion that the quiescent current of fine DAC is changing with certain fine DAC codes
and causing VCOARSE to vary and subsequently VOUT looses monotonicity.
A test using appendix A.4 was done to attempt to correlate DNL to ∆iSINK .
4.6.1 Changing Floating DAC Quiescent Current
A correlation between the change in quiescent current and DNL does exist. This can
be seen in figure 4·6. Note the DNL results of figure 4·6 are worse than figure 4·2
even though the device under test is identical! Figure 4·6 actually has the ammeter
37
of appendix A.4 in use while the conditions for figure 4·2 has the ammeter shunted.
Simply having the ammeter in series with the floating supply degrades DNL perfor-
mance. A precise correlation between DNL and ∆iSINK cannot be made. However a
reasonable observation is they are related.
Figure 4·6: DNL vs. ∆iSINK , low quiescent design appendix A.2,n = 16. fine starting command of 200, test apparatus A.4.
4.7 Power Consumption
Power was monitored while the SPI bus was running with a 100kHz clock. Power
consumption will change as update and bus rates change. To calculate power the DC
voltage seen by a particular device is not most relevant. The salient voltage is the DC
supply where a particular current originated. As an example, examine when the fine
DAC draws 1mA of current and VDD−FLOAT is 3V . A temptation may be to conclude
power is 1mA ∗ 3V = 3mW . That is true at the fine DAC itself. However the system
sees 1mA ∗ 64V = 64mW because the current originated from a 64V supply. The
LDO linearly (resistively) created the 3V from (64V −VCOARSE). The ”extra” 61mW
38
are dissipated by some combination of the LDO and coarse DAC. Reported results
are powers as seen by the system. System power is likely more useful for power supply
budgeting.
4.7.1 Power of High Quiescent Current Design Appendix A.1
Table 4.4: Power of appendix A.1, VDD−FLOAT = 2.83V .
Identifier Current Voltage Power. . . . . . . . . Earth Ground Side . . . . . . . . . . . . . . . . . .5504 Logic 176nA 3.566V 628nW5504 Analog 455µA 64V 29mWADuM1300 Primary 950µA 3.566V 3.4mW
. . . . . . . . . Floating Side . . . . . . . . . . . . . . . . . .ADuM1300 Secondary 380µA 64V 24mWDAC7512 104µA 64V 6.7mWLT3010 Quiescent 56µA 64V 3.6mW
Floating Side Total Current =540µA
Sum per channel 60mW
4.7.2 Power of Low Quiescent Current Design Appendix A.2
Appendix A.2 was never implemented on a prototyping board. To measure all cur-
rents exactly for each component would have been cumbersome on the PCB. That
would have required drilling and breaking many traces and soldering on temporary
leads. Instead, component current was tested on the bench attempting to replicate
conditions of the board. Bench readings were then used to appropriate the observed
total power of the board. Total floating side power could be exactly measured by
jumper “J1.” The total power of table 4.5 is correct but the percent going to any one
component may be slightly different.
39
Table 4.5: Power of appendix A.2, VDD−FLOAT = 3.361V .
Identifier Current Voltage Power. . . . . . . . . Earth Ground Side . . . . . . . . . . . . . . . . . .5504 Logic 200nA 3.566V 713nW5504 Analog 400µA 64V 26mW3 of ADuM1100 Primary 700µA 3.566V 2.5mW
. . . . . . . . . Floating Side . . . . . . . . . . . . . . . . . .3 of ADuM1100 Secondary 40µA 64V 2.6mWDAC7512 60µA 64V 3.8mWTPS7A Quiescent 15µA 64V 1mW
Floating Side Total Current =115µA
Sum per channel 36mW
4.8 16 Channel Version, Functional Check Driving a Mirror
The entire 16 floating DAC with controller (appendix A.10) was tested on a de-
formable mirror. The goal was to demonstrate end-use functionality. The test was
done in a clean room with an interferometer observing the face of the mirror. The
coarse DAC was held constant and fine DAC was changed until a difference in the sur-
face profile was noticed. Interferometer results confirming DM face deflection caused
by fine DAC are appendix A.13. A ∼1mV change in VOUT would result in surface
deflection on the order of 10 picometers. Observing a 10pm deflection is difficult and
outside the scope or this research.
4.9 1024 Channel Version, Functional Check With Multime-
ter
1024 channels implemented as appendx A.11 were tested by a voltmeter. The 1024 ar-
chitecture was not tested on a mirror by this research. Voltmeter tests confirmed func-
tionality. Performance was very similar to results previously discussed for the “high
quiescent current” design of appendix A.1. Several problems related to high den-
sity connectors were found. This resulted in not all channels working all the time.
40
However, these connector issues were not deemed to be inherent to the floating DAC
architecture.
41
Chapter 5
Discussion
5.1 ADuM1100 vs. ADuM1300
5.1.1 DNL and Monotinicity
ADuM1100 designs perform better in this application. The DNL is on average smaller
and the extremes are smaller as well. ADuM1100 designs approach only 15% of the
current limit of the coarse DAC, AD5504. ADuM1300 designs use around 60% of
the current limit of the coarse DAC. Measured results suggest operating closer to
the coarse DAC current limit degrades the coarse DAC’s ability to hold a constant
voltage in light of changing sinking current.
5.1.2 Power
Lowest power designs need to use the ADuM1100. The ADuM1300 complete design
used almost twice the current per channel. Testing to understand the precise data
rate to current ratio is needed before a final deployment. This is especially important
for floating DAC applications because floating side quiescent currents affect DNL and
monotonicity.
42
5.1.3 Foot Print and Cost
ADuM1300 encapsulates three isolated signals per chip. This saves on both cost
and footprint. PCB area of three of ADuM1100 will exceed a single ADuM1300.
Taking into account decoupling capacitors and space for signal routing, the three
ADuM1100’s footprint will exceed the ADuM1300 by around 100%. For an en-
tire cell of one floating channel the PCB area goes up perhaps 50%. The cost
of using three ADuM1100s is at least three times more expensive than a single
ADuM1300. If ADuM100s were used to isolate 1024 floating channel, the cost for
just the ADuM1100s is around 3*1024*1.81 =5560.
5.1.4 Single Channel PCB Design vs. 16 Channel PCB Design
The single channel board with ADuM1100s has smaller DNL and is lower power. The
design of appendix A.2 outperforms appendix A.1 in all categories except footprint
and cost. Optimum final design is appendix A.2 with LT-3010 used as the LDO.
5.2 Minimum Increment LSB
The low quiescent current design of appendix A.2 is chosen. An incrementing scheme
and VLSB must be defined.
5.2.1 Implications to Control and Feedback
Adaptive optics use closed loop feedback control. Non monotonic codes present a
serious problem to the control system. The controller will give a command expecting
the output to improve and instead it will get worse! Perhaps then, the control system
goes the other way. The output will continue to get worse! The controller will reverse
again, right back towards the non-monotonic code and the cycle repeats! To avoid
43
driving eventual programmers crazy or getting the control loop stuck, only monotonic
steps are chosen.
5.2.2 Monotonic LSB
Looking at figure 4·5 if overall floating VLSB is defined as 2 ∗ VLSB−FINE−DAC , then
the system is completely monotonic. This comes at the expense of VLSB increasing
from 820µV to 1.64mV. This concession is made to make the claim of monotinicity.
5.2.3 Stepping with Monotonic LSB
Implementing an overall LSB which is 2 LSBs of the fine DAC, affects the stepping
sequence. The concept of stepping 2 fine DAC codes at a time proceeds as table 5.1.
Figure 4·5 predicts that if the minimum step size is 2 fine LSBs all codes will be
monotonic. n is still 16 but now only 8 increments are required to get to 16.
Table 5.1: Concept of incrementing 2 fine DAC codes at a time,VREF−COARSE = 60, VREF−FINE = 3.361.
COARSECODE VCOARSE FINECODE VFINE VOUT
......
......
...1024 15.0000 200 0.1641 15.16411024 15.0000 202 0.1658 15.16581024 15.0000 204 0.1674 15.1674
......
......
...1024 15.0000 214 0.1756 15.17561024 15.0000 216 0.1772 15.17721025 15.0147 200 0.1641 15.17861025 15.0147 202 0.1658 15.18041025 15.0147 204 0.1674 15.1820
......
......
...
44
5.3 n = 16 vs. n = 17
The tradeoff of making the choice n = 17 compared to the actual decision n = 16
is significant. VLEFT−OV ER was ”inflated” to 1.52mV by making n only 16. As
mentioned in section 4.4 only 5 of 68k codes were not monotonic. ”Inflation” of the
monotonic threshold at the coarse DAC boundary is seen in figure 4·5. The monotonic
threshold conveniently dog legs around a big clump of large negative DNL values in
figure 4·5. This came at the consequence of one seventeenth of steps being 1.52mV
instead of the ”normal” VLSB = 821µV .
Choosing n = 17 causes the monotonic threshold in figure 4·5 to go right through
the clump of largely negative DNL values! VLEFT−OV ER for n = 17 is only 698µV .
Running a test with n = 17 recorded 47 non monotonic codes out of 72k. The benefit
of n = 17 is the nominal step size between any two codes is 821µV maximum.
5.3.1 DNL of Coarse DAC
Experimental results show n = 16 has less monotonic code than n = 17. This
is explained by the DNL or coarse DAC itself as a stand alone component. The
datasheet of AD5504 reports typical DNL of 14LSB = 1
414.7mV = 3.6mV . Luckily
the datasheet must report a conservative estimate or test condition were used to
simulate a worst case load. However, the DNL of coarse DAC is significant compared
to 1mV. That is the reason codes where fine DAC resets and coarse DAC increments
are more prone to high DNL than codes where coarse DAC is held constant.
45
5.3.2 Definition of nIDEAL
A definition for n which balances the goal of avoiding non-monotonic step with an
undesirably high VLEFT−OV ER is needed. nIDEAL formalizes observed results.
nIDEAL ≡ Floor Function(VCOARSE−LSB
VFINE−LSB
)− 1 (5.1)
Equation 5.1 has one subtracted from it, as compared to equation 3.5.
5.4 Explanation for DNL to ∆iSINK Correlation
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Title
Number RevisionSize
A
Date: 6/30/2014 Sheet of
File: X:\Desktop\aa\output_amp_idealaSchDoc Drawn By:
1a713M
R_f
122a36kR_1
GND
DAC
B_0B_1B_2aaaB_11
aV_COARSE
I_sink
I_amp
I_f
V_a
PI00V0CO0
PIR0101
PIR0102COR01PIR0f01 PIR0f02
COR0f
Figure 5·1: Ideal model of AD5504 output copied from the datasheet,annotations added.
No reason for the phenomenon of figure 4·6 is presented in section 4.6. This phe-
nomenon is the performance constraint of the entire design! Looking at the internals
of the AD5504 as described in the datasheet as in figure 5·1. The implication is the
output amplifier is ideal. Ideal amplifier assumptions are:
1. Zero output resistance.
2. Infinite open-loop gain.
46
1a713M
R_f
122a36kR_1
GND
DAC
r_out
B_0B_1B_2aaaB_11
+V_COARSE
I_sink
I_amp
I_f
V_a
Ao*aV+ -- V-)
PI00V0
CO0
PIR0101
PIR0102COR01
PIR0f01 PIR0f02COR0f
PIr0out01 PIr0out02COr0out
Figure 5·2: AD5504 output considering non-idealities.
3. Infinite input resistance.
Perhaps input impedance is close to infinite because the input is a CMOS gate.
However, assumptions 1 and 2 are not precisely correct. Open loop gain A0 is certainly
not infinite and estimating a value experimentally is difficult. Output resistance rout
is not 0Ω. This is most evident because the max output current is 1mA at 60V.
5.4.1 Non-ideal Coarse DAC Model
Taking the non-idealities into account the coarse DAC model is figure 5·2. Reconsid-
ering the observations of section 4.6 an argument can be made:
1. As observed, greater ∆isink correlates to greater DNL.
2. However, greater ∆iSINK is because ∆iSINK(i) > ∆iSINK(i− 1).
3. ∆iSINK(i) > ∆iSINK(i−1) means incremental current across rout for code
i compared to code (i− 1).
4. Incremental current across rout causes incremental voltage across rout.
47
5. Finite open loop gain A0 means this output voltage increase will not be
fully eliminated by the negative feedback loop.
6. Incremental undesirable voltage at rout causes an undesirable increase at
VOUT .
7. Undesirable increase at VOUT manifests as the observed increase in DNL.
Item (3) of section 4.3.3 is correct.
This research was restricted to integrating with an existing system. In context,
little can be done about the deleterious effects of rout and A0 < ∞. A solution to
DNL vs. ∆iSINK correlation is not offered yet an explanation is presented. Choosing
floating DACs which have almost perfectly constant isink as the fine command code
changes is desirable. Isolators should be chosen so the quiescent current is constant
regardless of transmitting or dormant. To reiterate, changes in quiescent current may
show up as an undesirable increase in DNL and potential loss of monotonicity.
5.5 Failure Mode of Abrupt Contact To Negative Potential
During testing and debug, an unfortunate failure mode was detected. If a user probes
VOUT or VDD−FLOAT with an instrument while floating DAC is powered up the entire
set-up may fail. Review the case VOUT = 51V with VCOARSE = 50V and VFINE = 1V .
Now, the unsuspecting engineer comes along with multimeter Agilent 34461A. The
input of 34461A is represented by a 10MΩ resistor in parallel with a worst case 120pF
capacitor. Suppose one lead is connected to 0V earth and the capacitor is discharged.
Now the other lead is touched (metal to metal, low resistance) to VOUT . Fine DAC
sees this as an abrupt capacitive load connected 50 volts below it’s own ground! This
exceeds fine DACs datasheet absolute maximum. Abrupt contact to earth ground
while powered up may break fine DAC or LDO or both on that one floating channel.
48
5.6 Untested Criteria
Several criteria which are regularly reported for generic DACs was not done for this
research. The end use of this DAC in a deformable mirror in a telescope eased several
constraints. Max update rate tests require a UART to the micro controller faster
than 9600 baud or a separate embedded program for the test.
5.6.1 Integral Nonlinearity
Integral Non-Linearity is the difference in commanded voltage and actual voltage.
INL defines error versus a fixed benchmark and DNL defines error versus two adjacent
codes. Adaptive optics are concerned with incremental steps and actual potential vs.
a fixed potential is not critical. INL was not tested. Figure 4·2 (b) shows DNL is
approximately zero sum. Also DNL does not drift steadily one way over the range. A
reasonable conclusion is INL will closely match INL reported on AD5504 datasheet.
5.6.2 Update Rate
Required update rate to achieve criteria was about 1 kHz for the entire 1024 solution,
meaning every channel can be update once per second. SPI clock of 100kHz was
chosen and used in tests. The level shifting technique used, and fine DAC7512 ac-
cept 50mbps and 30Mhz respectively. However, the ADuM1100 current consumption
goes up considerably. SPI clock running at 100kHz performs as reported in previous
sections. Clock rates higher than 100kHz require testing before deployment.
5.6.3 Settling Time
Settling time of the analog VOUT is determined by coarse DAC, fine DAC, load resis-
tance, and load capacitance. The settling times reported in AD5504 and DAC7512
were found with vastly different test conditions than a deformable mirror. End use
49
load capacitance is 150fF per DM actuator cell Horenstein et al. (2011). 150fF is so
little capacitance that wires, traces, and connectors may be the dominant capacitive
load. Estimating settling time based on data sheets and 150fF load could be signifi-
cantly inaccurate. All data reported in this research allows for a one second settling.
Actual settling time is likely much faster one second. Further testing is needed to
determine actual setting time.
5.6.4 Coarse DAC Incrementing More Than 1 LSB at a Time.
Coarse DAC can be stepped by more than one coarse LSB at a time. Examine the
situation where the 60 volt coarse DAC range should be broken into 32 partitions
of 1.875V each. Define the number of coarse DAC increments at each coarse DAC
boundary B = 4096/32 = 128. Calculate how many fine LSBs fit in 128 coarse LSBs
using a modified form of equation 3.5:
nMULTI ≡ Floor
(B ∗ VREF−COARSE
VREF−FINE
)= Floor
(128 ∗ 60V
3.361V
)= 2285 (5.2)
Applying the technique of subtracting 1 of equation 5.1 gives nMULTI−IDEAL = 2284.
VLSB will remain as before VLSB = 821µV. However, VLEFT−OV ER will change to:
VLEFT−OV ER−MULTI ≡ B ∗ VCOARSE−LSB − nMULT−IDEAL ∗ VFINE−LSB (5.3)
VLEFT−OV ER−MULTI = 128 ∗ 60V
212− 2284 ∗ 3.361V
212= 849µV
Coarse DAC incrementing more than 1 LSB at a time is somewhat confusing and
brings little benefit. If the entire Floating DAC design were only non-monotonic at
coarse DAC boundaries, then this would be helpful. This scheme reduces the number
of coarse DAC boundaries from 4096 to 32. However floating DAC demonstrated
50
it was non-monotonic at codes other than coarse DAC boundaries. This stepping
scheme has potential merit and could be used in floating architectures using coarse
DAC other than the AD5504. For the design in appendix A.2, using n = 16 and
incrementing 2 fine LSBs at a time is ideal.
51
Chapter 6
Conclusion
6.1 Proof of Concept
Floating one DAC off the output of another DAC is feasible. This technique relies on
three essential criteria:
1. Coarse DAC remains constant unless it’s code is changed.
2. A method for level shifting logic signals exists.
3. Constant floating supply voltage can be supplied to fine DAC as VCOARSE
changes.
4. DNL of coarse DAC does not significantly exceed eventual VLSB.
Floating architecture was demonstrated as valid.
6.2 Usability and Integration
Floating DACs can be used as a modular plug-in enhancement of existing systems
as was the case with this application. The modularity allows existing designs to be
preserved and remain as known working. Providing a stand alone upgrade to a system
is often highly desirable. The effect of increased resolution on the end use (in this
case a DM) may be unknown. Adding a floating DAC may allow quantifying the
benefit of increased resolution without engineering an entirely new solution.
52
This floating DAC design is made with readily available off-the-shelf components.
A cursory product search suggests this design exceeds resolution at the 60V range of
any off-the-shelf product. Avoiding custom designed and fabricated ASICs reduces
lead time and cost by orders of magnitude. Future researchers could use appendix A.2
as a template. Remaining design is then predominantly PCB layout and control
software.
Floating DAC is proven easily scalable to many channels. This research rigorously
analyzed a single channel. The research team demonstrated the concept remains
viable for 1024 channels. The biggest hurdle to 1024 channels was PCB design,
connectors and managing so many individual Chip Select signals.
Floating DAC “gets off the ground” quickly. A fully functional prototype board
model can be built and tested in a single day for less than $50. This document
attempts to provide helpful information including firmware, software, and bus scope
traces. Hopefully the low cost and useful information reduces barriers to entry to
implementing floating DACs.
6.3 Summary of Achieved Parameters
Optimal results of design appendix A.2 are summarized in table 6.1. The power
requirements of coarse DAC are included. In the specific application of appendix A.11
the coarse DAC already existed, so coarse DAC quiescent power is not considered
incremental. The research achieved the essential goal of < 3mV/LSB.
53
Table 6.1: Results summary, design appendix A.2.
Parameter Symbol Min Typ Max Unit Notes
LSB increment VLSB 1.52 1.64 mV
Resolution N 15.2 Bits equivalent
Differential Non-Linearity DNL -1 ±1/4 +1 LSB
Range 1 59 V VDD = 64V
Power 36 mW
6.4 Future Work
6.4.1 Ladder DAC Concept for High Voltages
Floating DAC architectures are well suited for very high voltages. This research has
only twice the resolution of a product such as TeledyneDalsa model DH9685A. Dalsa
has a high voltage CMOS process which enables them to offer a mirror driver ASIC.
However, suppose the goal is a 2000V volt, high resolution DAC. Analog Devices
iCouplerr can isolate up to 2000V. If constant DC voltages in increments of 50V
up to 2000V can be created, floating DAC architecture could be used. A method
for multiplexing the ground of the coarse DAC to different ”ladder rungs” would be
needed. Then, the overall DAC would have 3 stages. Potentially this could provide
millivolt resolution over two thousand volts!
6.4.2 Floating Power Using Transformer and Rectifier, AD isoPowerr
Providing floating using Low Drop-Out regulators is not ideal. Finding LDOs which
accept VDD as high as 64V is difficult. The other drawback is all floating side current
must be sunk by coarse DAC and disturb the output. The team investigated using
a transformer to cross the potential barrier and then rectify to provide VDD−FLOAT .
54
Implementing this with discrete components was too cumbersome.
After all designs were done, researcher Chris Woodall found Analog Devices
isoPowerr product line. These products provide both isolated power and logic isola-
tion on a single chip! This technique holds great promise and requires further inves-
tigation. This could potentially reduce part count by 30%. DNL may significantly
improve because iSINK would be close to zero.
6.4.3 Relaxed Resolution Requirement of HV DAC
Designing a floating DAC system from completely blank paper relaxes the resolution
requirements of the coarse DAC immensely. Reconsider the example of incrementing
1.875V worth of fine LSBs before incrementing coarse DAC in section 5.6.4. 12 bits
of resolution for coarse DAC were not needed. The exact same criteria could have
been met if coarse DAC only had 5 bits! Likely designing coarse DAC would be much
easier if only 5 bits were required.
All the benefits of floating DAC designs may only be realized if the floating capa-
bility used to ease design constraints of the coarse DAC. Floating architecture with
both coarse and fine DAC implemented on the same chip is possible. Better under-
standing the challenges of single stage high voltage DACs is needed. If warranted,
floating architecture could be intentionally designed into a DAC from early stages
and potentially ease overall design effort.
55
Appendix A
Appendix
A.1 Single Channel on Prototype Board Schematic, High
Quiescent
a-)
GND
a+)
64a0 V
1V_D
D1
6NC
2GND1
8GND1
7NC
5V_IC
4V_IB
3V_IA
16V_D
D2
11 NC
15GND2
9GND2
10 V_E2
12 V_OC
13 V_OB
14 V_OA
ADuM 1300
V_IN
8GND
4V_ADJ 2
LT3010
GND
9
SHDN5 V_OUT 1
NC3
NC6
NC7
USB aMini)
Vcc
P1.0
P1.1
P1.2
P1.3
P1.4
SCLK aClock)P1.5
P2.0
P2.1
P2.2
GND
P2.6
P2.7
TEST
RST
P1.7
SDO aData) P1.6
P2.5
P2.4
P2.3
M430G
2452
P1.0
P1.6
LED1
LED2
Vcc
TEST
RST
PWR
CLR1
SYNC2
SCLK3
SDI4
SDO5
DGND
6
AGND
7
LDAC8 VOUTD
9VOUTC
10VOUTB
11
VOUTA 12
RSEL13
Vdd
14
ALARM15 Vlogic
16
AD5504
GND
V_LOGIC
V_LO
GIC
V_LO
GIC
64Volts
64Volts
Floating_Ground
GND
Clock Data
GND
GND
V_DD_FLOAT
270K
220K
V_Out
V_D
D_FLO
AT
CS_Fine
Clock
Data
V_DD_FLOAT
Data
Clock
CS_Coarse
V_LOGIC
GND
SYNC6
SCLK5
DIN4
AGND
2
V_OUT 1
V_D
D3
DAC7512
CS_Fine
CS_Coarse
100nF
100nF
100nF
Floatin
g_Ground
V_D
D_FLO
AT
100uF
GND
V_D
D_F
LOAT
PI00(0)
PI00GND
CO0
PIC?01PIC?02
COC?
PIC?01PIC?02
PIC?01PIC?02
PIC?01
PIC?02
PIR?01
PIR?02COR?
PIR?01
PIR?02
56
A.2 Single Channel on PCB Schematic, Low Quiescent
a-)
GND
a+)
64.0 V
CLR1
SYNC2
SCLK3
SDI4
SDO5
DGND
6
AGND
7
LDAC8
VOUTD
9VOUTC
10
VOUTB
11
VOUTA12
RSEL13
Vdd
14
ALARM15
Vlogic
16
AD5504
GND
V_LOGIC
64Volts
64Volts
Floating_Ground
GND
V_DD_FLOAT
2.7M
R1
1.5M
R2
V_Out
CS_Fine
Clock
Data
V_DD_FLOAT
Data
Clock
CS_Coarse
V_LOGIC
GND
SYNC6
SCLK5
DIN4
AGND
2
V_OUT1
V_DD
3
DAC7512
10nF
C8
Floating_Ground
10uF
C12V_IN
8GND
4
FB2
TPS7A
EN5
V_OUT1
PG3
NC6
DELAY7
1601aQ1
J1
J2
GND
1V_DD1
4GND1
2V_I
8V_DD2
7GND2
5GND2
6V_O
ADuM 1100
3V_DD1
1V_DD1
4GND1
2V_I
8V_DD2
7GND2
5GND2
6V_O
ADuM 1100
3V_DD1
1V_DD1
4GND1
2V_I
8V_DD2
7GND2
5GND2
6V_O
ADuM 1100
3V_DD1
Floating_Ground
V_LOGIC
100nF
C6
GND
V_LOGIC
100nF
C5
GND
V_LOGIC
100nF
C4
GND
GND
GND
GND
Floating_Ground
Floating_Ground
Floating_Ground
V_DD_FLOAT
V_DD_FLOAT
V_DD_FLOAT
V_DD_FLOAT
100nF
C3
V_DD_FLOAT
100nF
C2
V_DD_FLOAT
100nF
C1
100nF
C9
1uF
C11
GND
PI00(0)
PI00GND
CO0
PIC101
PIC102COC1
PIC201PIC202
COC2
PIC301PIC302
COC3
PIC401PIC402
COC4
PIC501PIC502
COC5
PIC601PIC602
COC6
PIC801PIC802
COC8
PIC901 PIC902
COC9
PIC1101PIC1102
COC11
PIC1201PIC1202
COC12
PIR101
PIR102COR1
PIR201
PIR202COR2
57
58
A.3 Single Channel PCB
A.4 Test Apparatus
59
A.5 Single Channel Micro-controller Firmware
/*
* main.c
* Control AD5504 and DAC7512 from UART commands
* Jeffrey Kittredge, July 3, 2014
* Code Compose Studio V5.4.0
* Target MSP430G2553 on MSP-EXP430G2
*/
#include "msp430g2553.h"
#include <stdint.h>
#include <math.h>
#include "ascii2dec.h"
#include "uart_config.h"
#include "stateMachine.h"
#include "pinConfig.h"
#include "clockConfig.h"
#include "spiConfig.h"
#include "set7512.h"
#include "set5504.h"
uint16_t rxWord = 0x0000; //2 byte (4 hex digits) input word
unsigned char slaveStatus = IDLE; //state machine status
volatile uint16_t valueFor7512 = 0x0145; //0x0145 is about .278V
60
volatile uint16_t valueFor5504 = 0x7004; //0x7004= enable all AD5504
void main(void)
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
clockConfig();
pinConfig();
uartConfig();
spiConfig();
__bis_SR_register(GIE); //global interrupt enable
while (1) //continuously refresh
set7512( valueFor7512);;
__delay_cycles(4000);
set5504( valueFor5504);
__delay_cycles(4000);
//State Machine to parse the incoming UART bytes
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR(void)
61
if( IFG2 & UCA0RXIFG)
unsigned char data = UCA0RXBUF;
switch (slaveStatus)
case IDLE:
if ( data == SOH )
slaveStatus = READY_DEVICE_SELECT;
else
;
break;
case READY_DEVICE_SELECT:
if ( data == DC1)
slaveStatus = READY_MS_CHAR1;
else if ( data == DC2)
slaveStatus = READY_MS_CHAR2;
else
;
break;
//For the AD5504 COARSE DAC
case READY_MS_CHAR1:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 12 );
62
slaveStatus = READY_CHAR1_3;
break;
case READY_CHAR1_3:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 8 );
slaveStatus = READY_CHAR1_2;
break;
case READY_CHAR1_2:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 4 );
slaveStatus = READY_LS_CHAR1;
break;
case READY_LS_CHAR1:
rxWord = rxWord + asciiByteToDecByte( (uint8_t) data ) ;
slaveStatus = IDLE;
valueFor5504 = rxWord;
rxWord = 0;
break;
//For the DAC7512 FINE DAC
case READY_MS_CHAR2:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 12 );
slaveStatus = READY_CHAR2_3;
break;
63
case READY_CHAR2_3:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 8 );
slaveStatus = READY_CHAR2_2;
break;
case READY_CHAR2_2:
rxWord = rxWord + (asciiByteToDecByte( (uint8_t) data ) << 4 );
slaveStatus = READY_LS_CHAR2;
break;
case READY_LS_CHAR2:
rxWord = rxWord + asciiByteToDecByte( (uint8_t) data ) ;
slaveStatus = IDLE;
valueFor7512 = rxWord;
rxWord = 0;
break;
//set5504.h
#ifndef SET5504_H_
#define SET5504_H_
#include <msp430g2553.h>
#include <intrinsics.h>
64
#include <stdint.h>
void set5504( uint16_t dataOut);
// set analog devices AD5504 via SPI on UCB0 with ~CS on p1.4
// AD 5504 needs CKPH (clock phase) active
#endif /* SET5504_H_ */
//set7512.h
#ifndef SET7512_H_
#define SET7512_H_
#include <msp430g2553.h>
#include <intrinsics.h>
#include <stdint.h>
void set7512( uint16_t dataOut);
// set texas instruments DAC7512 via SPI on UCB0 with ~CS on p1.3
//the 7512 needs CKPH (clock phase) cleared
#endif /* SET7512_H_ */
//spiConfig.h
#ifndef SPICONFIG_H_
65
#define SPICONFIG_H_
#include <msp430g2553.h>
void spiConfig( void);
/*
* USCI-B
* Master
* SPI Mode
* Synchronous
* Most significant bit first
* Clock rate = SMCLK/ 10 = 1MHz / 10 = 100kHz
*/
#endif /* SPICONFIG_H_ */
//clockConfig.h
#ifndef CLOCKCONFIG_H_
#define CLOCKCONFIG_H_
#include "msp430g2553.h"
// configure the clocks
//CPU used digitally controlled oscillator at 1Mhz
void clockConfig( void);
66
#endif /* CLOCKCONFIG_H_ */
//pinConfig.h
#ifndef PINCONFIG_H_
#define PINCONFIG_H_
#include "msp430g2553.h"
void pinConfig( void);
/*
* sets up all the I/O pins
*
* P1.0= Debug LED, lights RED normally
* P1.1= RXD
* P1.2= TXD
* P1.3= ~CS_FINE (as GPIO)
* P1.4= ~CS_COARSE (as GPIO)
* P1.5= SCLK
* P1.6= Empty
* P1.7= DATA (MOSI)
*
* PORT2 = Empty
*/
#endif /* PINCONFIG_H_ */
67
//stateMachine.h
#ifndef STATEMACHINE_H_
#define STATEMACHINE_H_
#define IDLE 0
#define READY_DEVICE_SELECT 5 // coarse 5504 = DC1 or 7512 = DC2
#define READY_MS_CHAR1 4 //most significant, EG the 7 in 0x7004
#define READY_CHAR1_3 3
#define READY_CHAR1_2 2
#define READY_LS_CHAR1 1 //least significant, EG the 4 in 0x7004
#define READY_MS_CHAR2 14 //most significant, EG the 7 in 0x7004
#define READY_CHAR2_3 13
#define READY_CHAR2_2 12
#define READY_LS_CHAR2 11 //least significant, EG the 4 in 0x7004
#define SOH 1
#define EOT 4
#define DC1 17
#define DC2 18
#endif /* STATEMACHINE_H_ */
//uart_config.h
#ifndef UART_CONFIG_H_
#define UART_CONFIG_H_
68
#include "msp430g2553.h"
#include <stdint.h>
//sets up the UART settings on UCA0
void uartConfig( void);
#endif /* UART_CONFIG_H_ */
//ascii2dec.h
#ifndef ASCII2DEC_H_
#define ASCII2DEC_H_
#include <stdint.h>
#include <math.h>
uint8_t asciiByteToDecByte( uint8_t asciiByte);
/*takes a single byte representing a value of ascii, and converts
* to a decimal value
* only valid for the digit 0-9 and letters A-F
* EG, ASCII decimal 54 (the digit "6") will produce the output "6"
*/
#endif /* ASCII2DEC_H_ */
69
//set5504.c
#include "set5504.h"
void set5504( uint16_t dataOut)
UCB0CTL0 |= UCCKPH;
while (!( IFG2 & UCB0TXIFG));
P1OUT &= ~BIT4; //lower ~CS
__delay_cycles(10);
UCB0TXBUF = ( dataOut >> 8 ); //Most Significant byte
__delay_cycles(120);
while (!( IFG2 & UCB0TXIFG));
UCB0TXBUF = dataOut; //Least significant byte
__delay_cycles(120);
P1OUT |= BIT4; //raise ~CS
//set7512.c
#include "set7512.h"
void set7512( uint16_t dataOut)
UCB0CTL0 &= ~UCCKPH;
while (!( IFG2 & UCB0TXIFG));
P1OUT &= ~BIT3; //lower ~CS
70
__delay_cycles(10);
UCB0TXBUF = ( dataOut >> 8 ); //Most Significant byte
__delay_cycles(120);
while (!( IFG2 & UCB0TXIFG)); //originally this was only &
UCB0TXBUF = dataOut; //least significant byte
__delay_cycles(120);
P1OUT |= BIT3; //raise ~CS
//spiConfig.c
#include "spiConfig.h"
void spiConfig( void)
UCB0CTL0 |= UCMST + UCMODE_0 + UCSYNC + UCMSB;
UCB0CTL1 |= UCSSEL_2;
UCB0BR0 = 10;
UCB0BR1 = 0;
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI **
//clockConfig.c
#include "clockConfig.h"
71
void clockConfig( void)
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;
//ascii2dec.c
#include "ascii2dec.h"
uint8_t asciiByteToDecByte( uint8_t asciiByte)
if ( asciiByte <= ’9’ && asciiByte >= ’0’)
return (asciiByte - ’0’);
else if ( asciiByte <= ’F’ && asciiByte >= ’A’)
return (asciiByte - ’A’ + 10);
else
return 0;
/*
* uart_config.c
*
* Created on: Jan 14, 2014
72
* Author: Jeff
*/
//sets up the UART settings on UCA0
#include "uart_config.h"
void uartConfig( void)
/* Configure hardware UART */
UCA0CTL0 |= UCMSB; //MSB first, to be consistent with SPI
UCA0CTL1 |= UCSSEL_2; // Use SMCLK
UCA0BR0 = 104; // baud rate 9600, 1MHz clock, Data Sheet 15.3.13
UCA0BR1 = 0; // Set baud rate to 9600 with 1MHz clock
UCA0MCTL = UCBRS0; // Modulation UCBRSx = 1
UCA0CTL1 &= ~UCSWRST; // Initialize USCI state machine
IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt
73
A.6 Single Channel Fine SPI Bus Scope Trace
SPI 100kHz, falling clock edge, MSB first, command 0x7E1 (decimal 2017) about 1.6
Volts.
Hex digit sequence:
1. ”0x0” padding 0x0 because only 12 bit DAC
2. ”0x7”
3. ”0xE”
4. ”0x1”
74
A.7 Single Channel Coarse SPI Scope Trace
SPI 100kHz, rising clock edge, MSB first, Channel A command 0x1F4 (decimal 500)
about 7.3 Volts.
Hex digit sequence:
1. ”0x1” For 5504 Channel A
2. ”0x1”
3. ”0xF”
4. ”0x4”
75
A.8 Single Channel UART Scope Trace
UART, 9600 baud, 8-N-1, sending Fine DAC command 0x12C (decimal 300).
Frame sequence:
1. ASCII ”Start of Heading”
2. ASCII ”Device Control #2” (Coarse DAC is DC1)
3. ASCII ”0x1”
4. ASCII ”0x2”
5. ASCII ”0xC”
A.9 Single Channel MATLAB Code for UART
%multi_DMM_monitoring_change_5504_or_7512_over_UART.m
%send commands to AD5504 & DAC7512, record on Digital Multi Meters
%Jeffrey P Kittredge, June 11, 2014
76
%MATLAB R2013A with Instrument Toolbox
clc
defineDACparameters;
defineASCIIandUART;
defineInstrumentParameters;
%bounds of sweep (fine DAC is automatic)
C_START = 0+50; %50 from low
C_END = (4096-50); %50 from high
fileINtab = fopen(’values.txt’,’w’); %record in txt
%open DMMs as TCP/IP objects (get IP from front panel)
voltageDMM = openDMMoverTCPgivenIP( ’192.168.0.105’ ); %34461A
currentDMM = openDMMoverTCPgivenIP( ’192.168.0.106’ ); %34401A
%configure the DMM ranges
fprintf( voltageDMM, strcat(’CONF:VOLT:DC’, VOLTAGE_RANGE));
fprintf( currentDMM, strcat(’CONF:CURR:DC’, CURRENT_RANGE));
usb2uartMSP430launchpad = serial(’COM9’, ’BAUD’, 9600); %COM#?
fopen(usb2uartMSP430launchpad);
for C_Code= (CH1_OFFSET + C_START):(CH1_OFFSET + C_END )
77
sendDACvalueOverUART( C_Code, DAC5504, usb2uartMSP430launchpad );
for F_Code = F_START : (F_START + F_STEPS)
sendDACvalueOverUART(F_Code, DAC7512, usb2uartMSP430launchpad);
pause( FINE_SETTLING_TIME );
%Commands are defined in the SCPI protocol of instruments
fprintf( voltageDMM, strcat(’VOLT:DC:NPLC’, VOLTAGE_PLC));
fprintf( voltageDMM, ’READ?’);
V_Read = fscanf( voltageDMM);
fprintf( currentDMM, strcat(’CURR:DC:NPLC’, CURRENT_PLC ));
fprintf( currentDMM, ’READ?’);
Cur_Read = fscanf( currentDMM);
Write2txt(V_Read,Cur_Read,C_Code,F_Code,CH1_OFFSET,fileINtab)
end
end
fclose(usb2uartMSP430launchpad);
fclose(voltageDMM);
delete(voltageDMM);
fclose(currentDMM);
delete(currentDMM);
fclose(fileINtab);
78
%defineASCIIandUART.m
%Standard ASCII values
SOH = 1;
DC1= 17;
DC2= 18;
DAC5504 = DC1;
DAC7512 = DC2;
%defineDACparameters.m
CH1_OFFSET = 2^12; %12th bit = 1 = CH1
C_VREF = 60; %60V reference
F_VREF = 3.361; %V_DD_FLOAT measured
FINE_SETTLING_TIME = .2;
F_START = 200; %Fine DAC offset
F_STEPS = 16; %"n" in thesis
%defineInstrumentParameters.m
%for Power Line Cycles to PPM error of the 34461A see manual page 272
CURRENT_PLC = ’ 10’;
CURRENT_RANGE = ’ .001’; % units Amps
VOLTAGE_PLC = ’ 10’;
VOLTAGE_RANGE = ’ 100’; % units Volts
79
%sendDACvalueOverUART.m
function sendDACvalueOverUART ( value, device, Conn )
defineASCIIandUART;
fwrite(Conn, revBitOrder( SOH)) %Start of Heading
fwrite(Conn, revBitOrder( device )) %DC1=5504, DC2=7512
%the lead 0 in 0x0XYZ (for 7512) or 1 in 0x1EF2 (for 5504)
fwrite(Conn, revBitOrder( dec2ascii( fix(value/ (16^3))) ))
value = value - fix(value/ (16^3)) * 16^3;
%most significant byte of the DAC value 0x1EF2 it is the E
fwrite(Conn, revBitOrder( dec2ascii( fix(value/ (16^2))) ))
value = value - fix(value/ (16^2)) * 16^2;
%middle byte of the DAC value 0x1EF2 it is the F
fwrite(Conn, revBitOrder( dec2ascii( fix(value/ (16^1))) ))
value = value - fix(value/ (16^1)) * 16^1;
%Least Significant byte of the DAC value 0x1EF2 it is the 2
fwrite(Conn, revBitOrder( dec2ascii( fix(value/ (16^0))) ))
end
%Write2txt.m
function Write2txt ( V_Read, Cur_Read, C_Code, F_Code, ...
CH1_OFFSET, fileINtab )
80
V_Value = str2double(V_Read);
Cur_Value = str2double(Cur_Read);
%to determine significant digits, refer PPM error section
fprintf( fileINtab, ’%d\t%d\t%.5f\t%.9f\r\n’, ...
(C_Code - CH1_OFFSET), F_Code, V_Value, Cur_Value );
end
%revBitOrder.m
function [ reversed ] = revBitOrder( X )
%reverse order of bits in a single byte to match SPI bus,
%so that MSB is transmitted first
reversed = sum(uint8(bitset(0,1:8,bitget(uint8(X), 8:-1:1))));
end
%dec2ascii.m
function [ decAsASCIIbyte ] = dec2ascii( decimalIn )
%convert a decimal number to its corresponding ASCII code
if decimalIn >= 0 && decimalIn <= 9
decAsASCIIbyte = decimalIn + ’0’;
elseif decimalIn >= 10 && decimalIn <= 15
decAsASCIIbyte = decimalIn + ’A’ -10; % A=10
81
end
end
82
A.10 16 Coarse Schematic
Vlogic1
P1.0
2
UCA0R
XD /P1.1
3UCA0T
XD /P1.2
4
P1.3/ D
S_RaROW DATA
)5
P1.4
6
UCB0C
LK /P
1.5
7
P2.0 /D
S_CaCOL DATA
)8
P2.1 /S
HCPaCLK
)9
P2.2 /M
RaRES
ET)
10
DGND 20
SS3 /P2.6
19SS
4 /P2.7
18
TEST
17
RST
16
UCB0SIM
O /P
1.7
15UCB0SOMI /P1.6
14
SS2 /P2.5
13
SS1 /P2.4
12
P2.3 /S
TCPaLO
AD)
11
MSP540G2253
RSTTESTVCC
RXD
TXD
P1.0P1.6
MSP
430 Launch Pad
ez1
MSP
430_LA
UNCH_PAD
ROW1
ROW2
ROW3
ROW4
COL1
COL2
COL3
COL4
R1C
1R1C
2R1C
3R1C
4
R2C
1
R2C
4R2C
3R2C
2
J2VDD
VLO
GIC
J3 AGND
DGND
VLO
GIC
D6
47K
R6
DGND
DIN
Row
1_Col1
Row
1_Col2
Row
1_Col3
Row
1_Col4
SCLK
Row
2_Col1
Row
2_Col2
Row
2_Col3
Row
2_Col4
Row
3_Col1
Row
3_Col2
Row
3_Col3
Row
3_Col4
Row
4_Col1
Row
4_Col2
Row
4_Col3
Row
4_Col4
CS1
CS2
CS3
CS4
DOUT
Coarse_DACs
four_5504
DS_R
SHCP
MR
STCP
ROW1
ROW2
ROW3
ROW4
DS_C
COL1
COL2
COL3
COL4
Shift_R
egisters
Shift_R
egisters
DATA
CLK
DATA
CLK
ROW1
ROW2
ROW3
ROW4
12
34
56
78
910
1112
P25
Header 6
X2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
19 1
37 20
3838
3939
J1 37 Pin D-SUB
R4C
4R4C
3R4C
2R4C
1R3C
4R3C
3R3C
2R3C
1
Vdd
= 62-64 V DC
AGND = PE
aPotentia
l, Ea
rth)
16 Analog Outpu
ts14.7 mV/ L
SB
HV_D
AC_16
0-60 V Range
BU
APP
LIED
ELEC
TROMAGNET
ICS
COL1
COL2
COL3
COL4
PID601 PID602COD
6
PIez101
PIez102
PIez103
PIez104
PIez105
PIez106
PIez107
PIez108
PIez109
PIez1010
PIez1011
PIez1012
PIez1013
PIez1014
PIez1015
PIez1016
PIez1017
PIez1018
PIez1019
PIez1020
COez1
PIJ101
PIJ102
PIJ103
PIJ104
PIJ105
PIJ106
PIJ107
PIJ108
PIJ109
PIJ1010
PIJ1011
PIJ1012
PIJ1013
PIJ1014
PIJ1015
PIJ1016
PIJ1017
PIJ1018
PIJ1019
PIJ1020
PIJ1021
PIJ1022
PIJ1023
PIJ1024
PIJ1025
PIJ1026
PIJ1027
PIJ1028
PIJ1029
PIJ1030
PIJ1031
PIJ1032
PIJ1033
PIJ1034
PIJ1035
PIJ1036
PIJ1037
PIJ1038
PIJ1039
COJ1
PIJ201COJ
2
PIJ301COJ
3
PIP2501
PIP2502
PIP2503
PIP2504
PIP2505
PIP2506
PIP2507
PIP2508
PIP2509
PIP25010
PIP25011
PIP25012
COP25
PIR601PIR602 COR6
83
DIN
Row1_Col1
Row1_Col2
Row1_Col3
Row1_Col4
SCLK
Row2_Col1
Row2_Col2
Row2_Col3
Row2_Col4
Row3_Col1
Row3_Col2
Row3_Col3
Row3_Col4
Row4_Col1
Row4_Col2
Row4_Col3
Row4_Col4
CS1
CS2
CS3
CS4
CLR
1
SYNC
2
SCLK
3
SDI
4
SDO
5
DGND6
AGND7
LDAC
8
VOUTD
9
VOUTC
10
VOUTB
11
VOUTA
12
RSEL
13
Vdd14
ALARM
15
Vlogic16
U1
AD5504
0a1uF
C1
0a1uF
C2
10uF
C3
VDD
D1
2K2
R1
VLOGIC
VLOGIC
R1C1
R1C2
R1C3
R1C4
T4
T3
T2
T1
CLR
1
SYNC
2
SCLK
3
SDI
4
SDO
5
DGND6
AGND7
LDAC
8
VOUTD
9
VOUTC
10
VOUTB
11
VOUTA
12
RSEL
13
Vdd14
ALARM
15
Vlogic16
U2
AD5504
0a1uF
C5
0a1uF
C6
10uF
C7
VDD
D2
2K2
R2
VLOGIC
VLOGIC
R2C1
R2C2
R2C3
R2C4
T8
T7
T6
T5
SCLK
DIN
SCLK
DIN
CLR
1
SYNC
2
SCLK
3
SDI
4
SDO
5
DGND6
AGND7
LDAC
8
VOUTD
9
VOUTC
10
VOUTB
11
VOUTA
12
RSEL
13
Vdd14
ALARM
15
Vlogic16
U3
AD5504
0a1uF
C9
0a1uF
C10
10uF
C11
VDD
D3
2K2
R3
VLOGIC
VLOGIC
R3C1
R3C2
R3C3
R3C4
T12
T11
T10
T9
SCLK
DIN
CLR
1
SYNC
2
SCLK
3
SDI
4
SDO
5
DGND6
AGND7
LDAC
8
VOUTD
9
VOUTC
10
VOUTB
11
VOUTA
12
RSEL
13
Vdd14
ALARM
15
Vlogic16
U4
AD5504
0a1uF
C13
0a1uF
C14
10uF
C15
VDD
D4
2K2
R4
VLOGIC
VLOGIC
R4C1
R4C2
R4C3
R4C4
T16
T15
T14
T13
SCLK
DIN
VLOGIC
VLOGIC
VLOGIC
DOUT
DOUT
DOUT
DOUT
DOUT
VLOGIC
10uF
C4
10uF
C8
10uF
C12
10uF
C16
PIC101
PIC102
COC1
PIC201PIC202COC
2PIC301 PIC302
COC3
PIC401
PIC402COC
4
PIC501
PIC502
COC5
PIC601PIC602COC
6PIC701 PIC702
COC7
PIC801
PIC802COC
8
PIC901
PIC902
COC9
PIC1001PIC1002COC10
PIC1101 PIC1102COC11
PIC1201
PIC1202COC12
PIC1301
PIC1302
COC13
PIC1401PIC1402COC14
PIC1501 PIC1502COC15
PIC1601
PIC1602COC
16
PID101 PID102COD
1PID201 PID202
COD2
PID301 PID302COD
3PID401 PID402
COD4
PIR101PIR102 COR1
PIR201PIR202 COR2
PIR301PIR302 COR3
PIR401PIR402 COR4
PIT101COT
1 PIT201COT
2 PIT301COT
3 PIT401COT
4
PIT501COT
5 PIT601COT
6 PIT701COT
7 PIT801COT
8
PIT901COT
9 PIT1001COT10 PIT1101
COT11 PIT1201
COT12
PIT1301COT
13 PIT1401COT14 PIT1501
COT15 PIT1601
COT16
PIU101
PIU102
PIU103
PIU104
PIU105
PIU106PIU107
PIU108
PIU109
PIU1010
PIU1011
PIU1012
PIU1013
PIU1014
PIU1015
PIU1016
COU1
PIU201
PIU202
PIU203
PIU204
PIU205
PIU206PIU207
PIU208
PIU209
PIU2010
PIU2011
PIU2012
PIU2013
PIU2014
PIU2015
PIU2016
COU2
PIU301
PIU302
PIU303
PIU304
PIU305
PIU306PIU307
PIU308
PIU309
PIU3010
PIU3011
PIU3012
PIU3013
PIU3014
PIU3015
PIU3016
COU3
PIU401
PIU402
PIU403
PIU404
PIU405
PIU406PIU407
PIU408
PIU409
PIU4010
PIU4011
PIU4012
PIU4013
PIU4014
PIU4015
PIU4016
COU4
POC\S\1\
POC\S\2\
POC\S\3\
POC\S\4\
PODIN
PODOUT
POROW10COL1
POROW10COL2
POROW10COL3
POROW10COL4
POROW20COL1
POROW20COL2
POROW20COL3
POROW20COL4
POROW30COL1
POROW30COL2
POROW30COL3
POROW30COL4
POROW40COL1
POROW40COL2
POROW40COL3
POROW40COL4
POSCLK
84
DS_R
SHCP
MR
STCP
ROW1
ROW2
ROW3
ROW4
Q7S 9
Q0 15
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7 7
DS14
MR
10
OE
13
SHCP
11
STCP
12
VCC16
GND8
U574HC595PWa118
VLOGIC
DGND
DGND
SHCP STCP
DS_C
COL1
COL2
COL3
COL4
Q7S 9
Q0 15
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7 7
DS14
MR
10
OE
13
SHCP
11
STCP
12
VCC16
GND8
U674HC595PWa118
VLOGIC
DGND
DGND
MR
SHCP
STCP
MR
PIU501
PIU502
PIU503
PIU504
PIU505
PIU506
PIU507
PIU508
PIU509
PIU5010
PIU5011 PIU5012
PIU5013
PIU5014
PIU5015
PIU5016
COU5
PIU601
PIU602
PIU603
PIU604
PIU605
PIU606
PIU607
PIU608
PIU609
PIU6010
PIU6011 PIU6012
PIU6013
PIU6014
PIU6015
PIU6016
COU6
POCOL1
POCOL2
POCOL3
POCOL4PODS0CPODS0R
POM\R\
POROW1
POROW2
POROW3
POROW4
POSHCP POSTCP
85
A.11 1024 Channel Integration Overview
86
A.12 1024 Channel Control Board
87
A.13 Interferometer Results, 16 Channel Driving DM
16 Channel Coarse and Fine Board driving a deformable mirror with -100V bias to
mirror ground. One piston being deflected using a single channel of 16 Floating DAC.
The deflected piston is the small circular area.
References
(2007). High Voltage, Quad-Channel 12-bit Voltage Output DAC. Analog Devices,One Technology Way, Norwood, MA, b edition.
Agilent Technologies (2013). Truevolt Series DMM Operating and Service Guide.Agilent Technologies, Loveland, CO.
Ahmed, I. and Johns, D. A. (2005). A 50-ms/s (35 mw) to 1ks/s (15µw) powerscaleable 10-bit pipelined adc using rapid power-on opamps and minimal bias cur-rent variation. IEEE Journal of Solid-State Circuits, 40(12):2446.
Boston Micromachines Corporation (2010). Compact low-power driver for deformablemirror systems, quarterly update. S2.02-9229.
Carusone, T. C., Johns, D. A., and Martin, K. W. (2012). Analog Integrated CircuitDesign. John Wiley and Sons, Hoboken, NJ, 2nd edition.
Chen, B., Wynne, J., and Kliger, R. (2003). High speed digital isolators usingmicroscal on-chip transformers. Technical report, Analog Devices.
Cornelissen, S. A., Bierdan, P. A., and Bifano, T. G. (2006). Development of a4096 element mems continuous membrance deformable mirror for high contrastastronomical imaging. Proceedings of SPIE, 6306(630606).
Dai, S. (2012). Low power high resolution electronic driver for deformable mirrorsystems. Master’s thesis, Boston University.
Davies, J. H. (2008). MSP430 Microcontroller Basics. Newnes, Oxford, UK.
Dufort, B., Letavic, T., and Muhkerjee, S. (2002). Digitally controller high-voltageanalog switch array for medical ultrasound application in thin-layer silicon-on-insulator process. volume 0-7803-7439, page 78 and 79. IEEE Internation SOIConference.
Horenstein, M. N. (1996). Microelectronic Circuits and Devices. Prentice Hall,Upper Saddle River, NJ, 2nd edition.
Horenstein, M. N., Sumner, R., Miller, P., Bifano, T., Stewart, J., and Cornelis-sen, S. (2011). Ultra-low-power multiplexed electronic driver for high resolutiondeformable mirror systems. Proceedings of SPIE, 7930(79300M):2.
88
89
Kester, W., editor (2005). The Data Conversion Handbook. Newnes, Oxford, UK.
Macintosh, B., Graham, J., Oppenheimer, B., Pyneer, L., Sivaramakrishnan, A., andVeran, J.-P. (2006). Mems-based extreme adaptive optics for planet detection.Proceedings of SPIE, 6113(611308-1):4.
Perrault, J. A., Bifano, T. G., Levine, B. M., and Horenstein, M. N. (2002). Adap-tive optic correction using microelectromechanical deformable mirrors. OpticsEngineering, 41:561.
Sze, S. M. and Lee, M. K. (2012). Semiconductor Devices Physics and Technology.John Wiley and Sons, Hoboken, NJ, 3rd edition.
CURRICULUM VITAE
Jeffrey Kittredge
Jeffrey Kittredge was born in 1984 in Fairbanks, Alaska. He attended theUniversity of Rhode Island majoring in Industrial Engineering. His focus was De-sign for Manufacture and Assembly (DFMA). He studied abroad for one semester inKolkatta, India with internships. That experience focused on supply side sourcingand lean manufacturing. Jeffrey received the Nelson C. White award and also theInstitute of Industrial Engineers student chapter award and scholarship while at URI.He received his Bachelor of Science, Industrial Engineering in 2007.
Jeffrey worked for Procter and Gamble at the Gillette manufacturing center from2007 to 2012. He held several technical and leadership positions. His roles includedManufacturing Engineer, Electrical Engineer, and Line Leader. While working atP&G, he completed pre-requisite classes for Electrical Engineer on a part-time basisat Boston University. Jeffrey is a licensed Professional Engineer as Electrical inMassachusetts.
Jeffrey began the Master of Science program full-time in January 2013. He ismajoring in Electrical Engineering with a focus on solid state materials, devices,and circuits. His course work has also included Micro-controllers, IC manufacturing,and Radio Frequency design. He held a Research Assistant position in the AppliedElectromagnetics Lab. He was also a teaching assistant for EC583 Power Electronics.Jeffrey plans to graduate with Master of Science Electrical Engineering in December2014 and return to industry.
Jeffrey P. Kittredge
BU Electrical and Computer Engineering Department
8 Saint Mary’s Street Room 324
Boston, MA 02215