High Speed & RF Design and Layout: RFI/EMI Considerations Advanced Techniques of Higher Performance Signal Processing

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Todays Agenda

PCB Layout Overview

Schematic

Critical Component Location and Signal Routing

Power Supply Bypassing

Parasitics, Vias and Placement

Ground Plane

Layout Review

Summary

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Overview

What is high speed? The frequency above which a PCB can significantly degrade circuit

performance. 50MHz and above can be considered high speed.

PCB layout is one of the final steps in the design process and often not given the attention it deserves. High Speed circuit performance is heavily dependant on board layout.

Today we will address Practical layout guidelines that: Improve the layout process Help ensure expected circuit performance Reduce design time Lower design cost

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Schematics

Schematics

A good layout starts with good Schematics!

Basic Function of Schematics Represent actual circuit connections Generate NetList for layout.

Can it be made more effective? Can it represent functionality more clearly? Others can understand circuit

Can it show signal path? Aid layout Aid troubleshooting, debug Represent functionality

Can it be made more attractive? Can increase perceived value

More effective schematics decrease time to market

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Schematics

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A perfectly good schematic.

What are these? What is this? Too much unnecessary text Text orientation Alignment Lines cross. Is it necessary? Contradicting text No systematic approach

Components are scattered No indication of functionality Difficult to read

A good layout starts with a

good Schematic!

Schematics – Example. Is this better?

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Functionality evident at first site. Recognizable signal path. Components grouped by function. Auxiliary functions separated.

No clutter No crossed lines No excessive text All additional hidden information

is carried to layout automatically. Occupies less paper space, yet

symbol sizes are larger.

Color can add to overall appearance.

Separators can aid in recognizing functional blocks.

Is this Better?

Schematics – A circuit with more complexity

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Component Placement and Signal Routing

Component Placement and Signal Routing

Just as in real estate location is everything!

Input/output and power connections on a board are typically defined

Component placement and Signal routing require deliberate thought and planning

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Component Placement and Signal Routing Use of Plane Layers

Plane Layer Prepreg Copper Signal Trace Solder Mask Signal Current Return Current follows the path of least inductance

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Component Placement and Signal Routing Plane layer cutouts

Plane Layer Prepreg Copper Signal Trace Solder Mask Signal Current Return Current Not so good. Minimize Voids in plane layers

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Component Placement and Signal Routing Signal Routing

Placement not optimized – Minimize crossings

Connector

Digital ADC

RF

Power Conditioning

Analog Temp

Sensor

Connector

ADC Driver

Placement optimized – Idealized 14

Component Placement and Signal Routing Return Path Routing

ClockCircuitry

AnalogCircuitry R

esis

tor

DigitalCircuitry

Sensitive Analog Circuitry Disrupted by Digital Supply Noise

Not so good

ID

Voltage Drop

A better way

Sensitive Analog Circuitry Safe from Digital Supply Noise

Use GND and PWR planes to reduce return path R and L.

Use separate AGND and DGND planes to minimize digital coupling into AGND plane.

Compartmentalize functions

Group components associated with functions.

Place functions to coincide with signal path.

Route functions first with input and output along signal path.

Route connections between functions next.

Voltage Drop

More Voltage Drop

ANALOG CIRCUITS

DIGITAL CIRCUITS VD VA

+ +

ID

IA

IA + ID

VIN

GND REF

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Component Placement and Signal Routing Example

Two Inputs. Carbon copies to ensure balance.

Gain and feedback. Carbon copies to ensure symmetry.

Outputs. Carbon copies to ensure symmetry.

Level shifting tapped into signal path. Carbon copies to ensure symmetry.

Auxiliary function.

Critical Signal path as short as possible.

Critical signal paths are carbon copies to maintain balance.

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Component Placement and Signal Routing Packaging and Pinout choices

Packaging plays a large role in high-speed applications

Smaller packages Improved high frequency response Compact layout Lower package parasitics

Low Distortion Pinout (dedicated feedback) Compact layout Streamline signal flow Lower distortion

1 2 3 4

8 7 6 5

FB

INP

INN VOUT

+

-

Low Distortion 1 2 3 4

8 7 6 5

VOUT +

-

Standard

INP

INN

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PCB

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Bottom Silk Carries assembly and/or

component ID information. Informative only. Does not affect

performance. Not essential. Information contains text, lines,

shapes. Information can become useless if

not placed carefully. Min. line width = 5 mils (0.127 mm) Text height-to-line width ratio

should be > 12 to retain readability. Avoid placing text over vias, holes,

landing pads. Maintain a minimum distance

between landing pads. Quality varies between

manufacturers, ranging from sharp to smudged edges.

Bottom Mask Protects copper from environmental

effects. Minimizes solder bridging. Can

prevent bridging if designed with care. Affects PCB performance

somewhat. Not required. Essential to maintain

PCB longevity. Greatly increases PCB assembly yield. Normally green. Other popular

colors are black, blue red, white.

Bottom Copper Can be a signal layer or a plane

layer. Normally a 1.4 mils (0.04 mm) thick

copper plate. Can be thicker. Etched to form signal traces and

landing pads. Minimum trace width is 4 mils (0.1

mm). Minimum space requirement

between two objects is 4 mils (0.1 mm). Forms a capacitor with other

nearby copper plates. Has inductance.

PrePreg Separates two copper layers. Is a woven glass epoxy base

material with glue. Has relative permittivity between

about 4.7 and 2.2. Weave density determines high

frequency performance. Comes in a range of thickness. A

1080 laminate is 3.2 mils (0.08 mm) thick. Material determines maximum

soldering temperature.

Core Two copper foils already attached

to a woven glass material. Same as Prepreg but already

glued. Same characteristics as PrePreg.

Can provide “built-in” or “inter-

planar” capacitance if one or both copper foils are used as GND or PWR planes.

Another PrePreg and Core Can act as a spacer to ensure

specified finished PCB thickness If made thick, it minimizes

interplanar capacitance.

One more PrePreg Can form controlled impedance

lines when combined with copper traces above and GND plane below. Impedance depends on trace width

above and thickness and permittivity of PrePreg. Impedance accuracy depends on

the weave density.

Top Copper Usually a signal layer. Normally a 1.4 mils (0.04 mm) thick

copper plate. Can be thicker. Etched to form signal traces and

landing pads. Minimum trace width is 4 mils (0.1

mm). Minimum space requirement

between two objects is 4 mils (0.1 mm). Forms a capacitor with other

nearby copper plates. Traces have inductance.

Top Mask Same as bottom mask Protects copper from environmental

effects. Minimizes solder bridging. Can

prevent bridging if designed with care. Affects PCB performance

somewhat. Not required. Essential to maintain

PCB longevity. Greatly increases PCB assembly yield. Normally green. Other popular

colors are black, blue red, white.

Top Silk Same as bottom silk Carries assembly and/or

component ID information. Informative only. Does not affect

performance. Not essential. Information contains text, lines,

shapes. Information can become useless if

not placed carefully. Min. line width = 5 mils (0.127 mm) Text height-to-line width ratio

should be > 12 to retain readability. Avoid placing text over vias, holes,

landing pads. Maintain a minimum distance

between landing pads. Quality varies between

manufacturers, ranging from sharp to smudged edges.

PCB A typical 62 mils (1.6mm) 6 layer PCB stackup

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PCB PCB Material selection examples

Isola – FR4 types Common general purpose material. High temperature versions for leadfree solder exist High permittivity 4.7-4.2. Generates high parasitic capacitances Specified to 1 GHz Controlled impedance trace consistency OK but not great.

Rogers – PTFE types Good high frequency, high temperature material Low permittivity. 2.2 and up. Can reduce parasitic capacitances .Expensive Good impedance consistency. Specified to 10 GHz

Numerous other manufacturers. Some with performance specifications similar to above.

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PCB Component Landing pad design Landing pad size Traditionally oversized by ≈ 30% from component pad. Can fit soldering iron on it Can allow visual inspection of solder joint Can accommodate component with larger placement errors. Increases parasitic capacitance – lowers effective useful frequency Increases chances for solder bridging Requires more board space

Minimum oversizing: 0-5% from component pad. Retains mechanical strength Contact area between component and PCB

remains the same Reduces parasitic capacitance – retains

higher useful frequency Reduces required board space

Pad shape Traditionally rectangular with sharp corners Rounded corners allow tighter pad-to-trace

spacing. Reduces board size.

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This vs. This

This Or This

Signal Routing

Signal Routing

Use GND and PWR Planes Connect pads to planes using “Via-in-pad” method to minimize parasitics

Place components of a functional block as close as possible 0.5 mm component-to-component spacing is sufficient for manual placement

Minimize vias in signal traces. The less the better. Keep traces within a functional block on the same layer.

Use interplanar capacitance for bypassing

Keep plane layers as contiguous as possible Avoid unnecessary vias perforating plane layers. Avoid cutouts in plane layers

Keep traces as straight as possible Minimize bends and turns

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Examples

A perfectly good high frequency board

BUT: Excessive number of unnecessary vias Plane layer compromised with a large

cutout Unnecessarily long signal traces Landing pads are too large No internal plane layers

Same circuit with added provisions for an auxiliary function

A better alternative? More components yet smaller board size Vias are minimized Several internal plane layers “Properly” sized Landing pads

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Examples - Performance vs PCB

6 layer PCB

No bypass caps

No GND plane on top

No plane cut outs

No “stitching” vias

Performance vs. Component Location

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AD8099 Harmonic Distortion Vs. Frequency CSP and SOIC Packages

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HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

0.1–120

–100

–110

–80

–90

–60

–70

–50

1 10 50

0451

1-0-

085

SOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS

G = +5VOUT = 2V p-pVS = ±5VRL = 100Ω

FREQUENCY (MHz)

SOIC

CSP

Improvement 10dB at 1MHz 14dB at 10MHz

00:09:52

High Speed PCB Boards

Small signal BW:

New: 1.41 GHz

Existing: 976 MHz

This is nearly a 50% improvement

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Large signal (10 dm) BW:

5V suply:

New: 1.07 GHz

Existing: 948 MHz

10V supply:

New: 1.25 GHz

Existing: 891 MHz

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Pin4 - VN Pin8 - VP

VOUT2

R5

1 VOUT1

R13 IN1+

R7 2

3

IN1-

R1

R3

RS1

R11

R15

R9

7

5

6

R14 IN2+

R8 IN2-

R6

R2

R16

RS2

R12 R4

R10

C3 C2 C1

VP VN GND

C4 C5

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Crosstalk and Coupling

Capacitive Crosstalk or Coupling This results from traces running on top of each other, which forms a parasitic

capacitor Solutions run traces orthogonal, to minimize trace coupling and lower area

profile

Inductive Crosstalk Inductive crosstalk exists due to the magnetic field interaction between long

traces parallel traces There are two types of inductive crosstalk; forward and backward Backward is the noise observed nearest the driver on the victim trace Forward is the noise observed farthest from the driver on the driven line

Minimize crosstalk by Increasing trace separation (improving isolation) Using guard traces Using differential signals

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Power Supply Bypassing

Power Supply Bypassing

Bypassing is essential to high speed circuit performance

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Power Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pins

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Power Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edges

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Power Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast

rising/falling edges

Keep trace lengths short

EQUIVALENT DECOUPLED POWER LINE CIRCUIT RESONATES AT:

f = 1

2π LC √

IC +VS

C1

L1

0.1µF

1nH

f = 16MHz

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Power Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edges

Keep trace lengths short

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Power Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pins Capacitors provide low impedance AC return Provide local charge storage for fast rising/falling edges

Keep trace lengths short

Close to load return Helps minimize transient

currents in the ground plane

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Optimized Load and Bypass Capacitor Placement and Ground Return

Tantalum

Tantalum

C

C

RL

AD

80XX

RT

RG

RF

0 0

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Power Supply Bypassing Board Capacitance

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4 layer stack up Component/signal side

Ground plane

Power plane

Circuit side

d

K = relative dielectric constant A = area in cm2

d = spacing between plates in cm

A

kA 11.3d C=

Power Supply Bypassing Power Plane Capacitance

*Courtesy of Lee Ritchey *

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Power Supply Bypassing Capacitor Model

ESR (Equivalent Series Resistance) Rs

Capacitance XC = 1/2πfC

ESL (Equivalent Series Inductance) XL=2πfL

Effective Impedance

At Series resonance XL=XC Z = R

2)(2 XCXLRsZ −+=

*Courtesy of Lee Ritchey

*

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Capacitor Choices

0603 0612 *Courtesy of Lee Ritchey

*

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Multiple Parallel Capacitors

1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603

*Courtesy of Lee Ritchey

*

2 x (1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603)

1µF 330µF 0.1µF

0.01µF

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Parasitics

46

Parasitics

47

PCB parasitcs take the form of hidden

capacitors, inductors and resistors in the PCB

Parasitics degrade and distort performance

Trace/Pad Capacitance and Inductance

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113kXYC pF

Z=

K = relative dielectric constant X = Copper Length (mm) Y = Copper Width (mm)

Z = Distance to nearest Plane (mm)

Example1: SOIC landing pad X = 0.51 mm Y = 1.27mm

Z = 0.16mm: C = 0.17 pF; L=0.08 nH Z = 0.13mm: C = 0.21 pF; L=0.08 nH

20 2 0 5 2235X Y ZL X nHY Z X

. . ln . + = + + +

Example2: 3x3mm LFCSP landing pad X = 0.3 mm Y = 0.6 mm

Z = 0.16mm: C = 0.05 pF; L=0.05 nH Z = 0.13mm: C = 0.05 pF; L=0.05 nH

FR4 PCB with 1 oz Cu on top, 50Ω controlled impedance for 10 mils and 0.2mm wide traces

K= 4.7, Z=0.16mm and 0.13mm

Minimize Capacitance 1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane

Minimize Inductance 1) Use Ground plane 2) Keep length short (halving the length

reduces inductance by 44%) 3) Doubling width only reduces

inductance by 11%

Trace/Pad Capacitance and Inductance

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113kXYC pF

Z=

K = relative dielectric constant X = Copper Length (mm) Y = Copper Width (mm)

Z = Distance to nearest Plane (mm)

20 2 0 5 2235X Y ZL X nHY Z X

. . ln . + = + + +

Z

An internal or Bottom Plane Layer Forms an Interplanar capacitance with a

Power Plane layer (not shown) under it.

Spacer Large distance to eliminate interaction with

Controlled Impedance Layer above it.

Controlled Impedance Plane Layer Traces on the top signal layer, the spacer

between and this plane forms transmission lines with a characteristic impedance.

Top (Signal) layer Has signal traces and component landing

pads. Traces are transmission lines with

characteristic impedance

Top Solder mask Has effect on characteristic impedance

Via Parasitics

50

+

= 14ln2

dhhL

L = inductance of the via, nH H = length of via, cm D = diameter of via, cm H= 0.157 cm thick board, D= 0.041 cm

Via Inductance Via Capacitance

+

= 1

041.0)157.0(4ln)157.0(2L

L = 1.2nh

12

155.0DDTDC r

−=

ε

D2 = diameter of clearance hole in the ground plane, cm D1 = diameter of pad surrounding via, cm T = thickness of printed circuit board, cm = relative electric permeability of circuit board material C = parasitic via capacitance, pF T = 0.157cm, D1=0.071cm D2 = 0.127 C = 0.51pf

rε

nH

Via Placement*

0603 and 0402

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*Courtesy of Lee Ritchey

Capacitor Parasitic Model

C = Capacitor RP = insulation resistance RS = equivalent series resistance (ESR) inductance of the leads

and plates RDA = dielectric absorption CDA = dielectric absorption

52

L

r

RP

C

RDA CDA

RS

Resistor Parasitic Model

R = Resistor

CP = Parallel capacitance

L= equivalent series inductance (ESL)

53

CP

R

L

Low Frequency Op Amp Schematic

54

High Speed Op Amp Schematic

55

High Frequency Op Amp Schematic

56

Stray Capacitance

Stray Capacitance Simulation Schematic

57

Frequency Response with 1.5pF Stray Capacitance

1.5dB peaking

58

Stray Inductance

Stray Inductance

59

Parasitic Inductance Simulation Schematic

24.5mm x .25mm” =29nH

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Pulse Response With and Without Ground Plane

0.6dB overshoot

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Ground and Power Planes

Ground and Power Planes Provide A common reference point

Shielding

Lowers noise

Reduces parasitics

Heat sink

Power distribution

High value capacitance

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Ground Plane Recommendations

There is no single grounding method which is guaranteed to work 100% of the time!

At least one layer on each PC board MUST be dedicated to ground plane!

Provide as much ground plane as possible especially under traces that operate at high frequency

Use thickest metal as feasible (reduces resistance and provides improved thermal transfer)

Use multiple vias to connect same ground planes together

Do initial layout with dedicated plane for analog and digital ground planes, split only if required

Follow recommendations on mixed signal device data sheet.

Keep bypass capacitors and load returns close to reduce distortion

Provide jumper options for joining analog and digital ground planes together

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What we covered

High speed PCB design requires deliberate thought and attention to detail!

Load the schematic with as much information as possible

Where you put components on the board is just as important as to where you put entire circuits

Take the lead when laying out your board, don’t leave anything to chance

Use multiple capacitors for power supply bypassing

Parasitics must be considered and dealt with

Ground and Power planes play a key role in reducing noise and parasitics

New packaging and pinouts allow for improved performance and more compact layouts

There are many options for signal distribution, make sure you choose the right one for your application

Check the layout very carefully

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Electromagnetic compatibility (EMC)

There are two aspects of EMC: It describes the ability of electronic systems to operate without interfering with

other systems It also describes the ability of such systems to operate as intended within a

specified electromagnetic environment

Primary specifications are IEC-60050 and IEC1000

Extensive reviews in tutorial MT-095 and Analog Dialog 30-4 on Analog Devices website (www.analog.com)

Inability to meet these requirements will compromise your equipment

Inability to meet these requirements will severely limit the ability to sell the equipment to customers

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