high speed, low power fir digital filter implementation presented by, praveen dongara and rahul...
TRANSCRIPT
![Page 1: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/1.jpg)
High Speed, Low Power FIR Digital Filter Implementation
Presented by,
Praveen Dongara and Rahul Bhasin
![Page 2: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/2.jpg)
Flow Chart
• Motivation
• Brief Discussion on FIR
• Full Adder Design
• Pipelined Multiplier (8 X 8)
• Pipelined adder (16 X 16)
• Results
• Trouble shooting
![Page 3: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/3.jpg)
Motivation
• FIR - Finite Impulse Response Filter– Fundamental processing unit in DSP systems
• High frequency applications– Video imaging
• Low power applications– Wireless communications
![Page 4: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/4.jpg)
Brief Discussion on FIR Filters
1-N
0i
)( y(n) inxhi
• An N-tap FIR filter can be described by:
Direct Implementation
Tsample TM +
TA
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FIR Discussion contd.
• 2-parallel FIR Filter• Parallel Processing• Advantage
– Reduced power consumption
– Or high speed
• Disadvantage– Overhead of area
2-parallel design
![Page 6: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/6.jpg)
Why Pipelined/Parallel ?
• Pipelined to enable higher sampling rates
– Sampling frequency can be increased n-fold if we have n pipeline stages.
• Parallel for low power
![Page 7: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/7.jpg)
Why Pipelined/Parallel? Contd.
f V C L) / (f V )C (L P 2222
- V can be decreased by
- C increases by L (L=2)
- f can be decreased by L
![Page 8: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/8.jpg)
Optimizations at various levels
Improvement Achieved
Levels of design hierarchy
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Full Adder
• Dynamic Logic
• True Single Phase Clocking (TSPC)
xorcilxorbiajcy
rxobiajxorbiajSum
...
....
).(. cisicisixor
![Page 10: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/10.jpg)
Full Adder contd.
![Page 11: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/11.jpg)
Pipelined Multiplier
• Baugh-Wooley Algorithm for 8 X 8 multiplication
• 2’s complement numbers
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Pipelined Multiplier Floor Plan
• Latency of 12 cycles
• Partial product summing full adder array
• Vector merge adder
• Latch stages to skew the multiplier bits b0-b7
• Deskewing latches for the product bits
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Pipelined Multiplier Layout
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Pipelined Multiplier contd.
• Example – Input vectors 111111a1 X 0101010b
• If a=1 and b=1 we have the following output sequence.
– 1111111110101011
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Pipelined Multiplier contd.
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16 X 16 Pipelined Adder
• Latency of 8 cycles
• Triangular array of half adders
• Merging of two half adder rows – Leads to decrease in latency
• Advantage – Regularity of design– Fewer deskewing latches
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16 X 16 Pipelined Adder Layout
![Page 18: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/18.jpg)
FIR Filter Layout
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Results
![Page 20: High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin](https://reader036.vdocuments.us/reader036/viewer/2022062422/56649e6f5503460f94b6d18c/html5/thumbnails/20.jpg)
Trouble Shooting
• Convergence problems
• Elmore/Penfield analysis requires lot of disk space and time