high-speed , high-resolution , radiation-tolerant sar adc for particle physics experiments

Erik Jonsson School of Engineering & Computer Science

High-Speed, High-Resolution, Radiation-Tolerant SAR ADC

for Particle Physics Experiments

Yuan Zhou1, Hongda Xu1, Yun Chiu1

Datao Gong2, Tiankuan Liu2, Jingbo Ye2

1University of Texas at Dallas, Richardson, TX, USA2Southern Methodist University, Dallas, TX, USA

TWEPP 2014 - 2 - 2014-09-24

Outline

• Introduction

• Recent Advances in SAR ADCs

• Our Recent 12-bit SAR ADC Works

45-MS/s SAR Prototype (0.13μm, 2010)

160-MS/s SAR Prototype (40nm, 2014)

• Total Ionization Dose (TID) Results (40nm)

• Summary

TWEPP 2014 - 3 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 4 - 2014-09-24

ADC in Phase-II LAr Readout FEB

• High resolution: 12-14 bits• High speed: 40-80 MS/s• Low power, low area• Radiation tolerant

DetectorOutput Signal

Analog ShaperPreamp

Potential Phase-II Upgrade FEB (On detector)

MUX&

SerializerADC Optical Links

To Back-end

TWEPP 2014 - 5 - 2014-09-24

n1 bits n2 bits nk bits

V1

V2 Vk-1...

Vin V3

n2 bits

V1

V2

Residue amp

Stage 1

Stage 2

Stage k

2n2S/H

A/D D/A

n3 bits

Stage 3

Architecture Choice: SAR vs. Pipeline

• Pipelined ADC: High-gain residue amplifier hard to scale w/ process

• SAR ADC: low-power, low-area is a strong candidate for Phase-II

Vi

...DAC DoVDAC

VX

...

d0

dN-1

SAR

Pipeline

TWEPP 2014 - 6 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 7 - 2014-09-24

1E-16 1E-131E+10

1E+13

Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)

ISSCC & VLSI data

100mW

1W

10mW1mW100μW10μW

Efficiency = Power/(2∙BW∙3ENOB)

Per

form

ance

= 2

∙BW

∙3E

NO

B

10W

PipelineADC

SARADC

Bes

t des

ign

SAR and Pipelined ADCs (<2014)

Constant-Power Hyperbola

Power

Constant Performance

X∙Y = Power

Perf

orm

ance

Effic

ienc

y

Co

nst

ant

Eff

icie

ncy

TWEPP 2014 - 8 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 9 - 2014-09-24

12-bit, 45-MS/s, 0.13-μm CMOS ADC

Sub-binary DAC ODC

C0C1C13

SAR Logic

–VR

d0d1d13

CMPp

+VR

VX

C0

Vin

C13,d C6,dCΔ

ReadyCMPn

CLKCLK

ACLK

Vi

...DAC DoVDAC

VX

...

d0

dN-1

REDUNDANCY CAL

TWEPP 2014 - 10 - 2014-09-24

Sub-Binary DAC and Redundancy

MSB = 1

MSB = 0

FS/2Vin

No redundancy

2

Dout

1

2N

2N-1

0 FS

MSB = 1

MSB = 0

VL VHVin

Wide-code region

2

Dout

1

2N

2N-1

0 FS VL VHVin

Redundant region

1

Dout

2

2N

2N-1

0 FS

MSB = 1

MSB = 0

VM

Super-binaryBinary Sub-binary

• Built-in redundancy helps combat dynamic conversion errors (DAC mismatch, comparator, DAC settling, even SEU)

• Redundancy is also needed for digital claibration

TWEPP 2014 - 11 - 2014-09-24

• ODC is implemented in DAC w/ a small cap

Vin

ε

d+

d–

dout

+Δ, –Δ

SAR ADC

LMS

2δ

D

W = { wi }

W•D

Digital Post-Processing

Offset Double Conversion (ODC)

TWEPP 2014 - 12 - 2014-09-24

How to determine Bit Weights?

VFS0 VFS/2

2N-1

2N

Vin

D

Is the transfer curve shift-invariant?

TWEPP 2014 - 13 - 2014-09-24



VFS0 VFS/2

2N-1

2N

Vin

D

−Δ

TWEPP 2014 - 14 - 2014-09-24


VFS0 VFS/2

2N-1

2N

Vin

D


+Δ

−Δ

TWEPP 2014 - 15 - 2014-09-24

• Shift-invariant ONLY when the transfer curve is completely linear!

• Non-constant difference b/t D+ and D− reveals bit weight information

VFS

0 Vin

ε = D−−D+

δ2

(MSB-1)δ1

(MSB)δ

ε


TWEPP 2014 - 16 - 2014-09-24

12-bit, 45-MS/s, 0.13-μm CMOS ADC

Sub-binary DAC ODC

Main DAC

CM

P

DTC

SAR Logic

370μm

160μ

m

Die size: 0.06 mm2

• 12 b, 45 MS/s in FG mode

• 3-mW power (36.3 fJ/step)

• Most read JSSC article Nov. 2011

C0C1C13

SAR Logic

–VR

d0d1d13

CMPp

+VR

VX

C0

Vin

C13,d C6,dCΔ

ReadyCMPn

CLKCLK

ACLK

TWEPP 2014 - 17 - 2014-09-24

Measured ADC Spectra (BG Mode)

0 5 10-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]0 5 10

-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]

After Cal.Before Cal.

SNDR = 60.2dB

SFDR = 66.4dB

THD = -61.7dB

SNDR = 70.7dB

SFDR = 94.6dB

THD = -89.1dB

TWEPP 2014 - 18 - 2014-09-24

Comparison with 12-bit ADCs

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

Year

Fo

M (

pJ/

con

v. s

tep

)

Two-stepPipelinedSAR

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

102

Year

Act

ive

area

(m

m2 )

Two-stepPipelinedSAR

0.06 mm2

46 fJ/step @ 22.5 MS/s31 fJ/step @ 45 MS/s42%40%

Est. cal. ckt. DAC

Preamp,CB, Buffers

Digital

11%7%7% 11%

42%40%

Total Power: 3.0 mW

(@ time of publication)

TWEPP 2014 - 19 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 20 - 2014-09-24

C5

d5

C4

d4

C3

d3

C2

d2

C1

d1

SAR logic

D1

Cf

Vcm

Ready

8 bit 2nd stage

D2

ProximityDetector

Master CLK

Vin

VrefVcm

0

• (5b + 8b) synchronous two-step pipelined SAR architecture

• First-stage capacitor weights identified w/ opportunistic DAC dither

12-bit, 160-MS/s, 40-nm CMOS ADC

TWEPP 2014 - 21 - 2014-09-24

• Smaller output swing for residue amplifier• Compensated by 2nd stage SAR ADC

― Increased resolution (7 bit 8 bit)― Scaled reference voltage (Vref 0.5Vref)

Cs

A0

Vin

Cs

Vout

+Vref

-Vref

Stage1 Stage2

5bit 7bit

32x Vout

+Vref

-Vref5bit

+0.5Vref

-0.5Vref

8xVout

8bit

Cf=Cs/32 Cf=Cs/8Stage1

Stage2

1-bit redundancytolerates offset

Subranging, Swing, and Linearity

TWEPP 2014 - 22 - 2014-09-24

• Two-stage amplifier provides ~ 30-dB gain

• Gain error is lumped into bit weights and calibrated

INP

OUTP OUTN

INN

1.1V

OUTP

OUTN

200mV

Simple Residue Amplifier

TWEPP 2014 - 23 - 2014-09-24

• Reference voltage is effectively halved

• Minimal loading determined by kT/C noise

CD

AC

SA

R lo

gic

D2

Vinn

CD

AC

Vinp

CDAC

Vref Gnd

CDAC

Vref Gnd

Unit capacitor0.9 fF

Second-Stage SAR ADC

TWEPP 2014 - 24 - 2014-09-24

Die Photo

40-nm digital CMOS process(die size = 0.042 mm2)

Integrator+

DAC

MDAC1 MDAC2 MDAC3 MDAC4

Sub-ADC1

Sub-ADC2

Sub-ADC3

Sub-ADC4

Sub-ADC5

Clock&

PN Gen.

1st StageSAR 2nd Stage

SARResidue

Amp

Clk Gen.

PN Gen.

300μm

139

μm

TWEPP 2014 - 25 - 2014-09-24

Measured ADC Dynamic Performance

fs = 160MHz after cal. fin = 25MHz after cal.

10 80 30055

60

65

70

75

80

85

90

Fin [MHz]

dB

SNDRSFDR

100 160 20055

60

65

70

75

80

85

90

Fs [MHz]

dB

SNDRSFDR

fNyquist=80MHz fs=160MHz

fin [MHz] fs [MHz]

TWEPP 2014 - 26 - 2014-09-24

Analog 1.1V2.8mW(53.6%)

• Total power is ~ 5 mW at 160-MS/s operation

Analog 1.1V2.42mW48.8%

Digital 1.1V2.32mW46.8%

Reference 1V0.12mW(2.4%)

Calibration Logic0.1mW(2%)

Power Breakdown (VLSI’14 Version)

TWEPP 2014 - 27 - 2014-09-24

1E-16 1E-131E+10

1E+13

Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)

ISSCC & VLSI data

100mW

1W

10mW1mW100μW10μW

Efficiency

Per

form

ance

10W

Bes

t des

ign

12b,160MS/s5mW

ADC PE Chart Revisited

TWEPP 2014 - 28 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 29 - 2014-09-24

TID Test of 40-nm CMOS SAR ADC

• DUT under X-ray radiation when powered up w/ clock input.

• ADC performance (e.g., SNDR, SFDR, power, etc.) measured after irradiation is complete.

TWEPP 2014 - 30 - 2014-09-24

Measured SNDR and SFDR @ 80 MS/s

100

102

66

66.5

67

67.5

68

68.5

69

SN

DR

[dB

]

100

101

102

10310.67

10.75

10.84

10.92

11.00

11.09

11.17

EN

OB

[bit]

Radiation dose [krad]

fin=10MHzfin=25MHzfin=40MHz

100

102

80

82

84

86

88

90

92

SFD

R [d

B]

100

101

102

10313.00

13.33

13.66

14.00

14.33

14.66

15.00

EN

OB

[bit]


TWEPP 2014 - 31 - 2014-09-24

Measured SNDR and SFDR @ 160 MS/s

100

102

66

66.5

67

67.5

68

68.5

69

SN

DR

[dB

]

100

101

102

10310.67

10.75

10.84

10.92

11.00

11.09

11.17

EN

OB

[bit]


fin=10MHzfin=25MHzfin=40MHzfin=70MHz

100

102

80

82

84

86

88

90

92

SFD

R [d

B]

100

101

102

10313.00

13.33

13.66

14.00

14.33

14.66

15.00

EN

OB

[bit]


TWEPP 2014 - 32 - 2014-09-24

0 20 40 6066

67

68

69

SN

DR

[dB

]

After 300-krad Radiation

fin = 10MHzfin = 25MHzfin = 40MHz

0 20 40 6066

67

68

69After 500-krad Radiation


0 50 100 150 20066

67

68



0 20 40 60

75

80

85

90

Time after radiation [hour]

SFD

R [d

B]

0 20 40 60

75

80

85

90


0 50 100 150 200

75

80

85

90


Annealing (fs = 80 MS/s)

TWEPP 2014 - 33 - 2014-09-24

0 20 40 6066

67

68

69

SN

DR

[dB

]

After 300-krad Radiation

fin = 10MHzfin = 25MHzfin = 40MHzfin = 70MHz

0 20 40 6066

67

68



0 50 100 150 20066

67

68



0 20 40 60

75

80

85

90


SFD

R [d

B]

0 20 40 60

75

80

85

90


0 50 100 150 200

75

80

85

90


Annealing (fs = 160 MS/s)

TWEPP 2014 - 34 - 2014-09-24

Measured ADC Power

0 200 400 600 800 10000

1

2

3

4

5

6


Pow

er c

onsu

mpt

ion

[mW

]

Digital Power @ fs=80MHzAnalog Power @ fs=80MHzDigital Power @ fs=160MHzAnalog Power @ fs=160MHz

0 200 400 600 800 10002

3

4

5

6

7

8


Tot

al P

ower

con

sum

ptio

n [m

W]

fs=80MHzfs=160MHz

TWEPP 2014 - 35 - 2014-09-24

Outline

• Introduction






• Summary

TWEPP 2014 - 36 - 2014-09-24

Summary

Thank you for your attendance!

• High-resolution and high-speed SAR ADC is a strong candidate to meet the stringent requirements in HEP experiments

• The preliminary irradiation test (TID) results further highlight the feasibility of SAR ADC in deeply scaled CMOS processes for HEP applications

• Low power and small die size of SAR present great potentials for spatial redundancy technique to be employed in single-event upset (SEU) treatment

high-speed , high-resolution , radiation-tolerant sar adc for particle physics experiments

Documents

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