High Speed Digital Systems LabHigh Speed Digital Systems Lab

Final presentation Final presentation NOV 2011NOV 2011

Instructor: Instructor: Rolf HilgendorfRolf Hilgendorf

Students: Students: Elad Mor, Ilya ZavolskyElad Mor, Ilya Zavolsky

Integration of an A/D Integration of an A/D Converter Converter

into the sub-Nyquist Xampling into the sub-Nyquist Xampling systemsystem

Integration of an A/D Integration of an A/D Converter Converter

into the sub-Nyquist Xampling into the sub-Nyquist Xampling systemsystem

Part A Accomplishments Part A Accomplishments Design of transmission test environment.Design of transmission test environment. Performing speed tests to receive the highest frequency Performing speed tests to receive the highest frequency

for valid transmission (Loop-Back).for valid transmission (Loop-Back). Design and testing of A/D & NI adapters.Design and testing of A/D & NI adapters. Design of advanced VHDL testing environment for the Design of advanced VHDL testing environment for the

A/D adapter. A/D adapter. Execution of a single channel and a full width Execution of a single channel and a full width

transmission (A/D->Adapter->StratixIII) [without transmission (A/D->Adapter->StratixIII) [without performance of the bitslip or word alignment operations].performance of the bitslip or word alignment operations].

2A/D Integration

Part B GoalsPart B Goals To define and implement the To define and implement the

synchronization stages of 8 differential synchronization stages of 8 differential channels/48-bit data streams (DPA, CDA, channels/48-bit data streams (DPA, CDA, WAM).WAM).

To estimate the link quality using an To estimate the link quality using an automated error detection mechanism.automated error detection mechanism.

To understand the serial configuration To understand the serial configuration interface of the A/D, and to design an interface of the A/D, and to design an automatic/manual controller.automatic/manual controller.

To design of the relevant hardware To design of the relevant hardware components and to integrate them to form components and to integrate them to form the final design.the final design.

To test and analyze the sub-blocks and the To test and analyze the sub-blocks and the integrated system.integrated system.

3A/D Integration

4A/D Integration

Bitslip8:Bitslip8: Performs channel-by-channel data alignment. Performs channel-by-channel data alignment. The same hardware is used for all 8 channels, through a The same hardware is used for all 8 channels, through a mux/demux selection.mux/demux selection.The state machine will change each channel’s word The state machine will change each channel’s word boundary, until it matches the transmitted word boundary, until it matches the transmitted word (“111000”).(“111000”).

5A/D Integration

WAM: Word Alignment Mechanism; Implemented in order to solve WAM: Word Alignment Mechanism; Implemented in order to solve channel-to-channel skew.channel-to-channel skew. After switching to WAM stage (mux_select=“10”),and transmission of After switching to WAM stage (mux_select=“10”),and transmission of all-zerosall-zeros in all channels, The trigger has to be asserted. Its rising in all channels, The trigger has to be asserted. Its rising edge is clearing the main FF, and then the incoming data should edge is clearing the main FF, and then the incoming data should change to change to all-onesall-ones. Then the FF will sample the LSB of every channel . Then the FF will sample the LSB of every channel to determine which of the channels are late. Then by this result , The to determine which of the channels are late. Then by this result , The MUX array is selecting between the incoming data and a delayed MUX array is selecting between the incoming data and a delayed version of it and re-synchronizing the channels by that.version of it and re-synchronizing the channels by that.

6A/D Integration

WTPG - WAM Test Pattern GeneratorWTPG - WAM Test Pattern GeneratorWas designed according to the same principle that guided us in the Was designed according to the same principle that guided us in the design of WAM. The decision vector is given from the user. At the design of WAM. The decision vector is given from the user. At the assertion of the trigger signal, the data is changing from assertion of the trigger signal, the data is changing from all-zeros all-zeros toto all-ones, all-ones, with the effect of the delay of the channels that correlating with the effect of the delay of the channels that correlating bits were asserted in late_chan_vec[7..0].bits were asserted in late_chan_vec[7..0].

7A/D Integration

Full Width transmission Full Width transmission combined with bitslip8 and combined with bitslip8 and

WAM (stm2) and WTPG – WAM WAM (stm2) and WTPG – WAM Test Pattern GeneratorTest Pattern Generator

8A/D Integration

LFSR backgroundLFSR background

LFSR (Linear Feedback Shift Register) is a shift register LFSR (Linear Feedback Shift Register) is a shift register whose input bit is a linear function of its previous state. whose input bit is a linear function of its previous state. Applications of LFSRs include generating pseudo-Applications of LFSRs include generating pseudo-random numbers, with the big advantage of generating random numbers, with the big advantage of generating all of the possible sequences (except one).all of the possible sequences (except one).

9A/D Integration

LFSR usage and designation in stm3LFSR usage and designation in stm3The goal of the stm3 design is to perceive a Packet Error Rate The goal of the stm3 design is to perceive a Packet Error Rate (PER) estimation, over a long period of time, for the LVDS interface (PER) estimation, over a long period of time, for the LVDS interface and Stratix3 receiver module. Therefore, following the instructor's and Stratix3 receiver module. Therefore, following the instructor's advice we have used a 32-bit Fibonacci LFSR generator and advice we have used a 32-bit Fibonacci LFSR generator and checker. They were connected at receiver and transmitter ends of checker. They were connected at receiver and transmitter ends of the design. the design.

The LFSR Generator: TDG_Y_BUSThe LFSR Generator: TDG_Y_BUSThe generator is based on a 32 bit LFSR extended to 48 bits. When The generator is based on a 32 bit LFSR extended to 48 bits. When enabled and started, the circuit produces a pattern shifted by one enabled and started, the circuit produces a pattern shifted by one bit each cycle. The circuit operates at the basic clock rate at bit each cycle. The circuit operates at the basic clock rate at 60MHz. After bit 48 becomes 1 the first time, a self-holding latch is 60MHz. After bit 48 becomes 1 the first time, a self-holding latch is set to give a data_valid output signal to enable the circuitry.set to give a data_valid output signal to enable the circuitry.

Link Quality testing through LFSR error Link Quality testing through LFSR error detection design (stm3) – Receiver block detection design (stm3) – Receiver block

diagramdiagram

The LFSR Checker: TDC_Y_BUSThe LFSR Checker: TDC_Y_BUS

Test-data generated by 32 bit LFSR and extended to 48 bit is compared with Test-data generated by 32 bit LFSR and extended to 48 bit is compared with incoming data. The LFSR structure is identical to the one in TDG_Y_BUS; however, incoming data. The LFSR structure is identical to the one in TDG_Y_BUS; however, this LFSR may be loaded parallel with data. Each cycle, the complete received this LFSR may be loaded parallel with data. Each cycle, the complete received data is loaded into a compare-register. Then the outputs of the compare-reg and data is loaded into a compare-register. Then the outputs of the compare-reg and the shift-reg are tested for equality. The errors are counted externally.the shift-reg are tested for equality. The errors are counted externally.

10A/D Integration

A/D Serial Control developmentA/D Serial Control development

11A/D Integration

Looking into the A/D manual to learn the serial control interface.Looking into the A/D manual to learn the serial control interface. Experimenting with the A/D Serial configuration control interface (TCM) Experimenting with the A/D Serial configuration control interface (TCM)

to perceive different configuration and test patterns.to perceive different configuration and test patterns. In TCM we have discovered errors in the pin assignment on the ADA In TCM we have discovered errors in the pin assignment on the ADA

which had to be fixed by creating bypasses on the adapter.which had to be fixed by creating bypasses on the adapter. Characterization of the Serial control interface for the final design:Characterization of the Serial control interface for the final design:

Response timeResponse time Defining the order of action for the initialization of the A/DDefining the order of action for the initialization of the A/D Undefined output for a single cycle (X)Undefined output for a single cycle (X)

Design of the final A/D Controller:Design of the final A/D Controller:

12A/D Integration

Development of the controller according to the principles of operation that Development of the controller according to the principles of operation that were learned in TCM.were learned in TCM.

Implementation of Automatic/Manual configuration options (Implementation of Automatic/Manual configuration options (Manual- through Manual- through external control regs)external control regs)

Build of an interface between the A/D controller and the ProcWizard GUI Build of an interface between the A/D controller and the ProcWizard GUI and the Slave state machine (which is in charge of the initialization).and the Slave state machine (which is in charge of the initialization).

Testing of the final designTesting of the final design Waveform analysis:Waveform analysis:

Spikes phenomena Spikes phenomena eventually attributed to eventually attributed to reflection caused by reflection caused by bypassing the ADA.bypassing the ADA.

Disconnection of the Disconnection of the stumps has fixed the stumps has fixed the problem.problem.

13A/D Integration

Offset testing:Offset testing: Maximum measured on Maximum measured on

channel D: 15 mV (Specified channel D: 15 mV (Specified maximum offset).maximum offset).

Rest of the channel shown Rest of the channel shown approximately 2 mV offset approximately 2 mV offset which is the specified typical which is the specified typical offset.offset.

14A/D Integration

Gain test:Gain test: Peak-to-peak amplitude voltage Peak-to-peak amplitude voltage

gain was not unity as measured, gain was not unity as measured, and also seem to be frequency and also seem to be frequency dependant.dependant.

The analog inputs on the A/D card The analog inputs on the A/D card are connected to the A/D chip are connected to the A/D chip through two coils (unbalanced to through two coils (unbalanced to balanced). Looking into these balanced). Looking into these transformers data sheet revealed transformers data sheet revealed a characteristic frequency a characteristic frequency response.response.

As apparent, the final outcome of this test showed higher gain As apparent, the final outcome of this test showed higher gain levels than expected.levels than expected.

Final test – feeding the A/D with NI generated Final test – feeding the A/D with NI generated signal that was mixed in Mishali’s MWCsignal that was mixed in Mishali’s MWC

15A/D Integration

Result: The a2di design is fully Result: The a2di design is fully operationaloperational!

Future improvements Future improvements

ADA card revision: pin reassignment ADA card revision: pin reassignment according to Gidel’s IC4 layout.according to Gidel’s IC4 layout.

Trigger addition.Trigger addition. GUI control interface.GUI control interface. Gain distortion correctionGain distortion correction

Custom A/D card renovation Custom A/D card renovation Gain correction through FFT data Gain correction through FFT data

representationrepresentation Integration with the ExpanderIntegration with the Expander

16A/D Integration

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Questions / AnswersQuestions / Answers

Thank you!Thank you!

A/D Integration