high speed data acquisition architectures
DESCRIPTION
High Speed Data Acquisition Architectures. Some Basic Architectures. Non-Buffered (streaming) FIFO Buffered Multiplexed RAM “Ping Pong” Multiplexed RAM Dual Port RAM. Streaming Interface Block Diagram. Advantages / Disadvantages of Streaming. Advantages Simple, low cost - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/1.jpg)
High Speed Data Acquisition Architectures
![Page 2: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/2.jpg)
Some Basic Architectures
• Non-Buffered (streaming)
• FIFO Buffered
• Multiplexed RAM
• “Ping Pong” Multiplexed RAM
• Dual Port RAM
![Page 3: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/3.jpg)
Streaming Interface Block Diagram
ADCLPF DSP
Trigger/Clock
Interface(Bus, USB,
LAN)
RFInput
![Page 4: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/4.jpg)
Advantages / Disadvantages of Streaming
• Advantages– Simple, low cost– If only a small sample block is required,
internal DSP RAM can be used for buffering– Processing takes place in real time
• Disadvantages– Limited sampling speed
![Page 5: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/5.jpg)
FIFO Buffered Block Diagram
ADCLPF FIFO DSP
Trigger/Clock
InterfaceUSB, LAN,Bus, etc
RFInput
![Page 6: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/6.jpg)
Advantages / Disadvantages of FIFO Buffered
• Advantages– Simple
– Allows initial samples to be processed while subsequent samples are collected
– Moderate cost, low to moderate density
– Fast: 100MHz clock rates readily available
• Disadvantages– Sequential access, unneeded samples must be unloaded
– Calculations cannot be done “in place”
![Page 7: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/7.jpg)
Multiplexed RAM Block Diagram
ADCLPF
DSP
Trigger/Clock
Interface(Bus, USB,
LAN)
RFInput
Counter
SRAM
Multiplexer
Data
Address
Multiplexer
Address
Data
![Page 8: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/8.jpg)
Advantages / Disadvantages of Multiplexed RAM
• Advantages– Low cost– High density– Random access– Calculations can be done in place
• Disadvantages– More complex than FIFO, requires multiplexers, counters, etc– RAM only available after all data has been collected. Processing
of first samples cannot proceed in parallel with subsequent data collection
– RAM access time may require that ADC data be demultiplexed into multiple data streams
![Page 9: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/9.jpg)
“Ping Pong” Multiplexed RAM Block Diagram
ADC
LPF
DSP
Trigger/Clock
Interface(Bus, USB,
LAN)
RFInput
Counter
SRAM B
Multiplexer
Data
SRAM A
Multiplexer
Multiplexer Multiplexer
Data Data
Address Address
Address
![Page 10: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/10.jpg)
Advantages / Disadvantages of “Ping Pong” Multiplexed RAM
• Advantages
– High density
– Random access
– One data buffer is always available to DSP/Host, so next data set is collected while first data set is processed
– Calculations can be done in place
• Disadvantages
– Complex, requires dual RAM banks, several multiplexers, counters, etc
– RAM access time may require that ADC data be demultiplexed into multiple data streams
![Page 11: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/11.jpg)
Dual Port RAM Block Diagram
ADC
LPF
DSP
Trigger/Clock
Interface(Bus, USB,
LAN)
RFInput
Counter
Dual PortSRAM
DataB
AddB
DataA
AddA
Address
Data
![Page 12: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/12.jpg)
Advantages / Disadvantages of Dual Port RAM
• Advantages
– Simple
– Random access
– First data point is available for processing immediately
– Calculations can be done in place
• Disadvantages
– Low density, high cost
– RAM access time may require that ADC data be demultiplexed into multiple data streams
![Page 13: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/13.jpg)
Interfaces
• USB 2.0
• 10/100 LAN
• Gigabit LAN
• Parallel Bus (PXI, CPCI, VME, VXI, etc)
![Page 14: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/14.jpg)
USB 2.0
• Advantages– Simple hardware– 480 Mbps– Widely available on desktops and laptops
• Disadvantages– Can require substantial software overhead– Sharing bus with over devices limits bandwidth– Must be in close proximity to computer
![Page 15: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/15.jpg)
10/100 LAN
• Advantages– Widely available on desktops and laptops– Operates over long distances
• Disadvantages– Typically requires coprocessor– Can require substantial software overhead– Sharing bus with other devices limits
bandwidth
![Page 16: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/16.jpg)
Gigabit LAN
• Advantages– 1000 Mbps
– Operates over long distances
• Disadvantages– Typically requires embedded SBC with operating
system support
– Can require substantial software overhead
– Sharing bus with other devices limits bandwidth
![Page 17: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/17.jpg)
Parallel Bus
• Advantages– Fastest possible data transfer
– DSP may not be required for some applications
– Can use off the shelf SBC as controller/host processor
– Host processor/OS could support other interfaces (e.g. Gigabit LAN)
• Disadvantages– Expensive (requires SBC)
– Size, power consumption
![Page 18: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/18.jpg)
ADC14100-USB Block Diagram
Decimator256K x 18
FIFO
ADSP 21262Floating Point
DSP
100 MHz80 MHz
ExtClock
USB 2.0RFInput
ADC14 Bits
100MSPS
RS232
![Page 19: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/19.jpg)
ADC14100-USB Front Panel
![Page 20: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/20.jpg)
ADC14100-USB Rear Panel
![Page 21: High Speed Data Acquisition Architectures](https://reader036.vdocuments.us/reader036/viewer/2022062518/56814119550346895dace252/html5/thumbnails/21.jpg)
ADC14100-USB Features
• 14 Bit 100 MSPS ADC
• Analog Devices ADSP-21262 DSP
• 256K x 18, 100 MHz FIFO memory
• USB 2.0 Interface
• RS232 Interface
• Hardware decimator for lower sample rates at full analog bandwidth
• 3 software selectable clock sources:
– Internal 100 MHz oscillator
– Internal 80 MHz oscillator
– External clock