high-performance schottky barrier mosfet
DESCRIPTION
High-Performance Schottky Barrier MOSFET. Horng-Chih Lin Department of Electronics Engineering & Institute of Electronics National Chiao Tung University September 19, 2005. Outline. Background Low B Source Field-induced Drain (FID) Structure Non-Si Channel Materials - PowerPoint PPT PresentationTRANSCRIPT
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High-Performance Schottky Barrier MOSFET
Horng-Chih LinDepartment of Electronics Engineering &
Institute of Electronics National Chiao Tung University
September 19, 2005
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Outline• Background
• Low B Source
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
3
SB MOSFET
Source Drain
Silicide
Substrate
Gate • Source/drain made of metallic material (e.g., silicide) in lieu of heavily doped semiconductor.
• First reported in 1968 by Lepselter and Sze ( Proc. of IEEE, p.1400 (1968)).
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• Easy processing
• Elimination of S/D implant
• Ultra-shallow and abrupt junction
• Low S/D sheet resistance
• Low process temperature
Advantages of SB MOSFET
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ITRS 2003
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ITRS 2003
Device Intrinsic SpeedIon:Ioff Ratio
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Off-state (VG < VT) On-state (VG > VT)
Potential DistributionIEEE ED, V-47, p.1241 (2000)
Source Source
Channel
Channel
Drain Drain
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Major Issues (I)
bn
On current, limited by
(i) Barrier height- PtSi (Bp = 0.24 eV) for pMOS
- ErSi2 (Bn = 0.27 eV) for nMOS
- Near-zero or negative Bp desired
(ii) Barrier width- Modulated by gate bias - Gate overlaps with source necessary
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Major Issues (II)
bp
Off current
(i) Major Conduction mechanism:Field emission of holes (electrons) for nMOS (pMOS) at drain junction
(ii) StructureGate/drain overlap structure aggravates the leakage
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Performance of Sub- 40 nm pMOSAppl. Phys. Lett., V-74, p.1174 (1999)
n+ poly: L = 27 nm; p+ poly: L = 40 nm
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25 nm p-Channel SOI SB MOSFET Jpn. J. Appl. Phys. (Part I), V-39, p.4757 (2000)
• PtSi source/drain and metal gate
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Methods to Improve Performance
• Development of low B S/D materials- Zero or even negative barrier height highly desired- Use of SOI with ultra-thin body to reduce the leakage
• Implementation of FID structure
• Use of non-Si channel materials- Exs. CNT and Ge (SiGe) channel
• Metal/channel interface modulation - Insertion of an ultra-thin dielectric layer- Dopant segregation
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Outline• Background
• Low B Source
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
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Barrier Height
(eV)
PtSi
(1)
PtSi
(2)
ErSi
(1)
TbSi
(2)
DySi
(2)
YbSi
(2)
ErSi
(2)
PMOS (hole) 0.24 0.28
NMOS (electron) 0.28 0.37 0.38 0.37 0.27
(1) IEDM Tech. Dig. p.57 (2000)(2) EDL., Vol.25, p.525 (2004)
Barrier Height at Silicide/Si Junctions
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Characteristics of Schottky Diodes EDL., Vol.25, p.525 (2004)
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NMOS with YbSi2-x S/D
IEEE EDL., Vol.25, p.525 (2004)
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VD
Buried oxide
VD
SB MOSFETs Built on SOI with Ultra-thin body
Significant portion of the leakage blocked by the buried oxide
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SB MOSFET on Ultra-thin Body SOI IEDM ‘2000, p.57
SOI thickness ~ 10 nm
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Outline
• Background
• Low B S/D
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
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Substrate
Sub-gate
Substrate
Sub-gate
SB MOSFETs with Field-induced Drain (FID)
NSA structure SA structure
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Substrate
Sub-gate
- Barrier width modulated by sub-gate bias
- Source NOT necessary to overlap with the main-gate
- Ambipolar operation capability
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Fabrication Flow
- Amorphous Si deposition (LPCVD, 550 oC, 50 nm)- Re-crystallization (in N2, 600 oC, 24 hr)- Gate oxide (LPCVD, 20 nm)- Gate formation (n+ poly-Si, 200 nm )- CVD oxide (LPCVD, 200 nm)- Oxide patterning - Co salicide treatment
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- Passivation
(PECVD oxide, 550 nm)
- Contact hole patterning
- Metal pad and sub-gate
formation
Fabrication Flow (Cont.)
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Sub-gate
Reduction of Off-state Leakage by FID
Source
Drain
VG << Vth
• The FID expels the high-
field region away from the
drain junction.
• Field-emission leakage encountered in conventional SB devices thus suppressed.
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Sub-gate
Modulation of ON Current by FID
Drain
Source
VG > Vth
Dashed line has higher sub-gate bias
• Tunneling barrier width
modulated by the sub-gate
bias.
• Depending on the polarity of applied bias, the device could be set for either n- or p-mode operation.
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Vg,main (V)
-10 -5 0 5 10
I D (
A)
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Conventional SB TFTConventional SB TFT FID SB TFT FID SB TFT
Ambipolar Poly-Si TFTs with FIDH. C. Lin et al., IEDM’2000, p.857
VG (V)-10 -5 0 5 10
I D (
A)
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Vsub=-50VVD = -5V
VG (V)
- On/off current ratio < 10On/off current ratio < 1033 -- On/off current ratio ~ 10On/off current ratio ~ 1066
VD = -5VVsub=50VVD = 5V
VD = 5V
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New Modified Characterization SchemeH. C. Lin et al., IEDM’2004, p.781
-4 -3 -2 -1 010-12
10-10
10-9
10-8
10-11
ID(A
)
VG (V)
@RT
Step 1: Determination of VFB
Step 3: Extract of DOS
Step 2: s as a function of VG
The new method
Incremental method
FEC theory
Only two simple I-V measurements at room temperature from a single device are all that needed for full band-gap DOS extraction
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E-EF(eV)-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
DO
S(e
V-1c
m-3)
1016
1017
1018
1019
1020
1021
As-depositedSPC
ELA
Effect of Channel CrystallizationSPC Channel, L/W = 1/20 m/m
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TEM Photos
Grain size~ 20 nm
Grain size ~ 300 nmGrain size ~ 50 nm
As-deposited poly-Si
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SEM
Fin width
Channel length
VS
VG
VG, sub
Al sub-gate
n+ poly-Si gate
CoSi2source
CoSi2drain
VD
The top view of device structure
SB FinFET
31Gate Voltage (V)
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Dra
in C
urr
en
t (A
)
10-15
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
SS= 60.6 mV/decSS=60.8 mV/dec.
VG,sub= 7.5 V
VD = 0.1 V VD =
-0.1 V,
L = 470 nm, Fin width = 50 nm
VD = 1.5 V
VD = -1.5 V
Ambipolar Operation with Ideal Subthreshold Swing (IEEE NANO’02)
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Drain Voltage (V)-2-10
Dra
in C
urr
ent
(A/ m
)
0
20x10-6
40x10-6
60x10-6
80x10-6
VG - Vth = 0 ~ -1.2 Vin steps of - 0.2 V
Drain Voltage (V)-2-10
Dra
in C
urr
ent
(A/
m)
0
50x10-6
100x10-6
150x10-6
Vsub=-5V Vsub=-6V
VG - Vth = 0 ~ -1.2 Vin steps of - 0.2 V
Impact of S/D MaterialIEEE EDL., Vol.24, p.102 (2003)
L = 110 nm
CoSi S/D PtSi S/D
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CNT Devices with FIDIEDM’2004 p. 687
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CNT Devices with FIDIEDM’2004 p. 687
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Outline
• Background
• Low B Source
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
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SB MOSFET with SiGe ChannelIEEE EDL Vol. 23, p. 460 (2002)
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SB MOSFET with SiGe ChannelIEEE EDL Vol. 23, p. 460 (2002)
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Ge pMOSFETs With NiGe S/DIEEE EDL Vol. 26, p. 81 (2005)
• NiGe S/D
• Barrier height ~ 0.16 eV
• Drive current 5 times higher than Si PMOS with PtSi S/D
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SB PMOS on GOI with GePt S/DIEEE EDL Vol. 26, Vol. 26, p. 102 (2005)
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Bp of –0.05 eV was reported for CNT FET
CNT FET with Negative Barrier HeightNature, Vol.424, p.654 (2003)
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• Background
• Low B Source
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
Outline
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An ultrathin insulator at the interface trades a reduction in the thermionic for a tunneling barrier. The key is to reduce the thermionic barrier whilelimiting the tunneling barrier.
The Si in the direct vicinity of the metal acquires a dipole moment due to the influence of metal-induced gap states, generating a barrier to electron injection.
Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer
IEEE Trans. Nanotechnology, Vol.3 p.92 (2003)
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Resistance drops sharply as gap states are blocked and the Fermi level is liberated.
Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer
IEEE Trans. Nanotechnology, Vol.3 p.92 (2003)
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Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer
IEEE Trans. Nanotechnology, Vol.3 p.92 (2003)
Dependences of drain current and conductance on drain bias
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Schottky Barrier Height Engineering with Dopant
Segregation (DS) Technique(VLSI’04, p.168)
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Schottky Barrier Height Engineering with Dopant
Segregation (DS) Technique(VLSI’04, p.168)
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NiSi
BF2+
SDE
Si FinFET with Modified-Schottky Barrier (MSB)
IEEE Electron Device Lett., Vol. 25, p.430 (2004)
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Source Drain
Gate
A A’
Lg=25 nm
Ni silicide
Device Layout TEM
Si FinFET with Modified-Schottky Barrier (MSB)
IEEE Electron Device Lett., Vol. 25, p.430 (2004)
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Si FinFET with Modified-Schottky Barrier (MSB)
IEEE Electron Device Lett., Vol. 25, p.430 (2004)
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Micro-structure of S/D in MSB FinFETsIEEE Electron Device Lett., Vol. 26, p.394 (2005)
Fin width = 40 nm Fin width = 200 nm
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Outline
• Background
• Low B Source
• Field-induced Drain (FID) Structure
• Non-Si Channel Materials
• Interface Modulation Techniques•
• Summary
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Summary • SB MOS devices may find applications in TFT and nano-CMOS manufacturing.
• A novel SB MOSFET with FID demonstrated.
• Based on the structure and unique ambipolar feature, a greatly simplified FEC characterization procedure developed for extracting the DOS in TFT.
• Nano-scale SOI device with excellent ambipolar subthrehsold swing and high on/off current ratio achieved.
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• Near-zero or even negative barrier height at source junction highly desired for
practical SB MOSFET application.
• UTB SOI essential for leakage reduction
• Interface modulation processes are potential for future nano-scale device manufacturing.
Summary (Cont.)