high performance barium strontium titanate varactor technology
TRANSCRIPT
UNIVERSITY of CALIFORNIA
Santa Barbara
High Performance Barium Strontium Titanate Varactor
Technology for Low Cost Circuit Applications
A dissertation submitted in partial satisfaction
of the requirements for the degree of
Doctor of Philosophy
in
Electrical and Computer Engineering
by
Baki Acikel
ii
The dissertation of Baki Acikel is approved by
_______________________________________________________
Dr. Jonathan J. Lynch
_______________________________________________________
Professor James S. Speck
_______________________________________________________
Professor Umesh K. Mishra
_______________________________________________________
Professor Robert A. York, Chairperson
August 2002
iii
High Performance Barium Strontium Titanate Varactor Technology for Low Cost
Circuit Applications
Copyright © 2002
by
Baki Acikel
iv
ACKNOWLEDGEMENTS
I would like to foremost thank Professor Robert York for his continuous
guidance and support during my studies. He has been very involved with my research
and I benefited tremendously from his depth of knowledge in many diverse fields. I
am also thankful to Professor James Speck, Professor Umesh Mishra and Dr.
Jonathan Lynch for supervising this thesis and for their advice.
I also like to thank Troy Taylor for his vital role in providing me with the BST
material grown at UCSB. I am also grateful to many people for their direct
contribution in the project including Amit Nagra, Peter Hansen, Justin Serraiocco,
Hongtao Xu, Bruce Liu, Nadia Pervez, and David Laney (HRL). The research was
funded under DARPA-FAME program.
I had the privilege to know many people during my stay at UCSB. Professor
Nadir Dagli played a major role in my acceptance to UCSB. The students in Mishra-
York group helped make the work environment enjoyable. I would like to thank
Paolo, Pengcheng, Vicki, and Chris for their help. I have to thank Bill Mitchell, Jack
Ko, Ryan Naone for their contribution to my earlier research efforts. Steve Sakamoto,
Volkan Kaman, Dino Mensa, David Choi, Rahul Magoon are only some of many dear
friends I met here. I also like to thank my personal friends who provided their support
whenever I needed. Sacid, Erhan and Kamil have been the closest friends since I
arrived in Santa Barbara.
v
Finally, I would like to acknowledge my mother, Resmiye Acikel, for her
love and support throughout my life. She made it possible for us, my brothers and
sister, after my father passed away when we were kids. It was most difficult to be
away from my family but I hope this will make them proud. And, my beloved wife,
Yesim Tokat Acikel, was the source for endless support and love during our graduate
studies. Without her, this work would not be possible.
vi
VITA
July 16, 1973 Born in Antakya, Turkey
June 1995 Bachelor of Science,
Electrical and Electronics Engineering,
Middle East Technical University, Ankara, Turkey
September 1995 Graduate Student Researcher,
Department of Electrical and Computer Engineering,
University of California, Santa Barbara
September 1997 Teaching Assistant,
Department of Electrical and Computer Engineering,
University of California, Santa Barbara
September 1997 Master of Science,
Electrical Engineering,
University of California, Santa Barbara
August 2002 Doctor of Philosophy,
Electrical Engineering,
University of California, Santa Barbara
vii
PUBLICATIONS
1. B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, R. A. York, “A new high
performance phase shifter using BaxSr1-xTiO3 thin films,” IEEE Microwave and
Wireless Components Letters, vol.12, p.237-9, July 2002
2. T. R. Taylor, P. J. Hansen, B. Acikel, N. Pervez, R. A. York, S.K. Streiffer, J. S.
Speck, “The impact of thermal strain on the dielectric constant of sputtered
barium strontium titanate thin films,” Applied Physics Letters, vol.80, p.1978-80,
March 2002.
3. B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, R. A. York, “A new X-Band
1800 high performance phase shifter using BaSrTiO3 thin films,” in 2002 IEEE
MTT-S International Microwave Symposium Digest, vol.3, p.1467-9, Seattle,
WA, June 2002.
4. J. Serraiocco, B. Acikel, H. Xu, T. R. Taylor, P. J. Hansen, J. S. Speck, R. A.
York, “Tunable integrated passive circuits using BST thin films,” presented at
IFFF 2002, International Joint Conference on the Applications of Ferroelectrics,
Kyoto, Japan, May 2002.
5. R. A. York, B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, C. Elsass, “High
Frequency Varactors using Thin Film BST: Device Applications and Materials
Challenges,” invited paper, presented at Materials Research Society Spring
Meeting, San Francisco, April 2002.
viii
6. B. Acikel, Y. Liu, A. S. Nagra, T. R. Taylor, P. J. Hansen, J. S. Speck, R. A.
York, “Phase shifters using BaSrTiO3 thin films on sapphire and glass substrate,”
in 2001 IEEE MTT-S International Microwave Symposium Digest, vol.2, p.1191-
4, Phoenix, AZ, June 2001.
7. B. Acikel, P. J. Hansen, T. R. Taylor, A. S. Nagra, J. S. Speck, R. A. York, “
Tunable strontium titanate thin films for microwave devices” Integrated
Ferroelectrics, Thirteenth International Symposium on Integrated Ferroelectrics,
vol.39, p.313-20, Colorado Springs, CO, March 2001.
8. Y. Liu, B. Acikel, P. J. Hansen, T. R. Taylor, A. S. Nagra, J. S. Speck, R. A.
York, “Distributed phase shifters using BaSrTiO3 thin films on sapphire and
glass substrates,” Integrated Ferroelectrics, Thirteenth International Symposium
on Integrated Ferroelectrics, vol.39, p.313-20, Colorado Springs, CO, March
2001.
ix
ABSTRACT
High Performance Barium Strontium Titanate Varactor Technology for
Low Cost Circuit Applications
by
Baki Acikel
A monolithic Barium Strontium Titanate (BST) thin film varactor technology
has been developed for low-cost circuit applications. BST thin films have several
properties that make them attractive for high frequency applications including field
dependent permittivity, fast polarization response, and high breakdown field.
Challenges for the integration of BST films into monolithic process fabrication such
as high temperature growth conditions and need for robust electrode stacks on low
loss inexpensive microwave substrates etc. have been overcome. Different device
topologies have been investigated to implement parallel plate BST capacitors for low
voltage applications.
The development of low-loss phase shifters for phased arrays has been the
focal point of the research work on BST technology at UCSB. BST varactor loaded
distributed phase shifters on glass and sapphire substrates have been demonstrated.
An 180˚ phase shifter circuit has provided 0-250º phase shift with an insertion loss of
only 3.1 dB at 10 GHz. A figure of merit (FOM) 93º/dB at 6.3 GHz has been
x
demonstrated. This is the best result reported for BST film phase shifters at room
temperature.
Encouraged by the results of the distributed analog phase shifters, compact
size lumped element phase shifters have been fabricated. A C-Band 90˚ phase shifter
has resulted in 63˚ phase shift with an insertion loss of 1.1 dB, with FOM comparable
to the state of the GaAs semiconductor MMIC phase shifters. Compact size BST
tunable integrated passive circuits such as tunable matching networks have been
demonstrated for low voltage wireless applications.
xi
Contents
1.Thesis Outline .................................................................................. 1
2.BST Thin Film Varactors for Tunable Microwave Circuit
Applications ........................................................................................ 4
2.1 Motivations for BST Thin Films..............................................................4
2.2 BST Thin Films for Phase Shifter Applications.....................................11
2.3 Fundamentals of BST Material Properties: Bulk vs. Thin Films...........12
3.BST Device Technology Issues..................................................... 27
3.1 General Device Technology...................................................................27
3.2 BST Parallel Plate Capacitors ................................................................31
3.3 High Frequency BST Varactor Design -Early Device ...........................37
3.4 New BST Varactor Layout for Optimized Performance........................48
4. BST Varactors: Characterization & Modeling ............................. 56
4.1 Device Characterization .........................................................................56
4.2. Low Frequency Device Modeling.........................................................62
4.3 Characterization of BST Varactors in Microwave Regime ...................69
4.4 Device Modeling for New Schottky type BST Varactors......................75
5. Low Loss Analog Phase Shifters using BST Technology............ 86
5.1 BST Thin Film Phase Shifters................................................................87
xii
5.2 BST Varactor Loaded Phase Shifter: Overview ....................................88
5.3 Design of X-Band BST Varactor Loaded Phase Shifter ........................91
5.4 Circuit Fabrication..................................................................................92
5.5 DC and RF Characterization ..................................................................96
5.6 Analysis and Modeling of results...........................................................99
5.7 Non-Uniform Loading for Improved Return Loss...............................105
6. BST Varactors for Tunable Passive Integrated Circuits............. 113
6.1 Highly Integrated Passive Element Circuits.........................................113
6.2. Passive Circuit Components: Overview..............................................115
6.3 Compact size lumped element synthetic phase shifters .......................120
6.4 Tunable Impedance Matching Networks .............................................126
7. Summary and Future Work ........................................................ 135
7.1 Integrated BST Varactor Technology ..................................................135
7.2 BST Varactors for Loaded Transmission Line Phase Shifters.............136
7.3 Tunable Passive Integrated Circuits and Lumped Element BST
Phase Shifters......................................................................................137
Appendix A BST Finger Capacitor Fabrication............................. 140
Appendix B Tunable Matching Network Process .......................... 145
Appendix C Fabrication Details for Passive Integrated Circuits ... 148
Appendix DTwo BST Capacitors in Series: Early Device............. 151
xiii
List of Figures
Figure 2.1: A typical capacitance vs. voltage characteristics of BST
varactors. ...................................................................................5
Figure 2.2: BST bypass capacitors to reduce chip size and improve
device performance. ..................................................................7
Table 2.1: The comparison of currently available varactor technologies. .....8
Figure 2.3: The loss tangent and the capacitance density as a function of
frequency ................................................................................11
Figure 2.4a-b: Comparison of the permittivities of bulk and thin film
BST as a function of temperature. Figure 2.4a shows much
higher permittivities for bulk materials. In Figure 2.4 b, the
sharp peak in the permittivity is suppressed for thin film. ......13
Figure 2.5: The structure of (Ba,Sr)TiO3. Ba and Sr occupy the center
position and with Ti at the cube corners, surrounded by
oxygen octahedra.....................................................................14
Figure 2.6 a-b: The capacitance density and polarization curve as a
function of bias. The polarization curve is obtained by
integrating the measured C-V small signal data. The LGD
model fits the data very well. ..................................................17
xiv
Figure 2.7: The field dependence of permittivity as a function of film
thickness ..................................................................................18
Figure 2.8: (a) Dielectric constant and (b) inverse capacitance density as
a function of thickness.............................................................19
Figure 3.1a-b: BST interdigital and parallel plate varactor device
schematics. ..............................................................................30
Figure 3.2: Typical tunability curves for BST interdigital and parallel
plate capacitors fabricated at UCSB........................................30
Figure 3.3: Schematic of stacked BST capacitor and relevant device
integration issues. ....................................................................32
Figure 3.4: Permittivity and quality factor for Ba0.49Sr0.51TiO3 thin
films grown on sapphire and silicon substrates at UCSB. ......35
Figure 3.5: The tunability is shown for BST films grown at UCSB with
two different compositions......................................................36
Figure 3.6 The BST parallel plate capacitor areas. as a function of
thickness ..................................................................................38
Figure 3.7a-b: Layout schematic for two capacitors in series
configuration. The base electrode is shared and tuning
voltage is applied between two top contacts. ..........................40
Figure 3.8: The device Q factor for different physical device layout. .........41
xv
Figure 3.9a-c: The affect of the processing steps on film tunability and
loss tangent. .............................................................................43
Figure 3.10: The process details for the BST varactors with two
capacitors in series configuration............................................45
Figure 3.11a-b: Device schematic and completed picture of initial
parallel plate capacitors that had two capacitors in series
configuration. ..........................................................................47
Figure 3.12: Typical device measurement for BST varactors with two
capacitors in series configuration............................................47
Figure 3.13a-b The device schematics for the new single device BST
varactors suitable.....................................................................49
Figure 3.14: The fabrication of Schottky-like BST 'finger' varactors ..........51
Figure 3.15: Completed device picture of BST capacitor that uses
prepatterned bottom electrode. Thick metal contacts to the
bottom electrode allow reduced resistance in the base. ..........52
Figure 4.1: The BST varactors used for the capacitance measurements as
a function of frequency. The BST varactor is formed under
the signal port of the coplanar waveguide...............................58
Figure 4.2: The capacitance and the quality factor characteristics of a
typical BST varactor................................................................58
xvi
Figure 4.3: Q factors for two samples with different bottom electrode
thicknesses that had the same BST film growth. The quality
factor decreases sharply for the sample with the thinner
bottom electrode......................................................................59
Figure 4.4: The extracted quality factor for the BST film and the device. ..62
Figure 4.5: The equivalent circuit loss model for the BST varactors. .........63
Figure 4.6: The simplified equivalent circuits that dominates the
behavior in the corresponding frequency range. .....................64
Figure 4.7a: The distributed circuit model for the BST varactors with
CPW electrodes. ......................................................................65
Figure 4.7b: The simplified equivalent version of the distributed circuit. ...65
Figure 4.8: The series resistance due to base electrode in the BST
varactor....................................................................................67
Figure 4.9: The comparison of the measurement with the BST model........68
Figure 4.10: Equivalent circuit for microwave frequency measurements
with pad parasitics...................................................................71
Figure 4.11: Open and short-circuited pad measurements yield the
relevant parasitics....................................................................73
Figure 4.12a-c: The comparison of the high frequency measurements
and the models.........................................................................74
xvii
Figure 4.13: Device measurements for typical BST varactors with two
capacitors in series configuration............................................75
Figure 4.14: The capacitance and quality factor measurements for BST
finger devices as a function of frequency................................77
Figure 4.15: The quality factor of the devices with different finger
widths and lengths. ..................................................................77
Figure 4.16: The critical dimensions of new device layout. The
minimum feature is set by lithographic restrictions. ...............78
Figure 4.17: The schematic showing the different series resistance
components for BST varactor due to electrodes .....................80
Figure 4.18: The dependence of the series resistance to the device
length. The shorter device length reduces the series
resistance term.........................................................................81
Figure 4.19: The cutoff frequency of the modeled BST capacitors. ............82
Figure 4.20a-d: Comparison of the measured and the simulated results
for BST varactors. ...................................................................83
Figure 5.1: Total insertion loss as a function of loading factor for X-
Band phase shifter. ..................................................................91
xviii
Figure 5.2: The process flow diagram for the fabrication of the BST
phase shifter circuits................................................................94
Figure 5.3: The picture of the completed phase shifter. The side and top
views of the BST varactor loading sections are also shown. ..95
Figure 5.4a: Measured insertion loss of the X-Band phase shifter at
different bias voltages. The maximum insertion loss occurs
at 0 V bias where Bragg frequency is minimum.....................97
Figure 5.4b: Measured differential phase shift versus frequency at
different bias voltage. The phase shift linearly increases
with frequency indicating a true delay line characteristics. ....98
Figure 5.4c: Return loss measurements for X-Band phase shifter. ..............98
Figure 5.5: The characterization of the discrete test BST varactors. ...........99
Fig 5.6a-b: Measured vs. simulated results for the differential phase and
the insertion loss....................................................................102
Figure 5.6 c: The return loss measurements are compared with the
simulation results...................................................................103
Figure 5.7: The calculated total circuit losses as a function of frequency. 104
Figure 5.8a-b: The return and insertion loss measurements for the non-
uniformly loaded BST phase shifter designed at HRL. ........106
Figure 5.8c:: The differential phase shift as a function of frequency
obtained by HRL design........................................................107
xix
Figure 5.9a-b: ADS simulations of the return and insertion losses for the
HRL phase shifter..................................................................108
Figure 5.10: The unit cell used in the ADS phase shifter simulations. ......109
Figure 5.11: The BST phase shifter circuit used in HP ADS simulations. 110
Figure 6.1: The lumped element equivalent model for multi-turn
inductor. The conductor loss is indicated by series resistor
whereas capacitors indicate the parasitic coupling. ..............116
Figure 6.2: The cross section of a tunable passive integrated circuit
using BST varactors. .............................................................120
Figure 6.3: The equivalent circuit for quarter wavelength transmission
line used in the BST lumped phase shifter. The equivalent
capacitor was implemented using BST varactors. ................122
Figure 6.4a: The schematic of the lumped element circuit. .......................123
Figure 6.4b-c: The simulations for the phase shift and insertion loss of
the lumped element phase shifter. .........................................123
Figure 6.5: A photograph of the fabricated BST lumped element circuit..124
Figure 6.6a-c: The measurement results for the BST lumped element
phase shifter The differential phase, the insertion and return
loss are shown. ......................................................................125
Figure 6.7: The schematic of the BST tunable matching network used in
the power amplifier circuits...................................................128
xx
Figure 6.8: The fabrication process for the tunable impedance matching
network..................................................................................130
Figure 6.9: The picture of the tunable matching network. The DC
voltage is applied to the BST varactors using on-chip
resistors..................................................................................131
Figure 6.10a C-V measurement for the varactors used in the tunable
matching network..................................................................132
Figure 6.10b The capacitance vs. frequency measurement at different
bias voltages. .........................................................................132
1
Chapter 1
Thesis Outline
This thesis presents a comprehensive research effort for development of
alternative low cost varactor technology using Barium Strontium Titanate (BST)
thin films for tunable RF and microwave circuits. The work focuses on the BST
device fabrication technology as well as the application of this technology to new
circuits including phase shifters, highly integrated passive integrated circuits and
tunable matching networks. The phase shifters, which are crucial components for
modern phased array systems, will immediately benefit from high performance low
cost BST technology and this will enable widespread application. An analog phase
shifter based on the BST varactor loaded transmission line topology demonstrates
the potential of the BST technology. The phase shifter circuit performance
provided the motivation for further studies in the tunable passive integrated and
lumped element circuits discussed in Chapter 6.
A brief outline of the contents of each chapter is as follows.
The motivations for the development of BST thin film varactor technology
are presented in Chapter 2 along with a discussion of the advantages/disadvantages
of available varactor technologies. A brief survey of potential applications that
2
benefit from the BST thin film technology is presented. The fundamental BST thin
film material properties are reviewed in this chapter.
Material and device issues of BST varactors are discussed in Chapter 3.
Different device topologies are compared with an emphasis on parallel plate
capacitor structures. The material and device integration challenges including the
bottom electrode patterning for vertical devices are discussed. Innovative device
topologies and fabrication approaches are introduced to reduce the fabrication
complexities. The details of the BST varactor layout and fabrication are provided.
Characterization and modeling of the BST varactors are summarized in
Chapter 4. Both low and high frequency measurements are presented. The
challenges in the parameter extraction at high frequencies are discussed. Equivalent
circuit models showing good agreement with measured results are developed for
BST varactors. Optimization efforts are presented for the device loss improvement.
BST varactor loaded transmission lines are presented in Chapter 5. Theory
and design equations for analog phase shifters are reviewed. Measured and
simulated results are presented for an X Band 1800 phase shifter. This circuit
demonstrated the best figure of merit reported in the literature. A different phase
shifter with the improved return loss performance designed at Hughes Research
Labs (HRL) is fabricated at UCSB using BST varactor technology. Return losses
better than 20 dB are demonstrated over the design band even the BST varactors
are tuned with the good insertion loss performance.
3
Chapter 6 highlights the efforts for highly integrated BST tunable circuits.
Very compact small size BST lumped element phase shifters are presented for
lower GHz frequencies. Promising results comparable to semiconductor
alternatives are reported. Low voltage tunable matching networks are fabricated to
improve power amplifier efficiencies in handset modules for wireless application.
In the last chapter, we provide a summary and discussion of the future work
to further improve the BST circuit performance.
4
Chapter 2
BST Thin Film Varactors for Tunable
Microwave Circuit Applications
In this chapter, motivations for using Barium Strontium Titanate (BST) thin
films in tunable high frequency circuit applications are discussed. Available
alternative varactor technologies are compared with the advantages/disadvantages
highlighted for each technology. The applications that could potentially benefit
from using BST are listed such as phase shifters. A comparison for different phase
shifter technologies will be presented along with the reasons for using BST thin
films. A brief overview of the important BST thin film material properties will
follow.
2.1 Motivations for BST Thin Films
Barium strontium titanate, Ba1-xSrxTiO3, is being widely investigated as a
suitable dielectric material for a variety of applications including tunable RF and
microwave circuits, dynamic random access memories (DRAM), bypass capacitors,
and non-volatile memories [1]. Thin-film BST has several properties that make
these applications possible. Most importantly, the BST films show a field
dependent permittivity. When bias is applied to a BST capacitor, the dielectric
5
constant changes in a non-linear fashion. (The origins of this behavior will be given
when the material properties are discussed in the following sections). The non-
linearity of the dielectric properties with respect to an applied dc voltage make BST
attractive for tunable microwave devices such as varactors, filters, voltage
controlled oscillators (VCO), delay lines and phase shifters [2]. A typical
capacitance vs. voltage curve is shown in Figure 2.1 for BST parallel plate
capacitors, which has been the focus of our research. BST films offer a low cost,
20
25
30
35
40
45
50
-20 -10 0 10 20
Cap
acita
nce
(pF)
Voltage (V)
BST Varactor
Figure 2.1: A typical capacitance vs. voltage characteristics of BST varactors.
scalable varactor technology for tunable RF and microwave circuits. BST based
devices and circuits could potentially provide an alternative to semiconductor
varactors. The BST varactors with high tunabilities, defined as the ratio of
6
maximum permittivity to its minimum value (max) (min)/ε εr r , of up to 4:1 have been
demonstrated.
BST films have very high dielectric constant typically in the range of 200-
350, making them suitable for small-area bypass capacitors and MEMS switches.
In the early 1990’s, there was a huge research effort in DRAM industry for
alternative high dielectric constant materials. Ferroelectric thin film materials,
particularly BST, have been investigated as a replacement for the silicon
oxide/nitride dielectric material. GaAs chips for wireless communication
applications use on chip BST bypass capacitors gaining a performance advantage
over external bypass capacitors. [3] Smaller device packages with reduced pin
count are possible which do not require external components and bonding. In this
thesis, small area BST bypass capacitors were fabricated in a tunable matching
network, which is discussed in Chapter 6. It is also important to note that the high
dielectric constant makes it very difficult to manufacture small size varactors used
in high frequency circuits, typically 0.2-1 pF, because of the small capacitor areas
in the range of 5-10 mµ 2 . The issues related to fabrication of small area varactors
will be discussed in Chapter 3.
BST films have very high breakdown fields typically more than 2 × 106
V/cm. This allows a large RF signal to be applied to devices and indicates good
power-handling capability [4]. Intrinsic fast polarization response of the BST films
allows continuous and rapid tuning. The fast field response combined with the non-
7
linear behavior of the dielectric permittivities enables frequency conversion devices
such as multipliers and up/down converters using BST thin films.
Figure 2.2: BST bypass capacitors to reduce chip size and improve device performance [3].
There are currently three competing technologies for discrete integrated
microwave varactors that can satisfy industry requirements. Some important
features of these technologies, namely GaAs semiconductor, BST thin film and
Micro-Electro-Mechanical-Systems (MEMS) varactors, are contrasted in Table 2.1.
Note that the entries reflect data general-purpose continuously variable varactors
8
suitable for mm-wave operation. It is apparent that there are pros and cons for each
technology, and therefore the choice depends strongly on the particular application.
Low ?? H igh C ost
N on - herm etic
Flip,C & W ,B um p H erm etic/V acu
um
??
H erm etic
Flip,C & W ,B u
m p
Packaging
G ood, needs to be
quantified
T rades w ith control
voltage
T rades w ith control
voltage
Fast
<5 - 30V (bipolar)
Thickness dep.
M oderate
(Q <100 typ)
G ood
2 - 3:1 typ
BST
Poor
Excellent
Excellent
Slow
< 60 V
(bipolar)
V ery G ood
(Q <200)
L ow
(<1.5:1)
M EM S
E xcellent R eliability
<10V
(unipolar)
D oping dep.
C ontrol
V oltage
Poor IM D
Poor Pow er
H andling
Fast T uning
Speed
M oderate
(Q <60 ty p.) R F L oss
(Q )
G ood
2 - 3:1 typ T unability
(at high Q )
G aA s
Table 2.1: The comparison of currently available varactor technologies.
Both BST and MEMS technologies have recently emerged and show
significant promise for implementation of low-cost high performance circuits. [1]
The most important feature of MEMS varactors is their very low loss
characteristics. The high performance tunable filters and very low loss phase
shifters with high quality factors can be implemented using MEMS varactors. They
are very linear devices and therefore result in low inter-modulation products.
9
However, they are relatively slow compared to BST and GaAs varactors and
require higher control voltages. The high cost of packaging for MEMS devices has
been impediment to the development of a low cost alternative varactor technology.
Reliability has been also a concern for MEMS devices due to problems with the
stiction as a result of the dielectric charge up in capacitive switches and resistance
degradation in dc switches.
On the other hand thin-film BST varactors offer several advantages over
semiconductor varactor diodes and MEMS devices. An important feature of BST
technology—in comparison to semiconductor-based alternatives—is the wide
variety of substrate materials available for thin-film deposition. Using inexpensive
substrates and demonstrated high-volume deposition technologies, very low cost
microwave circuits can be realized using thin-film BST. The fabrication and
packaging of BST varactors are easier and cheaper compared to MEMS based
devices. They have higher breakdown field strengths and higher power handling
capability than semiconductor diodes. Good power handling and IMD can be
obtained by using relatively thicker films at the expense of control voltage.
There are certain applications which appear to favor thin-film BST
varactors including: 1) those that require rapid, continuous tuning at low voltages,
such as phase-shifters or delay lines used in phased array and phase linearization
systems, and 2) frequency conversion devices, such as frequency multipliers or
mixers, that exploit the “fast” capacitive non-linearity. Inexpensive broadband or
frequency agile components such as tunable matching networks, splitter/combiners
10
can be manufactured using a low cost BST technology. The desirable features of
inexpensive BST thin film technology are summarized below:
• BST films should have low loss tangents (tan δ < 0.01). BST films are
shown to have very low losses and little dielectric dispersion into GHz
frequency range (Figure 2.3) [5]. The tunabilities better than 2:1 should
be readily available.
• Inexpensive substrates must be used for BST thin film growth.
Standard growth and processing technologies are necessary for high
volume production.
• Simple device fabrication and low cost packaging are crucial to be cost
effective.
• Reproducibility and reliability issues should be addressed.
In this thesis, BST films grown by sputtering and MOCVD were studied.
Thin films are sputtered from 3” BaxSr1-xTiO3 targets. BST films are sputtered
on inexpensive substrate, such as high resistivity (HR) silicon, glass and sapphire,
which have excellent microwave properties. Film stoichiometry has been optimized
for high tunability and low loss performance. Our work has focused on
Ba0.5Sr0.5TiO3 (50/50 target) and Ba0.25Sr0.75TiO3 (30/70 target) film
compositions.
11
2.2 BST Thin Films for Phase Shifter Applications
Modern phase array systems require a large number of expensive phase
shifters. Therefore, low loss and low cost microwave phase shifters are required to
improve performance and reduce the cost of phase arrays to ensure widespread
application. At the present time, the phased array antennas are being used for long
range (X-Band) and short range (Ka-W Band) communication and radar systems.
Anywhere from 2-10 to thousands of phase shifters are needed in different types of
phased array antenna systems. BST thin films have been investigated as a potential
low cost voltage tunable element for microwave circuit applications because of
their high tunability, relatively low loss, and fast switching speed. Several groups
[1, 6-8] have implemented phase shifters using BST thin films.
Figure 2.3: The loss tangent and the capacitance density as a function of frequency [9].
12
Semiconductor diode and ferrite phase shifters have been two principal
means of providing phase control of microwave signals. Tunable BST phase
shifters offer the advantages of broad tuning range compared to ferrites, reduced
resistive losses compared to p-n junction varactor diodes, reciprocity, and fast
switching times. Thin films of tunable ferroelectric materials offer the additional
advantages of lightweight, compactness, lower processing temperatures, lower
operating voltages, low cost and compatibility with semiconductor processing
technology [6].
2.3 Fundamentals of BST Material Properties: Bulk vs. Thin
Films
A ferroelectric material has spontaneous polarization that can be reversed
by an applied electric field. This response manifests itself as a hysteresis loop in the
response of polarization to an external electric field [10]. They have a characteristic
structural phase transition temperature, called the Curie point ( CT ) where the
material undergoes a structural change from the ferroelectric phase to a non-polar,
paraelectric phase. As can be seen from Figure 2.4a, the relative bulk permittivity
increases as the temperature approaches the Curie point. Above CT , permittivity
decreases with temperature and often exhibits Curie-Weiss behavior where C is the
Curie constant.
13
rc
Cε (T)=T-T
(2.1)
In the paraelectric regime, the spontaneous polarization is zero but the permittivity
remains high. Therefore, materials in the ferroelectric regime exhibit a memory
effect via the hysteresis behavior, which is absent in the paraelectric phase. Hence,
the ferroelectric phase is necessary for nonvolatile memory applications, whereas
paraelectric phase is preferred for DRAM applications. The material chosen should
remain in one of these two phases in the normal operating temperature range for a
particular application.
Figure 2.4a-b: Comparison of the permittivities of bulk and thin film BST as a function of
temperature [11, 12]. Figure 2.4a shows much higher permittivities for bulk materials. In Figure 2.4 b, the sharp peak in the permittivity is suppressed for thin film.
Ba1-xSrxTiO3 is a continuous solid solution between BaTiO3 and SrTiO3
over the whole concentration range. The unit cell structure for the BST material is
shown in Figure 2.5. The Curie temperature of BST decreases linearly with
14
increasing Sr concentration at a rate of 3.4º C per mole % Sr. As a result, the
transient temperature and hence the electrical and optical properties of BST can be
tailored over a broad range to meet the requirements of various electronic
applications.
Figure 2.5: The structure of (Ba,Sr)TiO3. Ba and Sr occupy the center position and with Ti
at the cube corners, surrounded by oxygen octahedra.
There was a substantial research effort in the DRAM industry to incorporate
high K, ferroelectric materials into device processes since the early nineties. The
technology for higher density memories continues to be an important issue for the
next generation memory devices as typical circuit size becomes smaller and higher
15
capacitance densities are required. Using thinner films in the process solved this
requirement for increased capacitance up to some degree. However, the dielectric
thickness has reached a lower limit set by electron tunneling through the dielectric
thus the capacitor area can no longer be scaled down using planar device structures.
For high charge storage densities, ferroelectric materials have been prime
candidates with dielectric constants ranging well in to the thousands.
Although bulk dielectric constants in BST are quite high, the dielectric
constant of thin film BST is much smaller, particularly when film thickness is
reduced below about 100 nm as seen in Figure 2.4a [11]. This is due to the
observed decrease in permittivity with decreasing film thickness [13]. For DRAM
applications the maximum possible capacitance density is required while
maintaining acceptable leakage currents and dielectric lifetime. There is a trade of
between increasing capacitance by reduced film thickness due to the thickness
dependent permittivity. The DRAM efforts have not been concerned with the
tunability or other properties important for microwave varactor circuits. Our main
focus has been to optimize sputtered BST films for high tunability and low loss to
be used in applications such as a varactor.
For the purpose of understanding the underlying dielectric behavior, one
must consider the response of the polarization as a function of the applied field as
the fundamental quantity of interest. For ferroelectric material, the nonlinear
relationship between the applied field and polarization is most simply described by
16
a power series expansion of the free energy in terms of the order parameter,
polarization as in Landau-Ginzburg-Devonshire (LGD) theory [12].
effectiveE (T )P Pα α= + 31 11 (2.2)
ii
i
PE
ε χ ∂=∂0 (2.3)
where E is the electric field across the film and P is the polarization normal to the
substrate, α1 and α11 are the appropriate dielectric stiffness. It is found that for the
BST films α11 is not temperature dependent. For the ferroelectric materials, the
film permittivity is almost equal to the susceptibility.
By integrating the small signal capacitance curve shown in Figure 2.6a,
polarization versus field is obtained shown in Figure 2.6b, which has a functional
form of Eqn. (2.2) [12]. The fit is seen to be a very good description of the non-
linearity in the polarization data. Using the LGD formula, we obtained
. X cm/Fα = 101 2 4 10 and 5 2. X cm /C Fα = 20
11 0 75 10 , which are comparable to
the values reported in the literature. Thus the general shape of our C-V data is very
well described by classical nonlinear dielectric theory. The magnitudes of the
coefficients are different from those obtained from the bulk, as they must be given
the differences in permittivity.
17
8
9
10
11
12
13
14
15
-8 -6 -4 -2 0 2 4 6 8
Cp
Cap
acita
nce
Den
sity
(fF/u
m^2
)
Bias (V)
-10
-5
0
5
10
-8 -6 -4 -2 0 2 4 6 8
MeasuredLGD Theory
Pola
rizat
ion(
uC/c
m^2
)
Bias(V) Figure 2.6 a-b: The capacitance density and polarization curve as a function of bias. The
polarization curve is obtained by integrating the measured C-V small signal data. The LGD model fits the data very well.
18
Figure 2.7: The field dependence of permittivity as a function of film thickness [14].
The variation of the apparent permittivity with applied bias as a function of
film thickness can be seen in Figure 2.7. The apparent permittivities are found to
decrease systematically with film thickness at electric fields near zero. At higher
fields, the apparent permittivities become independent of thickness [12]. For the
varactor application, it is apparent that the thicker films give a higher tunability at
the expense of increased bias voltages.
Figure 2.8a and 2.8b show the dielectric data for Ba0.49Sr0.51TiO3 (65 mT),
Ba0.24Sr0.76Ti0.96O3 (35 mT), and SrTiO3 thin films. Fig 2.8a shows that the
permittivity at zero bias field is a function of thickness. This thickness dependence
19
Figure 2.8: (a) Dielectric constant and (b) inverse capacitance density as a function of thickness
is often attributed to the presence of an interfacial layer in series with the thickness
dependent capacitance density of the bulk of the film [15]. This dead layer has a
lower permittivity, which reduces the total film permittivity as the film thickness is
decreased [16]. Expressing the apparent capacity density at zero field as the inverse
sum of two capacitors connected in series,
app i B
-A A A= +C C C ε ε ε ε
= +i i
i o B o
t t t (2.4)
where the interfacial and the bulk parameters are represented by “i” and “B”
subscripts, respectively, appC is the measured (apparent) capacitance, A is the area
and t is the total film thickness. The first term in the Eqn. (2.4) indicates the
presence of a constant valued interfacial capacitance density and its value is given
by the non zero intercepts in the inverse of the capacitance density plots shown in
Figure 2.8b. The interfacial capacitance is between 40-80 fF/µm2 for the plotted
100
200
300
400
500
600
700
800
900
0 1000 2000 3000 4000 5000
Die
lect
ric c
onst
ant
Thickness [Angstroms]
Ba0.49
Sr0.51
TiO3
Ba0.24
Sr0.76
Ti0.96
O3
STO
0
0.02
0.04
0.06
0.08
0.1
0 1000 2000 3000 4000 5000Inve
rse
capa
cita
nce
dens
ity [ mm mm
m2 /fF
]
Thickness [Angstroms]
STO
Ba0.49
Sr0.51
TiO3
Ba0.24
Sr0.76
Ti0.96
O3
20
films. As the film thickness increases the thin interfacial capacitance layer has a
smaller effect. The data on Figure 2.8b implies that the total film thickness t is
large compared to the interfacial layer thickness, it since the data lies on a straight
line. The constant capacitance is usually thought to represent some type of
interfacial layer between the dielectric and one or both of the electrodes, and might
arise from surface contamination of the BST, nucleation or reaction layers at the
film/electrode interfaces, or changes in the defect chemistry at the dielectric-
electrode interfaces.
The field and thickness dependence of the permittivity in ferroelectric and
paraelectric thin films have been mostly explained by Schottky barrier model. In
this model, the variation in apparent capacitance with bias explained via a voltage
dependent interfacial depletion layer capacitance in series with the capacitance of
the bulk of the film, whose permittivity is taken to be bias-independent.
Temperature dependence of the dielectric constant for the BST thin films is
shown in Figure 2.4b [12]. The zero field permittivity starts to decrease linearly
around 300 K while the apparent the permittivity stay almost constant at higher
electric fields regardless of temperature. However, a sharp peak in the permittivity
at the bulk transition is not found in these films, contrary to what would be
observed for a stress-free and homogeneous macroscopic ferroelectric shown in
Figure 2.4a. The possible reasons for this include finite size effects, an
inhomogeneous depression of the transition temperature, or the external constraint
imposed by biaxial strain on the film from the substrate.
21
The theories of the bulk dielectric and ferroelectric properties of perovskites
such as BST are well understood [10]. However, the thin films of these compounds
exhibit variations in their polarization behavior with the changes in applied voltage,
operating temperature, particle size, and film thickness that are not well understood
[13]. Much of the research was targeted towards optimization of material properties
and finding appropriate solutions to DRAM integration issues. A good
understanding of material properties in such thin films is essential before they may
be successfully integrated into commercial devices in near future.
Since BST films are ferroelectric, they show a non-linear relationship
between electric displacement (or polarization) and electric field, even if when they
are in paraelectric phase above the Curie temperature. Polarization charging
currents flow in to such materials with a power-law time dependence of
approximately t-n where n< 1 [17]. A time dependent polarization manifests itself in
the frequency domain as a dispersion of the permittivity as a function of frequency.
Permittivity values are often reported at only a single frequency, neglecting the
decrease in permittivity with frequency from dispersion. It has been demonstrated
for high quality BST films with low leakage that the dielectric loss given by the
loss tangent can be derived form the frequency dispersion of the permittivity [18].
This is true since both quantities are related to the Fourier Transform of the time
dependent polarization mechanism, which is described by Curie von–Schweidler
behavior.
22
Investigation of field, temperature, and electrode work function dependence
of the leakage, with proper consideration of leakage versus relaxation, has provided
strong evidence that leakages are controlled by the reverse characteristics of back to
back Schottky barriers at each film-electrode interface [19]. Because of this there is
not a strong dependence of leakage on film thickness at a given electric field,
except due to the change in the field induced barrier height lowering.
Lifetime and reliability are also other extremely important issues in the
practical use of the capacitors. Therefore, determining failure mechanisms and
estimating lifetimes are crucial in the BST technology. The most important failure
mechanism in perovskite titanate thin films is resistance degradation, which is
defined as a slow increase of leakage current under a constant applied electrical
field after prolonged times. It has been proposed that deterioration at the grain
boundaries contributes to resistance degradation such as reduction of the grain
boundary potential barrier height due to space-charge accumulation, demixing
reactions of oxygen vacancies, and oxygen vacancy pile up at the electrodes. The
majority of the degradation theories are based on electromigration of oxygen
vacancies in a given dc electric field. Oxygen vacancies are present in significant
numbers in undoped and acceptor doped alkaline earth titanates. They are
positively charged with respect to the host lattice and in a dc electrical field they
can migrate toward the cathode. While the oxygen vacancies pile up in front of the
cathode and are compensated by the electrons injected from the cathode, a chemical
reaction can occur at the anode producing additional mobile oxygen vacancies.
23
References
[1] R. York, A. Nagra, E. Erker, T. Taylor, P. Periaswamy, J. Speck, S.
Streiffer, and O. Auciello, "Microwave integrated circuits using thin-film
BST," 2001.
[2] P. C. Joshi and M. W. Cole, "Mg-doped Ba/sub 0.6/Sr/sub 0.4/TiO/sub 3/
thin films for tunable microwave applications," Applied Physics Letters,
vol. 77, pp. 289-91, 2000.
[3] D. Ueda, "Implementation of GaAs monolithic microwave integrated
circuits with on-chip BST capacitors," Journal of Electroceramics, vol. 3,
pp. 105-13, 1999.
[4] B. Acikel, L. Yu, A. S. Nagra, T. R. Taylor, P. J. Hansen, J. S. Speck, and
R. A. York, "Phase shifters using (Ba,Sr)TiO/sub 3/ thin films on sapphire
and glass substrates," presented at IEEE MTT-S International Microwave
Sympsoium, 2001.
[5] J. D. Baniecki, R. B. Laibowitz, T. M. Shaw, P. R. Duncombe, D. A.
Neumayer, D. E. Kotecki, H. Shen, and Q. Y. Ma, "Dielectric relaxation
of Ba/sub 0.7/Sr/sub 0.3/TiO/sub 3/ thin films from 1 MHz to 20 GHz,"
Applied Physics Letters, vol. 72, pp. 498-500, 1998.
[6] A. Kozyrev, V. Osadchy, A. Pavlov, and L. Sengupta, "Application of
ferroelectrics in phase shifter design," 2000.
24
[7] F. De Flaviis and N. G. Alexopoulos, "Low loss ferroelectric based phase
shifter for high power antenna scan beam system," 1997.
[8] V. K. Varadan, K. A. Jose, V. V. Varadan, R. Hughes, and J. F. Kelly, "A
novel microwave planar phase shifter," Microwave Journal, vol. 38, pp.
244, 248, 250, 253-4, 1995.
[9] D. E. Kotecki, J. D. Baniecki, H. Shen, R. B. Laibowitz, K. L. Saenger, J.
J. Lian, T. M. Shaw, S. D. Athavale, C. Cabral, Jr., P. R. Duncombe, M.
Gutsche, G. Kunkel, Y. J. Park, Y. Y. Wang, and R. Wise,
"(Ba,Sr)TiO/sub 3/ dielectrics for future stacked capacitor DRAM," IBM
Journal of Research and Development, vol. 43, pp. 367-82, 1999.
[10] C. Basceri, "Electrical and dielectric properties of (barium, strontium)
titanium trioxide thin film capacitors for ultra-high density dynamic
random access memories," NORTH CAROLINA STATE UNIVERSITY,
1997.
[11] T. M. Shaw, Z. Suo, M. Huang, E. Liniger, R. B. Laibowitz, and J. D.
Baniecki, "The effect of stress on the dielectric properties of barium
strontium titanate thin films," Applied Physics Letters, vol. 75, pp. 2129-
31, 1999.
[12] C. Basceri, S. K. Streiffer, A. I. Kingon, and R. Waser, "The dielectric
response as a function of temperature and film thickness of fiber-textured
(Ba,Sr)TiO/sub 3/ thin films grown by chemical vapor deposition,"
Journal of Applied Physics, vol. 82, pp. 2497-504, 1997.
25
[13] R. Waser, "Dielectric analysis of integrated ceramic thin film capacitors,"
1997.
[14] P. Padmini, T. R. Taylor, M. J. Lefevre, A. S. Nagra, R. A. York, and J. S.
Speck, "Realization of high tunability barium strontium titanate thin films
by rf magnetron sputtering," Applied Physics Letters, vol. 75, pp. 3186-8,
1999.
[15] P. K. Larsen, G. J. M. Dormans, D. J. Taylor, and P. J. van Veldhoven,
"Ferroelectric properties and fatigue of PbZr/sub 0.51/Ti/sub 0.49/O/sub
3/ thin films of varying thickness: blocking layer model," Journal of
Applied Physics, vol. 76, pp. 2405-13, 1994.
[16] S. K. Streiffer, C. Basceri, C. B. Parker, S. E. Lash, and A. I. Kingon,
"Ferroelectricity in thin films: The dielectric response of fiber-textured
(Ba/sub x/Sr/sub 1-x/)Ti/sub 1+y/O/sub 3+z/ thin films grown by chemical
vapor deposition," Journal of Applied Physics, vol. 86, pp. 4565-75, 1999.
[17] A. K. Jonscher, Dielectric Relaxation in Solids. London: Chelsea
Dielectrics Pressh, 1983.
[18] S. K. Streiffer, C. Basceri, A. I. Kingon, S. Lipa, S. Bilodeau, R. Carl, and
P. C. Van Buskirk, "Dielectric behavior of CVD (Ba,Sr)TiO/sub 3/ thin
films on Pt/Si," 1996.
[19] G. W. Dietz, M. Schumacher, R. Waser, S. K. Streiffer, C. Basceri, and A.
I. Kingon, "Leakage currents in Ba/sub 0.7/Sr/sub 0.3/TiO/sub 3/ thin
26
films for ultrahigh-density dynamic random access memories," Journal of
Applied Physics, vol. 82, pp. 2359-64, 1997.
27
Chapter 3
BST Device Technology Issues
This chapter deals with the technology issues for the monolithic barium
strontium titanate (BST) varactors. General device issues related to BST varactors
are presented first. The challenges for the integration of ferroelectric materials into
monolithic fabrication processes are discussed. Different device layouts and
processes are compared. Early efforts focused on silicon substrate. Fabrication
techniques for different device structures on different substrates are discussed in
detail.
3.1 General Device Technology
The most desirable electrical characteristics for BST thin-film varactor
technology include high tunability, low RF loss tangents (high Q-factors), and good
power-handling capability. Equally important for commercial applications are
reproducibility, use of proven high-volume deposition technologies, and the use of
standard integrated-circuit processes for foundry compatibility.
In comparison to semiconductor alternatives thin-film BST devices promise
to be extremely competitive in terms of cost without a significant sacrifice in
performance for many applications [1, 2]. In order to fully exploit this advantage,
28
careful attention must be paid to the choice of substrate, deposition methods, circuit
design, and packaging. The BST thin-film technology is still relatively immature,
with numerous problems to be solved. The growth optimization of the BST
material, the electrodes and electrode-BST interfaces are sources of difficulty. The
fabrication technology of BST varactors is equally important and must be
addressed carefully by the researchers in the field.
Two different types of varactors, vertical (parallel-plate) or planar
(interdigital), are possible using BST thin films. The device schematics for both
types of devices are shown in Figure 3.1a and 3.1b. For the interdigital capacitors,
BST films are directly deposited on the appropriate substrate followed by top
interdigital electrode metallization. In general, interdigital devices are simpler to
fabricate and integrate into circuits, but suffer from reduced tunability (due to large
fringing electric field in the air) and higher control voltages. Having smaller
spacings between the fingers can further increase available tunability at lower
voltages. Typical operating voltages for interdigital capacitors are in the range of
100 V’s with a typical tunability of 2:1. The parallel plate capacitors, on the other
hand, can be operated with much lower bias voltages, making them attractive for
most microwave and millimeter-wave applications [3]. For parallel plate capacitors,
BST films are deposited directly on a bottom electrode on substrate. Then the top
electrodes are defined creating metal-insulator-metal (MIM) structures. The
distance between the electrodes is basically the BST film thickness and much
shorter than the spacings in the interdigital structures. That’s why the control
29
voltages typically scales with the film thickness. Also vertical structures offer a
higher tunability compared to interdigital structures since the electric fields are
better confined in the film. The control voltage or power handling capacity is easily
manipulated through control of the material thickness, but the integration of bottom
electrodes and other structures require more detailed fabrication. Figure 3.2a and
3.2b show tunability curves for typical BST parallel plate MIM and interdigital
structures fabricated at UCSB.
Since higher tunabilities can be obtained at relatively much lower bias
voltages, the parallel plate capacitors offer more flexibility in many circuit
applications. Typical electronic system requirements are very stringent in terms of
voltage requirement and the BST tunable varactors remain the only candidate for
the customer end applications such as wireless industry. That’s why our research
efforts have focused on the development of new technologies for integrated
parallel-plate devices.
Material deposition techniques such as rf magnetron sputtering and
chemical vapor deposition (CVD) are compatible with high production
requirements and promising for the development of low-cost microwave circuits. In
either case, careful study of the influence of growth parameters on material
properties, and correlation with device (electrical) properties is required. To date,
most of our work has used sputtered BST films. Sputtering is a widely used
deposition technique for a variety of materials including metals and dielectrics.
Sputtering is done at low gas pressures with plasma. It has been largely employed
30
Figure 3.1a-b: BST interdigital and parallel plate varactor device schematics.
3.5
4
4.5
5
5.5
6
6.5
7
-20 0 20 40 60 80 100
Width=2um,Spacing=1um Width=2um, Spacing=2um
Cap
acita
nce
(pF)
DC Bias (V)
20
25
30
35
40
45
50
-20 -10 0 10 20
Cap
acita
nce
(pF)
Voltage (V)
BST Varactor
Figure 3.2: Typical tunability curves for BST interdigital and parallel plate capacitors fabricated at UCSB.
31
for the following reasons: any material can be volatilized by positive ion
bombardment, compounds are volatilized stoichiometrically, high deposition rates,
and uniformity over large areas.
3.2 BST Parallel Plate Capacitors
The major issues requiring development for the integration of BST films
into vertical process are the adhesion layer of the bottom electrode, BST
deposition, electrode patterning, top electrode and process control to prevent further
performance degradation [4, 5]. Figure 3.3 summarizes the device related issues
related to vertical devices using BST films. Many groups have been investigating
different substrates for BST deposition. In our research, only low cost inexpensive
substrates were considered as a candidate for microwave integrated circuits. High
volume production is also a requirement for such an inexpensive technology
requiring large area substrates.
Our initial efforts focused on high-resistivity (HR) silicon since studies in
the DRAM industry have demonstrated a silicon compatible BST technology with
good film properties. HR silicon has a lower loss tangent than doped silicon
substrate making it suitable for microwave applications. Also large area HR silicon
substrates are available at relatively low cost. One other advantage silicon offers is
the possibility of using micro-machining to reduce the effective dielectric constant,
which is helpful in lowering transmission-line losses. Special care is required when
implementing low-loss high frequency transmission-lines on silicon.
32
Top Electrode
BST film
Pt
TiO2
SiO2
Si Substrate
BST film issuesStoichiometryBa/Sr ratioOrientationStressStructure
Diffusion BarrierElectrode-substrate reactionAdhesion, stressEase of processing
Adhesion layerEnhance electrode adhesionWithstand BST depositionconditionsEase of processing
Bottom Electrode issuesHigh growth temperaturesOxidation resistanceSufficient conductivitySurface roughnessAdhesionThermal stressesPatterning
BST varactor on Si
Figure 3.3: Schematic of stacked BST capacitor and relevant device integration issues.
The need to deposit the BST films in an oxygen environment at very high
temperatures, typically in the range of 450-700 ºC, makes the bottom electrode
choice crucial. Most integration schemes for perovskite dielectrics use noble metal
or metal-oxide electrodes in combination with a deposited diffusion barrier material
at the electrode/plug interface for DRAM applications [4]. The formation of an
insulating oxide at the BST-electrode interface during the growth will lower the
capacitance density and lower tunability. Pt, Ru, Ir or their conducting oxides have
been investigated by many groups as the bottom electrode [6]. From these metals,
reactive ion etching of Ru and RuO2 has been relatively easy due to their volatile
Ru oxides and halides. Patterning of Pt (and Ir) electrode material is complicated
by the absence of any low temperature readily formable volatile etch products. Pt is
typically patterned by reactive ion etching (RIE) using Cl2-based chemistry and a
patterned hard mask, which limits the bottom electrode thickness and fine scale
33
features with high aspect ratios. Physical sputtering is believed to be the dominant
etch mechanism when conventional dry-etching techniques are used.
Platinum base electrodes are still most commonly used for its oxidation
resistance, its high conductivity compared to oxide electrodes and its compatibility
with high temperature growth. BST capacitors with Pt electrodes have yielded the
best leakage characteristics because of the high work function of Pt (5.65 eV).
However, special care must be taken to avoid excessive compressive stress in the
Pt, which can lead to hillock formation and shorted devices. Another difficulty
involves adhesion of the Pt electrode to the substrate, sometimes leading to
process-induced delamination. Special care must be taken for the development of
the diffusion barriers and adhesion layers to solve these problems.
In our early studies, BST films were sputtered from a stoichiometry
0.5 0.5 3( )Ba Sr TiO target on to Pt (100nm)/ 2TiO (100nm)/ 2SiO (100nm)/ Si
substrates. Substrate templates were purchased from an outside vendor (Silicon
Quest, Santa Clara, California). 2TiO was sputter deposited at 400 C° . The
substrates were ultrasonically cleaned with acetone and isopropanol prior to BST
deposition. SiO2 and TiO2 were grown under the Pt as oxygen diffusion and
adhesion layers, respectively. The Pt metal must be deposited at elevated
temperatures to avoid hillocking upon cooling after BST film deposition due to the
thermal expansion mismatch between the Pt film (8.8×10-6 °C @ 25°C) and Si
substrate (2.618×10-6 °C @ 25°C). During the fabrication process, severe
34
delamination problems were observed because of poor bottom electrode adhesion
to the silicon substrate, making the production of large area circuits hard and
lowering the yield.
We also investigated BST parallel plate varactors on both glass and
sapphire substrates as alternative candidates because of their excellent microwave
properties [2]. Both substrates have low loss tangents in the orders of 410− and are
relatively low cost compared to other oxide substrates, such as MgO or LaAlO3.
The resistivity of sapphire (~1012 Ω cm) is higher than that of silicon (~0.01-10 Ω
cm) and HR silicon (~102-104 Ω cm). Glass also has the advantage of a lower
dielectric constant than silicon reducing the transmission line losses in the circuits.
Suitable bottom electrodes and adhesion layers have been investigated for both
substrates. Platinum has been grown epitaxially on sapphire substrate (C&A plane)
at 600 ºC without an adhesion layer enabling very smooth BST films to be grown.
BST films were also grown on prepatterned glass and sapphire samples that had
Ti/Au/Pt e-beam evaporated metals as bottom electrodes. The device processing
issues related to each substrate system will be discussed in the following sections.
35
100
200
300
400
500
600
700
800
900
20
40
60
80
100
120
140
160
180
0 1000 2000 3000 4000 5000
Die
lect
ric c
onst
ant
Quality factor
Thickness [Angstroms]
Q sapphire
K sapphire
K silicon
Q silicon
Figure 3.4: Permittivity and quality factor for Ba0.49Sr0.51TiO3 thin films grown on sapphire and silicon substrates at UCSB.
Noticeable differences were observed in the dielectric constants and quality
factors of the 100 nm BST films developed on sapphire and silicon substrates.
Higher dielectric constants and better quality factors were found on the films
deposited on sapphire as shown in Figure 3.4. The larger quality factor was
attributed to a better Pt bottom electrode and increased growth rates. The Pt bottom
electrode and subsequent oxide growth surface deposited on sapphire was a smooth
epitaxial film (~3 Å rms roughness) opposed to the platinized silicon with a 30-40
Å rms roughness. The effect of bottom electrode surface roughness on the film has
not been completely investigated. Decrease in quality factor as film thickness
increases has been attributed to increased resistive losses as the overall volume of
the dielectric increases. It is found that the growth rate also impacts quality factor
[7]. Possible explanations for the dependence of loss tangents on growth rate
36
include: less film contamination from residual gases, reduced growth surface
exposure to energetic particles and bombardment, and increased scattering of
energetic particles by a faster growth rate.
100
150
200
250
300
350
400
450
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
Perm
ittiv
ity
Electric Field [MV/cm]
Ba/Sr =50/50
Ba/Sr Target=30/70
Figure 3.5: The tunability is shown for BST films grown at UCSB with two different compositions.
The different film composition profoundly affects the film dielectric
properties. Researches have found that the maximum dielectric constant is
produced when the (Ba + Sr)/Ti ratio is equal to one. The dielectric constant
decreases when films are either titanium rich or titanium poor. The Ba/Sr ratio also
impacts film properties as higher dielectric constants and higher loss tangents are
associated with higher barium content. Figure 3.5 shows the tunability for two
37
different Ba/Sr targets used. 50/50 target has given 4:1 tunability whereas 30/70
film tunability was 2:1.
3.3 High Frequency BST Varactor Design -Early Device
Most high frequency circuit applications require small size capacitors in the
monolithic circuits. As discussed previously, BST films have very high dielectric
permittivities; typically in the range of 200-350. The value of a parallel plate
capacitor is given by
0ε ε= r
d
ACt
(3.1)
where rε is relative dielectric constant, 0ε is vacuum dielectric permittivity, A is
the area of the device and dt is the film thickness. Given the high dielectric
constants of the BST films, the small value capacitors can only be achieved by
small contact areas typically in the 2mµ range, requiring tight lithographic
tolerances. Figure 3.6 shows this relationship in a graphical format for different
capacitor sizes. In a phase shifter designed for K band, for example, the required
BST capacitors have values in 0.1-0.3 pF range. The early BST thin films grown on
silicon substrate typically had a thickness of 100 nm. As it is seen from Figure 3.6
this required capacitor areas of 4-8 2mµ . A device utilizing two capacitors in series
was developed at UCSB, increasing active contact area, which makes the
fabrication easier. The device cross-section and top view schematics are shown in
Figure 3.7a-b [8]. Capacitors connected in series result in reduced capacitance,
38
which enabled doubling the actual capacitor areas. The two capacitors share the
base electrode, which has a floating voltage value. Since the bottom electrodes are
common, there is no need to make contact to it. The tuning voltage is applied
between the top electrodes to change the permittivity.
0
5
10
15
20
25
30
0 500 1000 1500 2000
Cap
acito
r Are
a(um
2 )
Thickness(A)
0.1pF
0.2pF
0.3pF0.4pF
Figure 3.6 The BST parallel plate capacitor areas. as a function of thickness
The connection of small area capacitors to the rest of the circuit is also
crucially important. Normally, this would be done by having contact metals that are
physically in contact with the top electrodes. However, any metal contacting the
BST film, which is on the bottom electrode, would form a capacitor. Since BST has
very large permittivities, even small “active areas” resulting from this extra contact
would change the designed capacitor values tremendously. As a solution to this
problem, a lower permittivity (ε) material was utilized to define the active capacitor
39
areas on BST. By using this layer, the direct contact area of the top electrode is
limited to the opening in the low ε material. The suggested device layout is shown
in the Figure 3.3a. First, the low ε material needs to be patterned creating openings
in it and then, the top electrode is deposited on the hole areas defining the BST
capacitors. SiN and SiO2 dielectric films with low dielectric constant compared to
BST are suitable for defining small active areas in monolithic device fabrication.
The key dimensions of the BST varactor device layout are shown in the
Figure 3.7b. The minimum feature, indicated by w , is chosen for the capacitor
width while the length of the capacitor is denoted by l . The resistance due to the
base electrode is given by
3ρ ρ= ≈sPt
L wRA t l
(3.2)
where ρ is the platinum resistivity, L is the distance between two capacitors, and
Ptt is the bottom electrode thickness. It is assumed that the spreading resistance
under the capacitor is negligible and that the order of magnitude of series resistance
is not affected by this assumption. It is important to recognize that the conductor
contribution is highly dependent on the geometry of the capacitor layout. Equation
(3.2) indicates that the base resistance is minimum when the distance between the
two capacitors is minimized and capacitor length is maximized. This is achieved by
using long narrow stripes in the layout for a given capacitor area. In other words,
maximizing the periphery of the capacitor area optimizes the device performance in
40
this device geometry. The Figure 3.8 shows a comparison of the device quality
factors for the capacitors with different physical layout.
Substrate
BSTBottom Electrode
Top ElectrodesLow dielectricmaterial
BST capacitor
Side View
Top View
w
3w
w w w
l
Contact metals
w=lithography limit
Figure 3.7a-b: Layout schematic for two capacitors in series configuration. The base electrode is shared and tuning voltage is applied between two top contacts.
The bottom electrode thickness has to be increased to reduce the series
resistance contribution due to the base electrode as seen in Eqn. (3.2). Etching of
the bottom electrode is required to isolate the individual devices since the BST
41
films are grown on substrates with blanket Pt bottom electrode. The Pt etch also
proved to be a challenge in the BST fabrication process. Platinum is a noble metal
and ion milling is required to pattern the bottom electrode. Reactive ion etching
(RIE) with high power levels is typically required to etch Pt. The photoresist is not
suitable for such high power levels and long etch times. A harder SiN/SiO2 mask
was used for RIE etching [8]. It is important to remember that, the oxide/nitride
materials are also needed to define the active areas on the BST.
0
10
20
30
40
50
0 5 10 15 20
Mea
sure
d Q
Frequency, GHz
Dev
ice
Q
w=2 um Narrow stripe
w=5 um Square
Figure 3.8: The device Q factor for different physical device layout.
In early process developed at UCSB, SiN was used to etch the bottom
electrode and also as the low ε material. SiN was deposited directly on BST films
using plasma enhanced chemical vapor deposition (PECVD). Then using a
42
photoresist mask it was etched in a RIE system using SF6 /Ar gases to define holes
(the active areas on BST) in the nitride layer. After depositing the top electrodes,
the bottom electrode was etched with another high power RIE step. Later, it was
found that the device loss tangent is significantly affected during the fabrication
process particularly during the etching steps. Figure 3.9a-b show the C-V data
taken for two different devices and the affect of processing on the device quality
factor. One set of data is for devices fabricated on as grown film and the other set
of data is for the films that have gone through the RF process. The Figure 3.9a–c
show that even though RF process doesn’t affect the tunability, the loss tangent is
degraded after processing. Since both samples originally came from the same BST
film growth, the difference in loss tangent can only be explained by process
induced damage. The study that shows particular process steps that cause the
damage is shown in Figure 3.9c. It is clearly seen that the steps involving a RIE
etch of the platinum and silicon nitride windows are responsible for the degradation
in the BST loss tangent [1]. Both PECVD and RIE systems use highly energetic
ions that can potentially damage the film. It has been observed that the SiN etch
step results in more damage because the plasma comes into direct contact with BST
films during the etch when opening holes in the nitride layer. During the bottom
electrode etch the BST film is covered by both top electrode and SiN layers. It is
important to avoid any direct contact between the BST film and the plasma in RIE
steps.
43
40 10-12
60 10-12
80 10-12
100 10-12
120 10-12
140 10-12
160 10-12
180 10-12
-20 -15 -10 -5 0 5 10 15 20
ANL 90901a
Cap
acita
nce
(Far
ads)
Bias Voltage (V)
Unprocessed
Processed
0
0.02
0.04
0.06
0.08
0.1
-20 -15 -10 -5 0 5 10 15 20
ANL 90901a
Loss
Tan
gent
Bias Voltage (V)
Unprocessed
Processed
(a) (b)
0
0.01
0.02
0.03
0.04
0.05
-10.0 -5.0 0.0 5.0 10.0
Loss
Tan
gent
Bias Voltage (V)
As Grown
Pt etch using Cl2 RIE
Window etch using SF6 RIE
ANL 90313
0
0.01
0.02
0.03
0.04
0.05
-10.0 -5.0 0.0 5.0 10.0
Loss
Tan
gent
Bias Voltage (V)
As Grown
Pt etch using Cl2 RIE
Window etch using SF6 RIE
ANL 90313
(c)
Figure 3.9a-c: The affect of the processing steps on film tunability and loss tangent.
Figure 3.10 shows the modified process flow that addresses the problems
described above in the fabrication of the two capacitors in series configuration. The
fabrication details are given in Appendix D. The first step in the fabrication is to
etch the BST films on the bottom electrode and leave BST islands where varactors
will be defined. Next a SiO2 layer is evaporated and patterned by liftoff on these
islands. The SiO2 layer is used instead of SiN because it can be evaporated in the e-
44
beam system at UCSB and patterned by liftoff. E-beam evaporation and liftoff
allow defining the contact areas for the capacitors without the need of etching holes
in the dielectric layer. As a result, the damage introduced by dielectric deposition
and RIE etch has been eliminated. Another advantage of the SiO2 layer is that the
etch rate for the oxide in the RIE system using Cl2 gas is slower than that of the
SiN by almost a factor of two enabling thicker electrodes to be patterned. This SiO2
layer is used as a mask to etch the bottom electrode metal isolating individual
varactors. The SiO2 layer should be thick enough to withstand during Pt etch.
Depending on the bottom electrode thickness the top oxide layer thickness can be
adjusted. After defining active areas with the oxide layer Ti/Pt/Au/Pt top electrodes
are deposited and encapsulated by SiO2. First, the metals were evaporated in an e-
beam system and the sample was transferred without removing the photoresist to
another e-beam system that allows the dielectric evaporation. The titanium layer is
used to promote the adhesion of the top electrodes to the BST film. The first Pt is
used to have a symmetrical electrode structure in the top and bottom electrodes. Au
layer is included to increase the conductivity of the top electrodes reducing
conductor losses. Second Pt layer is included to act as a mask allowing a slower
metal etch. The top SiO2 acts as an encapsulation layer for the top electrode metals.
The metal and oxide thicknesses are determined by photoresist thickness used in
this step. The minimum series resistance contribution is achieved by increasing Pt
and Au thicknesses. The top SiO2 layer thickness is chosen such that the oxide
thickness will be reduced to 200-300Å after the bottom electrode etch is completed.
45
(a )
S u b s tra te
B S TP tS ta rt in g M a te ria l
(b )
S iO 2 S iO 2
B S T
S iO 2 S iO 2
(c )
BST
(d )
SiO2 SiO2S iN
(e )
SiO2 SiO2uBST
Pt
( f)
S iN
S u b s tra te
B S T E tc ha n d S iO 2e va p o ra t io n
T o p E le c tro d e(T i/P t/A u ) a n dS iO 2e va p o ra t io n
B S T a re a s u n d e r th e c a p a c ito r re g io n sa re n e v e r e xp o s e d to R IE d ire c tly a n dp ro te c te d b y m e ta l/o x id e la y e rs .
B o tto m P t E le c tro d eE tch u s in g C l2
S iN S te p C o ve ra g e
S iN e tc h (S F 6 /A r/O 2 )a n d th ic k c o n ta c t m e t-a lliza t io n (T i/A u )
P t/A uP t/A u
P t/A uP t/A uS iO 2
P t/A uP t/A u
Figure 3.10: The process details for the BST varactors with two capacitors in series configuration.
46
Next, the sample is etched in a RIE system using Cl2 gas (5 mT) at high
power (400W). The oxide layer defines the bottom electrode boundaries. A
crossover layer is needed after the bottom electrode etch to allow thick metal
contacts to be brought close to the top electrodes. A thick SiN layer has been
deposited on the sample by plasma enhanced chemical vapor deposition (PECVD).
This is followed by etching holes in the SiN layer using SF6/Ar gases at moderate
power levels. The actual etch time is determined by a control sample using laser
reflection. SiN layer rather than SiO2 is used as the crossover dielectric since the
etch rate for SiN is higher and high quality films can be deposited by PECVD.
Ti/Au (100 Å/ 1.2 um) metallization has been done for CPW layers simultaneously
contacting the top electrodes. The photograph of the completed varactor device is
shown in Figure 3.11b. A typical device measurement is shown in Figure 3.12 as a
function of frequency at different bias voltages. The details of the characterization
efforts will be given in Chapter 4.
The layout for two capacitors in series required a very detailed fabrication
process and had serious processing drawbacks. An oxide/nitride layer was needed
to etch the bottom electrode and to define the active areas on BST films. The e-
beam evaporated oxide limits the maximum base electrode thickness. This in turn
will set the device quality factor. It was also found that the adhesion of Pt to the
47
Top View
w
3w
w w w
w = lithographic design rule
l
Side View
Pt base
SiO2 SiO2
Substrate
SiNSiN
Ti/Au Ti/Au
Ti/Pt/AuTi/Pt/AuBST
BST Device
(a) (b)
Figure 3.11a-b: Device schematic and completed picture of initial parallel plate capacitors that had two capacitors in series configuration.
0
10
20
30
40
50
0 1 1010 2 1010 3 1010 4 1010
Qua
lity
Fact
or
Frequency(Hz)
Device
BST 30/70
6 10-14
8 10-14
1 10-13
1.2 10-13
1.4 10-13
1.6 10-13
0 1 1010 2 1010 3 1010 4 1010
Cap
acita
nce(
F)
Frequency(Hz)
0V
10V
20V
Figure 3.12: Typical device measurement for BST varactors with two capacitors in series configuration.
48
oxide layer was poor and Ti layer was required as an adhesion promoter. During
the Pt patterning, the top electrodes were found to peel off as a result of physical
sputtering. It has been reported that annealing after the processing is completed will
normally recover the thin film properties and processing induced damages. The Ti
layer made such an annealing step impossible since the films were shorted when
annealed as a result of titanium diffusion into the film. Also the parasitic capacitors
due to oxide/nitride layers had also high loss tangents degrading the device
performance. It was hard to extract the loss contributions from each material layer.
The fabrication process involved many steps, increasing the device cost and
lowering the yield. Moreover, having two series capacitor effectively doubled the
bias voltage for the same film thickness. A new device topology has been studied to
implement parallel plate capacitors that will potentially solve these problems [2].
3.4 New BST Varactor Layout for Optimized Performance
The most serious problems with two capacitors in series configuration were
the fabrication complexity and the bottom electron patterning. We proposed a new
process method where BST films were grown directly on pre-patterned bottom
electrode. Since the films are grown on pre-patterned templates, this eliminated the
need to etch Pt after BST growth. We also implemented a single device
configuration instead of two in series to reduce the fabrication complexity. A
suggested device schematic is shown in Figure 3.13a-b. It looks similar to Schottky
diodes and oxide/nitride layer on the BST varactors is eliminated for simple
49
fabrication. The device layout utilizes a single parallel plate capacitor and
minimizes conductor losses in the base electrode. A metal layer crossing over the
BST film creates the top electrode defining the BST varactor area.
Top Electrode
BST
Bottom Electrode
BST
Top Electrode
Bottom Electrode Substrate
Side View
Thick Metal
Figure 3.13a-b The device schematics for the new single device BST varactors suitable
There are two different methods how the bottom electrode can be patterned
prior to BST film: etching the bottom electrode and e-beam evaporation followed
by lift-off patterning. A thick layer of oxide/nitride can be used to etch relatively
50
thick bottom electrodes. One advantage the etching method offers is the possibility
of processing the bottom electrodes grown epitaxially by sputtering at high
temperatures. However, etching the bottom electrode has the same drawbacks
mentioned in the earlier section. Another problem is that the oxide and nitride need
to be deposited on the bottom electrode prior to the BST film growth, possibly
contaminating or damaging the metal-BST interface. On the other hand, the e-beam
evaporation doesn’t have these complications. The simple liftoff technique enables
the base electrode thickness be increased as needed. The different materials that are
investigated as adhesion layer for the platinum bottom electrodes are titanium and
ZrO2. Titanium is chosen because it can be evaporated in an e-beam system at
UCSB and smooth BST films have been shown on it. The studies resulted in robust
electrode stacks on both glass and sapphire. The BST films grown on sapphire
demonstrated better film properties. That’s why our research efforts focused on pre-
patterned sapphire substrates for the BST film varactors.
The fabrication process is summarized in Figure 3.14 and the details are
given in Appendix A. The fabrication of BST varactors starts with e-beam
evaporation of the bottom electrodes followed by lift-off on sapphire substrate.
Ti/Au/Pt metals were used as the bottom electrode metals. Au metal was
incorporated into the base electrode to increase the conductivity and reduce the
ohmic losses. Typically the metal thicknesses were 50Å/1000Å/1000 Å, for the
Ti/Pt/Au, respectively. The BST films were grown on pre-patterned templates. In
our studies, the BST films were grown using rf magnetron sputtering at UCSB. The
51
(b)
BST Film(280 nm)
ContactMetal
ContactMetal
(e)
(c)
Bottom ElectrodeTi/Au/Pt50A/100nm/100nm
(d)
BottomElectrode
Top ElectrodeBST Film
BST Varactor
Sapphire Substrate
Top ElectrodePt/Au
(100nm/500nm)
BST Film
(a)
Electrode patterning withe-beam evaporation &liftoff
BST film deposition
Top electrode metall iza-tion & liftoff
BST etch using HF
Thick contact metalliza-tion & liftoff(Ti/Au 10nm/1.2um)
Figure 3.14: The fabrication of Schottky-like BST ‘finger’ varactors
52
film stoichiometry was optimized for tunability and microwave loss performance.
Pt/Au top electrodes (100nm/500nm) were evaporated on the BST film and
patterned by lift-off. It is important to note that the top electrode process
immediately follows the BST film growth reducing process damage or
contamination. This is followed by BST etch in buffered HF. The HF removes the
field BST and opens the areas on the bottom electrode for the contact metal.
Thick Metal
Bottom Electrode
BST capacitor
Figure 3.15: Completed device picture of BST capacitor that uses prepatterned bottom electrode. Thick metal contacts to the bottom electrode allow reduced resistance in the
base.
A thick layer of Ti/Au (100/1.2 um) metals were evaporated for contacting the top
and bottom electrodes. The thick contact metal is brought to the top electrodes as
close as possible to lower the base resistance. A picture of a completed parallel
53
plate capacitor is provided in Figure 3.15. As can be seen from the device picture,
the series resistance associated with the BST capacitor has contributions from both
the base and top electrodes. The characterization and device modeling efforts will
be discussed in length in Chapter 4.
54
References
[1] R. York, A. Nagra, E. Erker, T. Taylor, P. Periaswamy, J. Speck, S.
Streiffer, and O. Auciello, "Microwave integrated circuits using thin-film
BST," 2001.
[2] B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, and R. A. York, "A new
high performance phase shifter using Ba/sub x/Sr/sub 1-x/TiO/sub 3/ thin
films," IEEE Microwave and Wireless Components Letters, vol. 12, pp. 237-9,
2002.
[3] B. Acikel, L. Yu, A. S. Nagra, T. R. Taylor, P. J. Hansen, J. S. Speck, and
R. A. York, "Phase shifters using (Ba,Sr)TiO/sub 3/ thin films on sapphire and
glass substrates," 2001.
[4] B. E. Gnade, S. R. Summerfelt, and D. Crenshaw, "Processing and device
issues of high permittivity materials for DRAMs," 1995.
[5] P. C. Fazan, "Trends in the development of ULSI DRAM capacitors,"
1994.
[6] D. E. Kotecki, J. D. Baniecki, H. Shen, R. B. Laibowitz, K. L. Saenger, J.
J. Lian, T. M. Shaw, S. D. Athavale, C. Cabral, Jr., P. R. Duncombe, M.
Gutsche, G. Kunkel, Y. J. Park, Y. Y. Wang, and R. Wise, "(Ba,Sr)TiO/sub 3/
dielectrics for future stacked capacitor DRAM," IBM Journal of Research and
Development, vol. 43, pp. 367-82, 1999.
[7] T. Taylor. (Personal Communication)
55
[8] E. G. Erker, A. S. Nagra, L. Yu, P. Periaswamy, T. R. Taylor, J. Speck,
and R. A. York, "Monolithic Ka-band phase shifter using voltage tunable
BaSrTiO/sub 3/ parallel plate capacitors," IEEE Microwave and Guided Wave
Letters, vol. 10, pp. 10-12, 2000.
56
Chapter 4
BST Varactors: Characterization & Modeling
This chapter deals with characterization and modeling of BST varactors.
BST varactors with varying sizes were to measure device properties from 100 Hz to
40 GHz. The low frequency measurements enable the characterization of the thin
film material properties without detailed fabrication process. The high frequency
measurements are important for accurate estimation of the circuit performance.
The challenges involving parameter extraction at microwave frequencies are
discussed. The frequency measurements and the device modeling are presented.
4.1 Device Characterization
Large value capacitors are fabricated to characterize dielectric properties of
BST films at low frequencies. Two different instruments have been utilized to do
low frequency measurements: Keithley 590 C-V Analyzer and Agilent 4294
Impedance Analyzer. The Keithley 590 measures capacitance versus voltage or
capacitance versus time characteristics of the devices. 100 kHz or 1 MHz test
frequencies are available. It provides very fast characterization of capacitor
properties and internal source voltage source enables 20± V bias. The setup has
been calibrated before each measurement and the stray capacitance in the cables
has been subtracted from the measurement results automatically after the
57
calibration. A computer controlling the instrument with GPIB interface has been
used to store the conductance, capacitance and voltage values. Stair and dual stair
measurements were done to see if the BST capacitors have shown any hysteresis.
The measurements were done on two large capacitors connected in series by
applying bias between the top electrodes or on a single capacitor between the top
and bottom electrode. 1 MHz standard C-V measurements are fitted in to an
equivalent parallel circuit and the device capacitor and quality factor are extracted.
Agilent 4294 Impedance analyzer enables impedance measurements
between 40 Hz to 110 MHz. A wide range of impedances can be measured, from
3m Ohm to 500M Ohm. Impedance measurements can be done as a function of
frequency at different bias points or as a function of bias at a single frequency.
High DC internal bias range ( 40± V) is useful for the characterization of thicker
films with high breakdown voltages. BST varactors that had coplanar waveguide
(CPW) electrode structures are fabricated to measure frequency dependent
dielectric properties. The schematic of the electrode structures is shown in Figure
4.1. The signal electrode of CPW line sits on the BST film and ground electrodes
are deposited directly on the bottom electrode. BST varactors with differing lengths
and ground-signal distances were characterized. The fabrication process involves
two steps. The BST film is grown on blanket (or prepatterned) platinum electrode
followed by BST etch using buffered HF. Finally, Pt/Au electrodes in the shape of
coplanar waveguides are evaporated. CPW structures can be used at high frequency
measurements and the distributed nature of the circuits
58
Substrate
BST
Contact electrodes Pt bottom electrode
Figure 4.1: The BST varactors used for the capacitance measurements as a function of frequency. The BST varactor is formed under the signal port of the coplanar waveguide
is accounted accurately. The details of the circuit model for the devices will be
discussed in the next chapter. A typical capacitance-frequency curve is shown in
45
50
55
60
65
0
50
100
150
200
1000 104 105 106 107 108
Capacitance (pF)
Q
Cap
acita
nce
(pF)
Q-factor
Frequency (Hz)
Figure 4.2: The capacitance and the quality factor characteristics of a typical BST varactor.
Figure 4.2. As seen, there is small dispersion in the capacitance characteristic as
described in Chapter 2. Some noise in the low frequency data is observed. The
59
quality factor of the device, at the beginning, increases with the frequency and
peaks between 1-10 MHz. Then, the Q factor decreases sharply as the frequency is
increased beyond 10 MHz. The high frequency loss is dominated by the conductor
losses due to base electrode.
50
60
70
80
90
100
110
120
1 10 3 10 10 3 100 10 3 1 10 6 10 10 6 100 10 6
Qua
lity
Fact
or
Frequency (Hz)
100 nm Pt
200 nm Pt Total Device Q
Figure 4.3: Q factors for two samples with different bottom electrode thicknesses that had the same BST film growth. The quality factor decreases sharply for the sample with the
thinner bottom electrode.
The quality factor (Q-factor) is used to characterize the losses in lumped
circuit elements. Quality factor can be defined as the ratio of stored energy to the
average energy dissipated in the system per cycle. For any type of passive circuits
represented by admittance or impedance this relation can be defined accordingly.
60
For an admittance (impedance) circuit, the quality factor is defined by Im Re
YQY
=
(or similarly Im Re
ZQZ
= for an impedance circuit)
To characterize different components of the losses, the following
experiment was carried out. BST films were simultaneously grown on two samples
that had different bottom electrode metal thicknesses. First, 1000 Å Pt was grown
on a sapphire substrate in the sputtering chamber. Then, the growth was interrupted
and a second sample was put into the system and an extra 1000 Å Pt was grown on
both samples simultaneously followed by 1000 Å 0.5 0.5 3Ba Sr TiO BST film growth.
At the end, the first sample had an electrode thickness twice the thickness of the
second sample. It was assumed that since the BST films were grown at the same
time, the difference in the device properties is directly due to the difference in the
base electrode thickness. The results from low frequency device measurements are
shown in Figure 4.3. As can be seen, the total device quality decreases faster for
thinner Pt electrode at higher frequencies. Intrinsic BST film losses can be
extracted from the previous measurement results. The total device quality factor for
the samples can be approximated as
1 1
2 2
1 1 1
1 1 1tot BST pt
tot BST pt
Q Q Q
Q Q Q
= +
= + (4.1)
61
where 1totQ is the total device quality factor, BSTQ is the intrinsic quality factor of
the BST film excluding conductor losses due electrodes and 1ptQ indicates ohmic
losses due the base electrode. The similar expressions follow also for the second
sample. We note that ptQ can be written as
1Pt
s
QR Cω
= (4.2)
where ω indicates the frequency, sR is the series resistance component due to the
base electrode and C is the BST capacitance value. sR is inversely proportional to
the base electrode thickness as a first approximation. It is clear from equation (4.2)
that the quality factor is proportional to the base electrode thickness and the higher
quality factors obtained by using thicker base electrode. Rewriting the results in to
(4.1), and subtracting two equations,
1 2 1 1
1 1 1 1
tot tot Pt PtQ Q Q nQ− = − (4.3)
where n is the ratio of Pt base electrode thickness. Intrinsic BST film quality factor
can be found using (4.1) and (4.3). The Figure 4.4 shows the extracted BST film
quality. The BST film shows a relatively constant quality factor up to 100 MHz
even though there is some dispersion at the high frequencies because of the
measurement and calibration limitations.
62
50
60
70
80
90
100
110
120
1 106 10 106 100 106
BST/ Pt/ Sapphire
Qua
lity
Fact
or
Frequency (Hz)
Intrinsic BST film Quality factor
Total Device Quality factor
Figure 4.4: The extracted quality factor for the BST film and the device.
4.2. Low Frequency Device Modeling
The different loss contributions are modeled in an equivalent circuit shown
in Figure 4.5. In this model Rs indicates the ohmic losses caused due to contact
electrodes –top and bottom. The leakage due to free and mobile charges is indicated
by GDC while Gac indicates dielectric losses in the film. C represents the intrinsic
BST capacitor associated with this dielectric loss. The total device quality factor
can be approximated by
1 1 1 1
total leakage BST PtQ Q Q Q= + + (4.4)
Each loss contribution becomes dominant in different frequency bands and
as a result simpler circuits can be used to approximate the complete circuit behavior
63
at different frequency intervals. These circuits are shown in Figure 4.6 for
corresponding bands and their quality factors are given by
1; ; ω ωω
= = =leakage BST PtDC AC
C CQ Q QG G RC
(4.5)
C
Rs
GacGDC
BST Film
Figure 4.5: The equivalent circuit loss model for the BST varactors.
The BST varactors with coplanar waveguide electrodes shown in Figure 1
can be described as a distributed circuit. A good model for the device can be
extracted using the device schematic shown in Figure 4.7a with the equivalent
circuit elements. topr is the resistance due to top Pt/Au signal electrode where
br represents the contribution from the base electrode. The contribution due to CPW
ground electrodes on the bottom electrode is represented by sider where BSTc is the
capacitance of BST film per unit length. The model can be further simplified as in
64
CGac
Rs
C
GDC C
Low Frequency Intermediate Frequency
High Frequency
Figure 4.6: The simplified equivalent circuits that dominates the behavior in the corresponding frequency range.
Figure 4.7b where sr is the series impedance associated with a transmission line
and BSTc and pr indicate the parallel conductance per unit length. From Figure
4.7a-b
/ 2
/ 2= +
=s top side
p b
r r rr r
(4.6)
The factor of 12 arises because there are two components connected in
parallel. To find the characteristic impedance and propagation constant of test
structure, the general transmission line formulas are used. For a transmission line,
the propagation constant and the characteristic impedance are given by
0
γ =
=
zy
zZy
(4.7)
where z is the series impedance and y is the parallel admittance per unit length.
Putting equation (4.6) into (4.7)
65
1
s BST
p BST
jwr cjwr c
γ =+
(4.8)
0
1 p BSTs
BST
jwr cZ r
jwc+
= (4.9)
topr
sider br brsider
BSTc
Figure 4.7a: The distributed circuit model for the BST varactors with CPW electrodes.
pr
BSTcsr
L
Figure 4.7b: The simplified equivalent version of the distributed circuit.
66
For a transmission line with a load LZ , the input impedance at a distance L
from the load is given by
00
0
tanhtanh
Lin
L
Z Z LZ ZZ Z L
γγ
+=+
(4.10)
For an open circuited transmission line, ( LZ → ∞ ) the input impedance is
approximated by Eqn. (4.11)
0 01coth ( ) 1
3inLZ Z L Z L
Lγγ γ
γ= ≈ + (4.11)
Putting Eqn. (4.8) and (4.9) into (4.11), the result becomes
13
p st
BST
r r LZL jwc L
≈ + + (4.12)
In this expression, the first term represents the loss due to the base electrode
and it is inversely proportional with L and the second term signifies the loss due to
the top electrode and increases with L, which are intuitively expected.
The base electrode resistance can be found using the device physical layout.
A device cross section is shown in Figure 4.8. Schottky diodes have very similar
device geometry except the capacitor is formed by N − semiconductor region
whereas here BST film forms the capacitor area. The spreading resistance under the
BST capacitor is also modeled as a distributed circuit. The base resistance is given
213 6
b gap spreading
b b bb
b b b
r r r
g w wr gt t t
ρ ρ ρ= +
= + = +
(4.13)
67
where bρ is the base electrode conductivity, bt is the base electrode thickness, g is
the distance between the top and side contact, w is the top contact width. 13
term
arises because of the spreading nature of the current under BST film.
Similarly resistance due to top and side contacts can be calculated.
Assuming the same width for both contacts
toptop
top
sideside
side
rt W
rt W
ρ
ρ
=
= (4.14)
where subscript indicates the contact name. If more than one metal layer has been
utilized for contacts the effective sheet resistance and thicknesses can be found in a
similar way.
/ 2w
g
Spreading resistance under top contact
spreadingrgapr
Figure 4.8: The series resistance due to base electrode in the BST varactor.
68
Putting the expressions for sr and pr back in to the equation (4.11) we obtain
1 2
1 2 2 1
12 6 2
bs
b
W LR gt L W t tρ ρ ρ
ρ ρ = + + +
(4.15)
We note that
0 r
d
dAC
WLCt
tGWL
ε ε
σ
=
= (4.16)
where σ indicates the film conductance, and dt is the film thickness. The shorted
device measurements are made in a similar way to characterize the losses in the
base electrodes. CPW contact pads are put directly on base electrode after etching
BST films.
0.001 0.01 0.1 1 10 100Frequency , MHz
30
50
70
100
150
200
totQ
Figure 4.9: The comparison of the measurement with the BST model
69
Figure 4.9 shows the comparison between the measurements and the model
for the low frequency structures. It was assumed that the BST varactors had a
constant quality factor in the measurement range. The model correctly predicts the
device behavior in the whole frequency range. There is some discrepancy in the
high frequency end of the measurement, which is caused by either calibration errors
or some intrinsic losses in the film or contact resistance, which were not included in
the model.
4.3 Characterization of BST Varactors in Microwave Regime
In this section, the high frequency measurement results are presented for
both type of BST varactors implemented at UCSB that are covered in detail in
Chapter 2, but the modeling details will be given only for the Schottky-like BST
varactors. The high frequency characterization was done by recording 1-port s-
parameters for different integrated BST varactors at different applied bias levels.
The measurements were done on a Cascade Microtech probe station using ACP-40
CPW probes by Cascade and 40A GSG Picoprobes by GGB Industries. A HP
8722D network analyzer was used for s-parameter measurements between 50 MHz
to 40 GHz.
There were two critical steps required to accurately extract values for the
series resistance and BST capacitance. Because the series resistance was so small,
the measured s-parameters were very near the edge of the Smith Chart, so a very
accurate calibration is required otherwise even very small ripples in the
70
measurements would result in the s parameters outside the Smith Chart which
means the devices show a flawed gain. The second critical step is the accurate
estimation of the large pad parasitics that are used to contact BST varactors. The
capacitance due to large pads can be comparable to small value BST capacitors that
are typically employed in microwave frequencies and must be correctly embedded
from the real device measurements.
The calibration technique that was used for this work was the line-reflect-
match (LRM) method that was developed by Cascade Microtech [1]. This method
is a hybrid of two measurements developed earlier, namely short-open-load-
through (SOLT) and through-reflect-line (TRL). In SOLT method, three defined
standards are measured on two ports separately. A 50 Ω load and a short circuit are
measured and raised probes are used as open standards. Measuring the open probes
in the air, which has a dielectric constant lower than the calibration substrate,
results in a negative capacitance, which is defined to account for the difference.
SOLT calibration technique works comparatively well for low Q devices up to 20
GHz, but measured 1-port s-parameters go outside the chart between 30-40 GHz.
TRL method doesn’t suffer from the drawbacks of SOLT method. In this
calibration method, two different transmission lines of lengths differing by a
quarter wavelength are measured followed by the measurement of a high reflection
standard. One drawback of the TRL method is the requirement of having exactly 50
Ω line, which means the calibration degrades at high frequencies. Another problem
is the fact that the lowest frequency range is set by the longest through line length.
71
As a result to have calibration over wide frequencies, it is necessary to have
through lines with different lengths each one covering a certain bandwidth.
Calibrations below 1 GHz require very long transmission lines, which may become
impractical. LRM method uses a very short through line, typically 1 ps, is
measured thus eliminating dispersion problems. The reflection standard must be a
high reflection standard but doesn’t need to be precisely defined. 50 Ω load is used
as a calibration standard, which is treated as an infinitely long delay line. This
overcomes the issues related to dispersion problem and long through lines.
The equivalent circuit for microwave measurement setup is shown in Figure
4.10. PC , PL , and PR represent the parasitic capacitance, inductance and resistance
due to contact pads, respectively. It is important to accurately account for the
parasitics due to the pads in the measurements after calibration is performed. This
Lp
CPW Pad Capacitance
Cp
CPW Pad Inductance
CPW PadResistance
Rp
DUT
CPW parasiticsRF Device Model
Figure 4.10: Equivalent circuit for microwave frequency measurements with pad parasitics
72
is usually done by having some calibration pads such as open and shorted
structures on the wafer [2, 3]. Open structures omit the device under test on the
mask layout and leave the pads open. Shorted pads are fabricated by connecting
signal and ground planes at where the device would be located.
The equivalent lumped element circuit for open and shorted cases area also
shown in Figure 4.1. In the open circuited pads, measured admittance is given by
ω=padop PY j C (4.17)
which shows that the imaginary part of the input admittance increases linearly with
frequency. The data for an open pad is shown in Figure 4.12a. A value of 32 fF for
PC fits the data perfectly in the frequency range. The shorted pads will have an
admittance given by
1ωω
= ++padsh P
P P
Y j CR j L
(4.18)
The inductance of the pads is determined by subtracting open circuit
capacitance PC value from short-circuited measurement. The resistance due to pads
is very small. The data for the short-circuited pads is shown in Figure 4.12b after
PC has been removed from the expression. PL inductance value is modeled to be
82 pH and in good agreement with the data.
73
CPW “short”CPW “Open”
Cp Cp
Lp Rp
Figure 4.11: Open and short-circuited pad measurements yield the relevant parasitics
It is more advantageous to use admittance parameters than impedance to
extract the BST varactor properties. Using the series RC model shown in Figure
4.6,
BST S
BST
SBST
S S
jwCw C R jwCw C R w C R
Z R
Y ++ +
= +
=2 2
2 2 2 2 2 2
1
1 1
(4.19)
At frequencies whereS
w CR1 the expression reduces to
BST S jwCY w C R= +2 2 (4.20)
The varactor capacitance is extracted by taking the imaginary part of the
admittance expression, which is linear with the frequency with a slope of C . Eqn.
(4.20) shows that the conductance expression varies as the square of the frequency.
The measured data together with extracted device parameters are shown in Figure
4.12 a-c.
Near the edge of Smith Chart, the constant resistance circles are very
closely spaced and it is difficult to extract the series SR resistance value. That’s why
74
it is common practice to measure the devices with higher resistances and extract the
losses for small devices using scaling rules. BST varactors with typical values of
0.15-2 pF were fabricated at the same time and measured for characterization.
0
1
2
3
4
5
0 5 10 15 20
Y11measuredY11modeled
ImY
11(
mS)
Frequency (GHz)
Open Pad
0
2
4
6
8
10
0 5 10 15 20
Z11 measuredZ11modeled
ImZ
11(
Ohm
)Frequency(GHz)
Shorted Pad
(a) (b)
0
2
4
6
8
10
0 5 10 15 20
MeasuredModeled
Real
Y11
(mS)
Frequency(GHz)
DUT
(c)
Figure 4.12a-c: The comparison of the high frequency measurements and the models.
Figure 4.13 shows the extracted capacitance and the device Q factors for
some discrete BST varactors with two capacitors in series configuration as a
function of frequency. There is some dispersion at the low frequencies but the
75
capacitance is almost constant at frequencies up to 40 GHz. The device Q factor is
relatively low at the low end of the spectrum possible indication of losses in the
BST film or oxide/nitride combinations.
0
10
20
30
40
50
0 1 1010 2 1010 3 1010 4 1010
Qua
lity
Fact
or
Frequency(Hz)
Device
BST 30/70
6 10-14
8 10-14
1 10-13
1.2 10-13
1.4 10-13
1.6 10-13
0 1 1010 2 1010 3 1010 4 1010
Cap
acita
nce(
F)
Frequency(Hz)
0V
10V
20V
Figure 4.13: Device measurements for typical BST varactors with two capacitors in series configuration.
4.4 Device Modeling for New Schottky type BST Varactors
In this section, the characterization, modeling and optimization of the new
Schottky type BST varactors will be considered. This structure makes use of BST
films grown on a prepatterned base electrode, with a top contact defining the active
capacitance area. Thin-film BST has a high intrinsic capacitance density, which
leads to small electrode areas for the realization of typical capacitance values for
RF circuit design. This in turn can lead to high ohmic losses and high current
76
densities, hence the choice of materials and geometrical design can have a strong
influence over the device Q-factor and power handling.
Figure 4.14 shows the capacitance and the device quality factor
measurements from some discrete Schottky-like BST varactors. The devices had
1.5 um wide varactor fingers in the mask layout. As seen from Figure 4.14, the
capacitance nicely scales with the different device lengths and doesn’t show
noticeable dispersion up to 10 GHz. Compared to Figure 4.13, the varactors have
higher Q factors especially at lower frequencies. The quality factor shows 1/f type
of frequency dependency, which is indicative of conductor loss mechanisms at the
high frequencies. It is important to note that all the capacitors have the same BST
film growth.
If the device performance were limited by the intrinsic BST thin film losses
at microwave frequencies, one would expect that the total device Q factor would
not change for the devices with different physical layouts. Figure 4.14 indicates
that that the film Q values are high enough that layout dependency is observed.
In Figure 4.15, this dependency is shown in a different format as a function
of capacitance for some BST varactors with the different finger widths and lengths.
The devices are initially characterized as a function of frequency and the quality
factor and capacitance values are extracted from the measurements. The figure is
obtained by plotting the total device quality factors as a function of capacitors at 10
GHz. It is clear from Figure 4.15 that for a given capacitor value there is an
77
optimum design that will give the maximum device Q factor at the operating
frequency.
0
0.1
0.2
0.3
0.4
0.5
0.6
0 2 4 6 8 10
1.5umx5um1.5umx10um1.5umx15um1.5umx20um
Cap
(pF)
Frequency(GHz)
0
50
100
150
200
0 2 4 6 8 10
1.5umx5um1.5umx10um1.5umx15um1.5umx20um
Qde
vice
Frequency(GHz)
Figure 4.14: The capacitance and quality factor measurements for BST finger devices as a function of frequency.
15
20
25
30
35
40
0 0.5 1 1.5 2
Width 1.5um Gap=3umWidth 2um Gap=3umWidth 3um Gap=3umWidth 6um Gap=3um
Dev
ice
Q
Capacitance ( pF)
Figure 4.15: The quality factor of the devices with different finger widths and lengths.
78
A simplified device layout shown in Figure 4.16 was used to study the
ohmic losses in the conductors with critical device dimensions labeled All the
metal layers are modeled with an associated sheet resistance (Ohms per square),
and the dielectric film with an associated capacitance density (Farads per meter).
The thick metal consists of the Ti/Au metallization layer for CPW line, and
is typically 1-1.5 µm thick. This layer typically makes a negligible contribution to
the overall ohmic loss in the varactor equivalent circuit. Thick metal contacts to
the base electrode on each side of the top contact allows for reduced resistance. The
technology specifications are given with the following area density quantities.
2
2
base electrode sheet resistance [ /square] thin metal sheet resistance [ /square] BST capacitance density [F/m ]
BST conductance density [S/m ]
b
t
d
d
rrcg
= Ω= Ω
=
=
Figure 4.16: The critical dimensions of new device layout. The minimum feature is set by lithographic restrictions.
79
The important dimensions are denoted as follows: W is the finger width, L
is the finger length on the bottom electrode which defines the varactor area, d is the
distance between the thick metal and the bottom electrode edge and g is the
distance between the finger and the thick metal edge that lies on the bottom
electrode. The BST film boundary doesn’t have a direct consequence in the ohmic
loss calculations.
The structure is modeled as a distributed circuit similar to the low frequency
CPW pads. A good first order model suitable for optimization studies are shown in
Figure 4.17 with different resistance components from top and bottom electrode.
With reference to the dimensions in Figure 4.16, the “access” resistance arising
from the top contact is given by
=access tdR rW
(4.21)
The top contact along the capacitor surface contributes
3
=top tLR rW
(4.22)
where the factor of 1/3 comes from the distributed nature of the contact. The base
electrode contributes a resistance, which includes contributions from the two sides
and the end of the device, and can be approximated by
||2 2
≈ ≈+
sidebase end b
R gR R rL W
(4.23)
80
Figure 4.17: The schematic showing the different series resistance components for BST varactor due to electrodes
So, to first order, the base electrode contribution depends on the device periphery
whereas the top contact resistance depends on aspect ratio, as intuitively expected.
Denoting the admittance density of the BST film as d d dy g j cω= + , the
total impedance is written as
13 2
≈ + + + + t
in bd
r L gZ d rW L W y WL
Rs
(4.24)
and the equivalent series resistance for the device is identified. There are some
second-order corrections to the series resistance that can be made due to spreading
resistance in the base electrode directly under the top contact.
One must choose the optimum capacitor layout for a desired capacitor value
such that the series resistance is minimized. For a certain capacitor size, the product
of the width and length of the top finger contact gives its area
81
= AWL
Substituting this into (4.24) gives
23 2 = + + +
t bs
r L r gLLR dA L A
(4.25)
It is seen from Eqn (4.25) that choosing the smallest possible length L
minimizes the series resistance for a given capacitor area. Eqn. (4.25) is plotted in
Figure 4.18, which shows the relation between the series resistance and the length
of the capacitor. The series resistance term goes to zero as the length L term
becomes smaller. The limit on length L will be set by the lithography employed in
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
Res
ista
nce(
Ohm
)
Length(um)
g=3µmcapsize=.4pF
Figure 4.18: The dependence of the series resistance to the device length. The shorter device length reduces the series resistance term.
the fabrication technology. If we denote the smallest dimension by λ , then L λ=
gives the optimum Q. The smallest possible capacitor that can be realized will have
82
an area 2λ and hence a minimum achievable capacitance of 2min dC c λ= where dc
is the capacitance density. Considering only electrode losses ( 0dg = ), the cutoff
frequency for the device is given by
12π
=cs d
fR c A
(4.26)
The cutoff frequency is plotted in Figure 4.19 as a function of capacitance.
This figure illustrates an important fact: in order to realize a capacitor with the
highest possible Q-factor (lowest series resistance), it may be advantageous to use a
parallel combination of two or more smaller capacitors (the Q-factor of two
identical capacitors in parallel is the same as the individual capacitors).
0 0.2 0.4 0.6 0.8 1Capacitance , pF
1000
2000
3000
4000
5000
ffotuCycneuqerF,
zHG
Figure 4.19: The cutoff frequency of the modeled BST capacitors.
This is due to the periphery-dependent base-electrode contribution to
resistance.
83
To test the accuracy of the models, the discrete BST varactors with varying
finger widths and lengths are fabricated and measured. The finger widths were
varied from 1.5 µm to 6 µm and the device lengths were between 5 µm and 20 µm.
The series resistance expression given in equation (4.25) was used to calculate the
ohmic losses in the device.
0
20
40
60
80
100
120
140
0 5 109 1 1010 1.5 1010 2 1010
Qua
lity
Fact
or
Frequency(GHz)
Qmetal
(tanδ=0)
Qtot
(tanδ=0.01)
Qtot
(tanδ=0.02)
Measured
fingersize=1.5x5
0
20
40
60
80
100
120
140
0 5 109 1 1010 1.5 1010 2 1010
Qua
lity
Fact
or
Frequency(GHz)
Qmetal
(tanδ=0)
Qtot
(tanδ=0.01)
Qtot
(tanδ=0.02)
Measured
size=3x10
0
20
40
60
80
100
120
140
0 5 109 1 1010 1.5 1010 2 1010
Qua
lity
Fact
or
Frequency(GHz)
Qmetal
(tanδ=0)
Qtot
(tanδ=0.01)
Qtot
(tanδ=0.02)
Measured size=6x5
0
20
40
60
80
100
120
140
0 5 109 1 1010 1.5 1010 2 1010
Qua
lity
Fact
or
Frequency(GHz)
Qmetal
(tanδ=0)
Qtot
(tanδ=0.01)
Qtot
(tanδ=0.02)
Measured
size=6x20
Figure 4.20a-d: Comparison of the measured and the simulated results for BST varactors.
Figure 4.20a-d show the comparison between the measured (markers) and
simulated (dashed-lines) device performances as a function of frequency. The total
circuit loss was simulated for three different loss tangents (tanδΒST=0, 0.01 and
84
0.02). The total circuit loss for tanδ=0 (infinite QBST) case is denoted as Qmetal since
all the loss is due to conductors. The actual finger widths and lengths were
estimated based on the discrete BST capacitance measurements. Simulations have
shown that the base electrode resistivity is larger than the calculated resistances
using bulk values or DC measurements.
The devices show high device-Q factors (100-150) at low frequencies
(below 2 GHz) and the Q factor decreases and approaches Qtot(tanδ=50) curve
asymptotically. Above 5-7 GHz, the fit between the measured and the simulated
results is excellent for all the devices with different sizes. The measured data
mostly lies between tanδ=0.02 and tanδ=0.01. From the plots it is interpreted that
the BST Q-factor shows a frequency dependent decrease for frequencies up to 5-7
GHz. Both BST film losses and the ohmic losses are very important in the overall
device quality factor. At high frequencies, Qtot follows the Qmetal. Growing high
quality BST material will further improve the total device performance, especially
at the low GHz regime. The conductor losses, which become dominant at high
frequencies, should be minimized to increase the device performance.
85
References
[1] S. Lautzenhiser, A. Davidson, and K. Jones, "Improve accuracy of
on-wafer tests via LRM calibration," Microwaves and RF, vol. January,
1990.
[2] K. Ikuta, Y. Umeda, and Y. Ishii, "Measurement of high-frequency
dielectric characteristics in the mm-wave band for dielectric thin films on
semiconductor substrates," Japanese Journal of Applied Physics, Part 2
(Letters), vol. 34, pp. L1211-13, 1995.
[3] S. T. Allen, "Schottky Diode Integrated Circuits for Sub-Millimeter
Wave Applications," University of California, Santa Barbara, 1994.
86
Chapter 5
Low Loss Analog Phase Shifters using BST
Technology
In this chapter, a discussion of the potential of BST varactor loaded
transmission lines for microwave control applications is presented. The basic
principle of operation of the distributed phase shifter circuits and the relevant
design equations are summarized [1].
Low loss analog phase shifters were designed and fabricated at UCSB on
different substrates. The early work on the phase shifters utilized the BST varactors
that were implemented by etching bottom electrodes on sapphire and glass
substrates [2]. Our recent research focused on the new Schottky-like ‘finger’ BST
varactor devices described in Chapter 3. A brief description of the monolithic
fabrication process is presented, followed by RF measurements on the fabricated
circuits. A new design using BST finger varactors was capable of producing 0-250°
phase shift at 10 GHz with a maximum insertion loss of only 3.1 dB and return loss
lower than –10 dB over all phase states at room temperature. The circuit achieved
the best figure of merit reported in the literature for the BST phase shifters. This
circuit has many desirable features including one control voltage, very low DC
87
power since the varactors draw extremely low currents and fine resolution in
controlling the phase shift resulting in more accurate beam control in phased arrays.
A different phase shifter designed at Hughes Research Lab (HRL), which
provides improved return loss over a desired frequency band, has also been
fabricated at UCSB using BST varactors. The results from both circuit
measurements are compared with Mathematica and HP ADS simulations.
5.1 BST Thin Film Phase Shifters
Low loss and low cost microwave phase shifters are required to improve
performance and reduce the cost of phase arrays to ensure widespread application.
Therefore, BST thin films have been investigated as a potential low cost voltage
tunable element for implementing phase shifter circuits [3]. In these circuits, the
BST either forms a fraction of the substrate or the entire microwave substrate, on
which the conductors are deposited (thick films/bulk crystals) [3, 4]. In contrast,
our approach relies on discrete, vertical BST capacitors periodically loading a
transmission line. Varactor loaded transmission lines using GaAs Schottky diodes
optimized for low insertion losses have already been reported [1]. When designed
correctly [5, 6] this structure behaves like a synthetic transmission line whose phase
velocity can be controlled by changing the value of the external loading capacitors.
The BST parallel plate varactor technology utilizes the tunability of the BST film
effectively and requires much lower control voltages. The periodic loading allows
the structure to be optimized for good loss performance.
88
The design methodology used in this work has been adapted from an earlier
work at UCSB [1] where the GaAs Schottky varactors were used as the tunable
elements and the performance of the loaded distributed phase shifter circuit was
optimized for minimum insertion loss [6].
5.2 BST Varactor Loaded Phase Shifter: Overview
The BST varactor loaded phase shifter consists of a high-impedance Zi
transmission line periodically loaded with voltage variable capacitors Cvar with
spacing lsect. The properties of this synthetic transmission line such as its
characteristic impedance and phase velocity are voltage dependent, given in (5.1)-
(5.2) where Ll and Cl indicate inductance and capacitance per unit length, Zi and vi
are the impedance and phase velocity on the line, respectively. When bias voltage
is applied to the varactors, transmission line properties are altered resulting in a
differential phase shift. This is the essential principle behind the operation of the
phase shifter circuit.
( )
lL
l var sect
LZC C (V ) l
=+
(5.1)
( )phase
l l var sect
vL C C (V ) / l
=+
1 (5.2)
il l
i i i
ZL Cv Z v
= = 1 (5.2 a)
89
This periodic structure has a Bragg frequency [6] given by equation (5.3), where all
the parameters are per unit cell quantities.
( )Bragg
t t var
fL C Cπ
=+
1 (5.3)
There are two important design parameters for the circuit: the loading factor
“x” and the capacitance ratio “y” defined in Eqn. (5.4) [6]. The loading factor is
defined as the ratio of normalized maximum varactor capacitance to the
transmission line capacitance Cl, where “y” is the inverse ratio of maximum
varactor capacitance, which occurs at zero bias, to its minimum value. All the other
circuit parameters like line impedance, Bragg frequency, and differential phase
shift can be expressed in terms of these two parameters and the circuit performance
can be optimized for minimum loss.
max
min maxvar sectvar var
l
C / lx ; y C / CC
= = (5.4)
At any given frequency f, the maximum differential phase shift obtainable
from a single section is given by Eqn. (5.5) [1]. It indicates that increasing loading
factor (x) and/or the capacitance ratio (y) results in increased differential phase
shift.
( )sect
i
lf x xyv
δφ π= + − +2 1 1 (5.5)
When designing the loaded transmission line, the minimum Bragg
frequency must be kept much higher than the maximum operating frequency since
90
the reflections from the loaded sections add up in phase causing high insertion
losses at frequencies close to Braggf . The Bragg frequency and loading factor alone
determine the spacing lsect between the loading varactors. The loaded line
impedance is set to 50 Ω at zero bias since the lowest Braggf -maximum insertion-
loss occurs at this bias point.
The total insertion loss of the phase shifter has two components as given in
(5.6)-transmission line loss and varactor loss. The line losses are dependent on line
type and geometry and the varactor loss is largely dependent on the varactor
technology used. In this study, coplanar waveguide transmission lines (CPW) are
fabricated because shunt components can be connected easily. Even though
microstrip lines are more common in microwave industry, CPW lines are becoming
more popular since they don’t require the use of via holes, which are hard to
fabricate and at the same time introduce parasitic inductance.
( ) ( ) i
tot sect var cpw sect var L sect sect ic L
c maxs var
ZfL n L L n C Z n l Zf Z
fr C
π α
π
= + = +
=
2
12
(5.6)
For the circuit optimization, the losses in the BST varactors are modeled
using a simple series RC model similar to Schottky diode varactors. At high
frequencies, BST varactor losses are dominated by conductor losses due to the
series resistance (rs) in the electrodes, which validates RC model. The loss due to
this series resistance increases as the square of the frequency and is inversely
91
proportional to the small signal cutoff frequency fc (5.6). The conductor loss (Lcpw)
in the loaded CPW depends on the attenuation constant α(Zi), which is a function of
the dielectric constant of the substrate and the physical dimensions of CPW line.
5.3 Design of X-Band BST Varactor Loaded Phase Shifter
The design equations (5.1)-(5.6) were used to design an X-band phase
shifter on sapphire substrate that will provide 180° phase shift at 10 GHz. The
minimum Bragg frequency was chosen to be 17.5 GHz. When optimizing the loss
performance of the circuit, the following parameters were used in the simulations:
dielectric constant (εs) of 10.2 was used for sapphire substrate, CPW conductor
thickness (t) of 1.5 µm, BST varactors with cutoff frequency (fc) of 250 GHz (or
quality factor of 25) and capacitance ratio y = 0.4.
0
1
2
3
4
5
0 1 2 3 4 5
CircuitLossBST LossesCPWLoss
Inse
rtio
n Lo
ss (d
B) C
ompo
nent
s
Loading Factor(x) Figure 5.1: Total insertion loss as a function of loading factor for X-Band phase shifter.
92
The result of the loss analysis is plotted in Figure 5.1. Figure shows how the
total circuit loss varies with loading factor. It is important to note that large loading
factors are achieved not by increasing the value of the externally added variable
capacitor, but by decreasing the transmission line capacitance term. This involves
using high impedance lines. Note that the losses shown here are calculated at the
operating frequency, which is 10 GHz. As seen from the Figure 5.1, the CPW loss
increases rapidly with loading factor. When the loading factor is increased, the line
impedance required also increases as indicated in Equation (5.1). Higher impedance
lines tend to have higher resistive losses because the center conductor width is
narrower. The varactor loss, on the other hand, increases slowly with increase in
loading factor since the maximum varactor capacitance itself is as weak function of
loading factor for x>1 [1]. One must remember that the minimum insertion loss
point is determined by CPW line loss characteristics. CPW lines limit allowable
loading factors and higher loading factors can be potentially achieved by other
transmission line geometries without increased losses.
5.4 Circuit Fabrication
Varactor loaded delay lines were fabricated on both glass and sapphire
substrates using standard monolithic processing techniques. [2, 5] Two different
BST varactor technologies described in Chapter 3 were employed for the phase
shifters. Early efforts focused on K-Band phase shifters on glass and sapphire phase
substrates, where the two BST capacitors in series configuration were used. The
93
most recent work involved the Schottky-like finger devices as the loading
varactors. Only the results from these new phase shifters will be presented here.
An X-Band periodically loaded phase shifter was fabricated to provide
180°-phase shift at 10 GHz. The Bragg frequency for the periodically loaded line
was chosen to be 17.5 GHz. The loading BST capacitors have a zero bias design
capacitance of 260 fF. To preserve the symmetry, two 130 fF BST capacitors were
connected in parallel from the CPW center conductor to both ground planes. The
unloaded CPW has a line impedance of 72.97 ohm, which corresponds to a design
loading factor of x=1.7 that results in the minimum insertion loss. The line
consisted of the center conductor width (w) of 230 µm, ground to ground spacing
d=1040 µm, and unit cell length of lsect=1404 µm. Sapphire substrate thickness
was 325 µm.
The process flow for the phase shifter is depicted in Figure 5.2 and a brief
description is provided below. Detailed fabrication steps are included in Appendix
A. The first step in the fabrication process was the deposition of bottom electrode
metals (Ti/Au/Pt) on the sapphire substrate. The electrodes were patterned by lift-
off after e-beam evaporation. Next, low loss Ba0.2Sr0.8TiO3 films with moderately
high tunability were grown on pre-patterned sapphire templates. Pt/Au top
electrodes were evaporated followed by BST etch using buffered HF. Thick Au
metallization was done for CPW structures. Figure 5.3 shows the details of the
phase shifter circuit fabricated at UCSB. The circuit measurements and the
performance simulations will be discussed in detail in the following sections.
94
(b)
BST Film
CPW Signal CPW GroundCPW Ground
(e)
(c)
Bottom Electrodes
(d)
BottomElectrode
Top ElectrodeBST Film
BST Varactor
Sapphire Substrate
Top ElectrodesBST Film
(a)
Figure 5.2: The process flow diagram for the fabrication of the BST phase shifter circuits.
95
17.5 mm
3.5 mm
50 um
Top View
Top ElectrodeBST Film
Substrate Prepatterned Bottom Electrode
Thick Metal Pads
BST Capacitor
Side View
Figure 5.3: The picture of the completed phase shifter. The side and top views of the BST
varactor loading sections are also shown.
96
5.5 DC and RF Characterization
Different test structures were included on the same wafer to study low and
high frequency performance of the BST varactors. C-V characterization was done
at 1 MHz on a Keithley CV 590 analyzer. The BST film has provided tunability of
2.5:1 (or y of 0.4) at a reverse bias of 20 V.
RF measurements were done on a HP 8722D network analyzer that was
calibrated using on-wafer standards. The two-port s-parameters of the phase shifter
circuit were recorded up to 10 GHz for different bias voltages. 1-port S11
measurements were made on test BST varactors mounted at the end of CPW lines.
The measured S11 data for the varactor diodes was fitted to a series RC model using
the procedure described in [7]. Based on the extracted parameters, the small signal
cutoff frequency (fc) for the BST varactors was estimated to be ~ 250 GHz using
equation (5.6).
The measurement results from the X-Band phase shifter circuit are
presented in Fig. 5.4a. The figure shows the insertion loss of the phase shifter
circuit at different biases. The maximum insertion loss is only 3.1 dB at 10 GHz.
The differential phase shift with respect to the zero bias is plotted in Fig. 5.4b. The
circuit was capable of a 0-250° continuous phase shift at 10 GHz. This corresponds
to a figure of merit of 81°/dB, which is defined as the differential phase shift
divided by the maximum insertion loss for zero voltage state, at the operating
frequency. The return loss is better than –10 dB for all states from DC to 10 GHz as
97
seen in Figure 5.4c. This indicates that the impedance of the loaded line does not
vary strongly with bias and is close to 50 Ω under all bias conditions. As bias is
applied the capacitive loading is reduced resulting in higher Bragg frequency. The
maximum bias voltage required to get the phase shift was below 20V, which is
smaller almost by a factor of two than a similar phase shifter with the same BST
composition and thickness that had two capacitors in series configuration [2]. The
circuit has demonstrated a record figure of merit 93°/dB at 6.3 GHz and 87°/dB at
8.5 GHz.
-10
-8
-6
-4
-2
0
0 2 109 4 109 6 109 8 109 1 1010
S21 MAG [dB] 0vS21 MAG [dB] 5vS21 MAG [dB] 10vS21 MAG [dB] 15vS21 MAG [dB] 17.5v
Inse
rtio
n Lo
ss (d
B)
Frequency (Hz) Figure 5.4a: Measured insertion loss of the X-Band phase shifter at different bias voltages.
The maximum insertion loss occurs at 0 V bias where Bragg frequency is minimum.
98
0
100
200
300
400
0 2 109 4 109 6 109 8 109 1 1010
S21 ANG [Deg] 0vS21 ANG [Deg] 5vS21 ANG [Deg] 10vS21 ANG [Deg] 15vS21 ANG [Deg] 17.5v
Diff
eren
tial P
hase
(Deg
ree)
Frequency (Hz) Figure 5.4b: Measured differential phase shift versus frequency at different bias voltage.
The phase shift linearly increases with frequency indicating a true delay line characteristics.
-60
-50
-40
-30
-20
-10
0
0 2 109 4 109 6 109 8 109 1 1010
S11 MAG [dB] 0vS11 MAG [dB] 5vS11 MAG [dB] 10vS11 MAG [dB] 15vS11 MAG [dB] 17.5v
Ret
urn
Loss
(dB
)
Frequency (Hz) Figure 5.4c: Return loss measurements for X-Band phase shifter.
99
5.6 Analysis and Modeling of results
The circuit performance of the phase shifters has been analyzed and
compared with theoretical models and HP ADS simulations. The BST varactor
parameters are the most important variables in the overall circuit performance,
which determines the loss and the total phase shift. As a result, the accurate
characterization of the varactor properties at high frequencies has utmost
importance to obtain a good match between the design and measured circuit
performance. The measured values of the discrete BST varactors such as the
capacitance, the quality factor and the tunability were used to simulate the circuit
performance.
0
500
1 103
1.5 103
2 103
0 500 1 103 1.5 103 2 103
Cap w=1.5Cap w=3Cap w=6
Mea
sure
d C
apac
itanc
e(fF
)
Design Value (fF)
y=x
Figure 5.5: The characterization of the discrete test BST varactors.
100
Small area discrete BST varactors were fabricated on the same wafer with
the phase shifters and characterized to estimate the values of the actual varactors
used in the phase shifter circuit. The extraction process was discussed in more
detail in Chapter 4. Figure 5.5 shows the difference between the measured values
and the design values for the small area varactors. It was found that the actual
varactors had larger values than their design values. The increase in the capacitor
values is attributed to the higher value of BST thin film capacitance density dc and
the feature enlargement due to process variation. The small area BST varactors use
typically 1.5-3 µm wide stripes and the control of the minimum size feature is
critically important to obtain desired values. As seen from Figure 5.5, the
difference is larger for the varactors with the smallest features. It was estimated that
the discrete BST varactors implemented in the phase shifter circuit had a
capacitance of 360 fF instead of the design value of 260 fF. The accurate
characterization of the quality factor of the discrete varactors proved to be a
challenge since the capacitance and resistance elements were very small. The
device quality factor is extracted to be around 25-30 for the BST varactors of the
typical device sizes. Low frequency C-V measurements have shown that the films
had a tunability of 2.5:1 using variable frequency impedance analyzers. These
values along with the CPW line dimensions used in the simulation programs.
The losses in the varactor and transmission lines are analyzed separately
using Mathematica. Expressions similar to the design equations are developed for
101
the phase shifter unit cells for the analysis. To simulate the phase shifter
performance using HP Advanced Design Systems (HP ADS), a unit cell has been
designed using lumped element circuit components and lossy CPW transmission
lines. The layout for the unit and the circuit is shown in Figure 5.10 and Figure
5.11, respectively at the end of this chapter. The losses in the BST varactor are
modeled using series RC circuit. The typical values obtained from the discrete BST
varactor measurements are used in the simulations. The device quality of 25 (or the
cutoff frequency of 250 GHz) has been assumed at the operating frequency (10
GHz). An equivalent resistance value was calculated based on the cutoff frequency.
This model inherently assumes that at low frequencies, the device performance
becomes better since Q factor is inversely proportional to the frequency. The
capacitor values were tuned by defining a variable for the tunability. By cascading
enough number of the unit cells in series, the phase shifter performance has been
simulated. This model can be improved further to include the film losses by
including an equivalent conductance. Also, it is possible to include the voltage
dependent models for the BST varactors based on the low frequency
measurements.
102
0
100
200
300
400
500
0 2 4 6 8 10
MeasurementADS Simulation
Diff
eren
tial P
hase
Frequency(GHz)
-10.0
-8.00
-6.00
-4.00
-2.00
0.00
0 2 4 6 8 10 12 14
ADS SimulationMeasurementIn
sert
ion
Loss
(dB
)
Frequency(GHz) Fig 5.6a-b: Measured vs. simulated results for the differential phase and the insertion loss
Figure 5.6a-c show the comparisons of the measurement results with the HP
ADS simulations. The differential phase shift is estimated with great accuracy by
both programs. HP ADS estimated 2480 phase shift while the Mathematica models
provided 2430 phase shift. The accuracy is better than 2%.
103
-60
-50
-40
-30
-20
-10
0
0 4 8 12 16 20
0v5v10v15v17.5v
Ret
urn
Loss
(dB)
Frequency(GHz)
Measurement
-70
-60
-50
-40
-30
-20
-10
0
0 4 8 12 16 20
ADS Simulation
y=1y=1/1.375y=1/1.75y=1/2.125y=1/2.5
Ret
urn
Loss
(dB)
Frequency(GHz) Figure 5.6 c: The return loss measurements are compared with the simulation results.
The comparisons for the maximum insertion loss and the return losses are shown in
Figure 5.6b-c. ADS simulation provided an insertion loss of 2.8 dB at 10 GHz and
accurately predicted the overall circuit performance. The ripples in the insertion
loss are estimated to be due to reflections from the unit cell sections and input
104
impedance mismatch. At low frequencies, the fit between the measured and
simulations can be further improved by including a more accurate frequency
0
0.5
1
1.5
2
2.5
3
0 2 4 6 8 10
CircuitLossBST LossesCPWLoss
Inse
rtio
n Lo
ss fo
r 18
00 Pha
se S
hift
Frequncy(GHz) Figure 5.7: The calculated total circuit losses as a function of frequency.
dependent series resistor values. The simulations proved that the circuit
performance can be estimated with good accuracy by using the correct lumped
element values obtained form the discrete varactor measurement. The ripples in
the insertion loss were not captured by the theoretical models used in Mathematica
simulations (Figure 5.7) since the insertion loss was found by simply multiplying
the total number of unit cell section with the insertion loss due to a single section.
The insertion loss was better than –10 dB for all the circuit states at the design
frequency and accurately estimated by ADS simulations
To estimate the loss contributions, the theoretically calculated losses are
also simulated as a function of frequency and the results are shown in Figure 5.7. It
105
is apparent that the varactor losses are the dominant mechanism and therefore the
circuit performance can be improved further by reducing the series resistance and
the dielectric losses in the BST varactors. This can be achieved by simply using
thicker metallization layers for the bottom and the top electrodes. The other means
of achieving improved circuit performances are using multi-finger device approach
to increase the device periphery and adapting more aggressive lithography design
rules.
5.7 Non-Uniform Loading for Improved Return Loss
We have also implemented a different varactor loaded delay line designed
at Hughes Research Lab by Dr. Jonathan Lynch and his colleagues. The design
solves the problem of high return losses in the phase shifters at the operating
frequency. As shown in (5.1), the characteristic impedance of the line is voltage
dependent and its value becomes different from 50 ohms as the voltage is applied.
It has been suggested that the significant return loss improvement can be achieved
by cutting the first and last capacitance values in the half. Using this design
approach, high return losses are maintained even when the capacitors are tuned.
106
-50
-40
-30
-20
-10
0
0 5 109 1 1010 1.5 1010 2 1010
S11 MAG [dB] 0vS11 MAG [dB] 5vS11 MAG [dB] 10vS11 MAG [dB] 15v
S11
MA
G (d
B)
Frequency (Hz)
-10
-8
-6
-4
-2
0
0 5 109 1 1010 1.5 1010 2 1010
S21 MAG [dB] 0vS21 MAG [dB] 5vS21 MAG [dB] 10vS21 MAG [dB] 15v
S21
MAG
[dB
]
Frequency [Hz] Figure 5.8a-b: The return and insertion loss measurements for the non-uniformly loaded
BST phase shifter designed at HRL.
The HRL phase shifter design was implemented at UCSB using the BST
varactors as the loading elements. The phase shifter layout looks exactly the same
as UCSB design except that the individual varactor values are different. HRL
design was implemented on the same mask and fabricated at the same time with the
107
other circuits. The device parameters for the circuit components are extracted as
described earlier in section 5.3.
0
100
200
300
400
500
0 2 109 4 109 6 109 8 109 1 1010
g
S21 ANG [Deg] 0vS21 ANG [Deg] 5vS21 ANG [Deg] 10vS21 ANG [Deg] 15v
Diffe
rent
ial P
hase
Frequency [Hz] Figure 5.8c:: The differential phase shift as a function of frequency obtained by HRL
design.
Figure 5.8a-b show the return and insertion losses along with the phase shift
as a function of frequency for the non-uniformly loaded HRL design. It is observed
that very high return losses, better than –20dB, are achieved for frequencies
between 8-10 GHz. The maximum insertion loss was 4 dB at 10 GHz with 2700
phase shift.
The circuit performance is simulated using HP ADS program in a similar
way using the discrete BST varactor parameters. Simulations shown in Figure 5.9
resulted in good agreement with the return and insertion loss measurements.
108
-50
-40
-30
-20
-10
0
0 5 109 1 1010 1.5 1010 2 1010
Ret
urn
Loss
(dB
)
Frequency (Hz)
-10
-8
-6
-4
-2
0
0 5 109 1 1010 1.5 1010 2 1010
Inse
rtio
n Lo
ss (d
B)
Frequency (Hz) Figure 5.9a-b: ADS simulations of the return and insertion losses for the HRL phase shifter.
109
L=lum
G=gum
W=wum
Subst="CPWSub1"
Num=1
L=lum
G=gum
W=wum
Subst="CPWSub1"
Num=2
R=RsOhm
C=(cm
ax/tun)fF
PhaseShifterU
nitCell
Figure 5.10: The unit cell used in the ADS phase shifter simulations.
110
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
UC
SB
_Unit_C
ellU
CS
B_U
nit_Cell
TermTerm
2N
um=2
Z=50O
hm
TermTerm
1N
um=2
Z=50O
hm
S_Param
SP1
Step=
Stop=20GHz
Start=.0
5GHz
SweepVar="fre
q"
S-PARAMETERS
ParamSweep
Sweep1
Step=
Stop=2.5
Start=1SweepVar="tun
"
PARAMETERSWEEP
CPWSUB
CPWSub1
Rough=0.01um
TanD=0.001
T=1.2um
Hu=1.0E9meter
Cond=4E+7
Mur=1
Er=10.2
H=325um
CPWSub
Option
sOption
s1
MaxWarnings=10
GiveAllWarnings=yes
I_RelTol=1e-6
V_RelTol=1e-6
TopologyCheck=yes
Temp=25
OPTIONS
Device
Performance
FromTestSamples
layout=2x4.3um
cmax=180-18
5*2=360-370fF
Qdev=35
VAR
VAR3
w=ww
g=gg
l=ll
Eqn
Var
VAR
VAR2
M=1
ll=702
gg=405
ww=230
Eqn
Var
VAR
VAR1
Qf=150
tun=1
f=10
q=30
Rs2=106/(2*3
.14*f*q*c
max2)
Rs=106/(2*3.14*f*q
*cmax)
cmax2=180
cmax=360
Eqn
Var
Design
Parameters
cmax=260fF
wcenter=230um,
gap=405um,
lsect=1404um
TESTSTR
UC
TUR
EScm
ax=180-185*2=360-370fFQ
dev=35
Figure 5.11: The BST phase shifter circuit used in HP ADS simulations.
111
References
[1] A. S. Nagra, "Varactor based Technologies for the Tuning and Control of
Microwave Circuits and Antennas," in Electrical and Computer
Engineering: University of California, Santa Barbara, 1999, pp. 115.
[2] B. Acikel, L. Yu, A. S. Nagra, T. R. Taylor, P. J. Hansen, J. S. Speck, and
R. A. York, "Phase shifters using (Ba,Sr)TiO/sub 3/ thin films on sapphire
and glass substrates," 2001.
[3] V. K. Varadan, K. A. Jose, V. V. Varadan, R. Hughes, and J. F. Kelly, "A
novel microwave planar phase shifter," Microwave Journal, vol. 38, pp.
244, 248, 250, 253-4, 1995.
[4] F. De Flaviis, N. G. Alexopoulos, and O. M. Stafsudd, "Planar microwave
integrated phase-shifter design with high purity ferroelectric material,"
IEEE Transactions on Microwave Theory and Techniques, vol. 45, pp.
963-9, 1997.
[5] B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, and R. A. York, "A new
high performance phase shifter using Ba/sub x/Sr/sub 1-x/TiO/sub 3/ thin
films," IEEE Microwave and Wireless Components Letters, vol. 12, pp.
237-9, 2002.
[6] A. S. Nagra and R. A. York, "Distributed analog phase shifters with low
insertion loss," IEEE Transactions on Microwave Theory and Techniques,
vol. 47, pp. 1705-11, 1999.
112
[7] K. Ikuta, Y. Umeda, and Y. Ishii, "Measurement of high-frequency
dielectric characteristics in the mm-wave band for dielectric thin films on
semiconductor substrates," Japanese Journal of Applied Physics, Part 2
(Letters), vol. 34, pp. L1211-13, 1995.
113
Chapter 6
BST Varactors for Tunable Passive
Integrated Circuits
In this chapter, we will discuss the research efforts on tunable passive
integrated circuits fabricated by integrating lumped elements such as inductors and
resistors with BST varactors on the same chip. Lumped element circuits offer
compact size and high performance, especially at lower end of the frequency
spectrum. Lumped element synthetic phase shifters and tunable matching networks
have been studied. Low voltage tunable matching networks suitable for wireless
applications that can be operated at 0-5 V range are implemented. Design
considerations and challenges are discussed.
6.1 Highly Integrated Passive Element Circuits
The trend in telecommunications devices for portable and battery powered
applications require a high level of integration to reduce size, weight, cost and
power consumption. In particular, high performance front-end systems for wireless
applications require miniaturization and integration technology capable of high
quality performance into the gigahertz frequencies [1]. There are a number of
candidate technologies to meet these system requirements [2, 3]. The arguments
114
indicate that a single chip transceiver in standard digital CMOS technology is not
feasible in the near future [1]. The unavailability of high Q on chip inductors
essential for the realization of low loss filters, matching networks, and resonators is
one of the main problems. Low temperature co-fired ceramic (LTCC) technology
and thin film multi-layer or multi chip module technologies (MCM) are other
alternatives being considered [1, 2]. LTCC technology is reported to have
materials with limited quality, large tolerances on dimensions of the screen-printed
conductors and vertical shrinkage during firing. Modeling difficulties for three
dimensional structures are also reported. MCM technology, on the other hand, has
shown great promise in the interconnection technology realizing integrated passives
components for microwave frequencies. High quality inductors using thick copper
metallization and low loss dielectrics are currently available.
We believe that system on a package (SOP) approach will still be important
since it is not possible to integrate complete front-ends on a single chip as there will
always be some sub-blocks that are difficult to realize. The advantage of SOP
approach is that the most optimal technology (performance/cost) can be used to
create each sub-block. By combining the passives with surface chip (wirebond, flip
chip) active devices fully integrated RF front-end subsystems may be realized. Our
goal is to incorporate the BST technology to achieve tunability in these systems. In
the following sections a discussion of the essential passive circuit components
(inductors, capacitors and resistors) required to achieve high performance will be
provided.
115
6.2. Passive Circuit Components: Overview
On chip inductors are realized in either lumped or distributed form in
microwave circuits. Lumped inductors are lengths of metal line, which have mutual
inductance by virtue of electromagnetic interactions between the metal segments
[4]. Depending on the inductance required, integrated inductors can be realized
either as a straight narrow line, as single loop inductors or multi-turn spiral
inductors. The drawback of the spiral inductors is that the center turn needs to be
connected back to the outside circuit, which dictates that either air-bridge
crossovers or dielectric spaced underpass must be used. Round inductors
accomplish a better performance than rectangular spirals at the expense of layout
complexity. Circular shaped spiral inductors have the advantage of smooth field
distribution and the absence of sharp corners that would cause extra losses and
parasitic capacitive effects.
The integrated spiral inductor requires a more complicated fabrication
process and analysis for estimating the component behavior and parasitic effects
than other passive elements. Large value inductors can be implemented in relatively
smaller areas by using multi layer metallization schemes [5]. Due to the large
number of geometrical parameters involved (conductor width, conductor spacing,
number of turns, diameter, spacing to the ground plane, multi-layer metallization
layers) the characterization and optimization of the inductor’s performance may
become complex. All the geometrical parameters are inter-related and different
116
combinations may achieve the same inductance value, but with different quality
factors and frequency behavior.
The behavior of a spiral inductor may be modeled up to its first resonant
frequency using the lumped element equivalent circuit model in Figure 6.1. [6] In
the model, the ohmic losses are accounted by resistor R ; the desired inductance is
represented by L and the parasitic capacitive effects are shown using different
capacitor C values. C1 and C2 model the capacitive coupling between the coil and
the ground planes and C3 indicates the coupling between the turns of the coil itself.
C1
L
C2
C3
R
Figure 6.1: The lumped element equivalent model for multi-turn inductor. The conductor
loss is indicated by series resistor whereas capacitors indicate the parasitic coupling.
117
Planar spiral inductors designed for operation above a few gigahertz are
restricted in their inductance values by the parasitic capacitances. The dominant
parasitic capacitance occurs between the spiral turns and the ground plane. At
higher frequencies, the capacitances resonate with the inductance and limit the
upper frequency of operation. Reduction of these capacitances is accomplished by
designing spirals with fewer turns and smaller radii. Reducing the spiral radius
limits the conductor width, increasing the inductor’s series resistance. High
frequency spiral inductors are typically limited to a few nanohenries of inductance.
The design equations in [6] are used to obtain desired inductor values with
high quality factors. Different layouts result in the desired inductance value and
other design requirements such as high Q factor, minimum size, minimum number
of turns, large metal widths etc are used to finalize the design. The achievable
values of inductance and Q decrease with frequency.
Capacitors are the other important passive elements in the integrated
circuits. A discussion was presented for metal-insulator-metal (MIM) and
interdigital BST capacitors in Chapter 2. Similar arguments are still valid for
capacitors using other dielectrics. Fixed value MIM capacitors use common
dielectrics such as silicon nitride, silicon dioxide and polymide. Silicon nitride is
more popular in MMICs since it has larger dielectric constant and can be used for
passivating the GaAs active devices. Polymide can also be used as a dielectric in
processes that use polymide as the spacer layer for the spiral inductors to achieve
fixed small value capacitors.
118
Resistors in MMIC circuits are made of either doped semiconductors (mesa
resistors or implanted planar resistors) or deposited thin film resistive (TFR) layers.
Since the film thickness is fixed, it is common practice to quote the resistivity in
terms of aspect ratio, i.e. ohms-per-square. The actual size of the resistor is
determined by the lithography tolerance requirements and power dissipation due to
current flow. The area of the ohmic contact pads on the resistors must be suitably
large to minimize their contact resistance and provide better control of the
resistance value. Sputtered or ebeam evaporated thin film resistors provide a better
linearity and lower temperature dependency compared to mesa type resistors
implemented with semiconductors. The most commonly used materials for TFRs
are tantulum nitride, cermet and nickel chrome.
Our efforts focused on the development of a viable technology that
incorporates BST varactors and integrated passive components. Our task has been
integrating the passives into relatively more mature and more demanding BST
varactor process.
The high temperature growth conditions for BST film is not compatible
with the relatively low temperature steps for the passive component processes. This
necessitated processing for BST varactors to be done first. A brief description of
the process is given here. The details can be found in the Appendix C. The bottom
electrode is deposited directly on sapphire substrate, followed by BST film growth.
The film stoichiometry and thicknesses are varied for different system
requirements. For example, films with high barium (Ba) content, which are also
119
thinner than standard films, are grown to get high tunabilities at lower operating
voltages. Pt/Au top electrodes are evaporated and patterned by lift-off defining the
BST “finger” varactors and low frequency test devices. Using buffered
hydrofluoric acid (HF), BST is etched clearing the bottom electrodes for thick
metal contact. The process described so far is basically BST varactor process that
was described in detail in Chapter 3. After this step, the integration of other passive
structures is performed.
A thick layer of Ti/Au metals are evaporated and patterned by lift-off to
contact the bottom electrode and define CPW transmission lines directly on the
substrate. If the inductor underpass is used in the process instead of air-bridge, it
will be patterned at this step. Both underpass and air bridge process have been
implemented for inductor process. It is found that underpass structures are more
desirable because of the planarity issues with thick inductor metallization deposited
on the substrate. Air bridges may have shorting problems. When the span of the air
bridge is large especially with many-turn inductors, reliability issues arise.
Underpass can be made wider in order to minimize resistive losses and increase the
current carrying capacity. Different dielectrics, namely benzo-cyclobutene (BCB)
and PMGI, have been investigated for the crossover layer for the inductors. Both
dielectrics have low dielectric constants and loss tangents. They are spun on the
samples using photoresist spinner and cured for solvent removal. The curing
temperatures for both dielectrics are relatively lower, below 250 0C. Instead of
SiN, these dielectrics can also be used as the low ε material to implement small
120
fixed value metal-insulator-metal (MIM) capacitors. Vias are opened in the
dielectric layer for making contact to underpass layer. (PMGI is patterned by using
a developer whereas BCB is etched using SF6 gas.) Finally, thick Ti/Au inductor
metal is put directly on the dielectric and patterned by liftoff , making contact to the
underpass metals through vias. We also integrated thin film resistors (TFR) using
Ta material for tunable matching networks. Since Ta metal becomes extremely hot
during ebeam evaporation, TFR process must come prior to PMGI or BCB process.
Figure 6.2 shows the cross-section of a tunable passive circuit that has BST
varactors.
Embedded Thin Film Resistor
Fixed small value capacitor
Inductor Underpass
Spiral Inductor
Via
Au/Pt Bottom electrode
BST film
Top electrode
First thick metal layer
Second thick metal layerMain dielectric layer
PMGI
Substrate
Figure 6.2: The cross section of a tunable passive integrated circuit using BST varactors.
6.3 Compact size lumped element synthetic phase shifters
In chapter 5, we examined the uniformly loaded transmission line circuits
using BST varactors for variable delay lines. The design was optimized for the
121
minimum insertion loss for desired phase shift. However, the phase shifter circuit
requires large circuit areas. As the operating frequency becomes lower, the circuit
size becomes impractically large. The size can be reduced significantly by using
lumped element circuit equivalent for the transmission line section or by loading
the transmission lines more heavily using higher impedance transmission line
sections. We will discuss the first approach that uses lumped element transmission
line sections. The simple design and broadband frequency characteristics make the
circuits attractive for low frequency applications.
Design parameters for the lumped element phase shifter is relatively simple
compared to the periodically loaded transmission line. A quarter wavelength
transmission line (900) can be replaced by a lowpass filter in π configuration at the
operating frequency as shown in Figure 6.3. The equivalent inductance L and
capacitance C for the lumped equivalent circuit [7] is given by
ZL ; Cf fZπ π
= =0
0
12 2
(6.1)
where Z0 is the characteristic impedance, which is 50 Ω in this work, and f is the
design frequency. BST varactor technology is used for implementing equivalent
capacitance C. By applying bias to the BST capacitor, the transmission line
parameters, namely phase velocity and characteristic impedance, can be altered.
The capacitance value is designed to be the average of the Cmax and Cmin in (6.2),
where Cmax is the zero bias BST capacitor value.
max minC CC +≈2
(6.2)
122
A single stage low pass filter as shown in Figure 6.3 was designed for 5.2
GHz. HP ADS program is used to optimize the phase shift from a unit section. By
cascading more of the unit cell in series, the circuit can provide additional phase
shift. The approach used in the simulations was described in detail in Chapter 5.
Circuit simulations have shown a 300-phase shift with an insertion loss of 0.6 dB
assuming 3:1 tunability. Three sections were used to design a 900-phase shifter at C
Band.
Z , longλ0 4
≡
ZL fπ= 02
C fZπ=0
12 Z = Ω 0 50
Figure 6.3: The equivalent circuit for quarter wavelength transmission line used in the BST
lumped phase shifter. The equivalent capacitor was implemented using BST varactors.
123
C1C2C2C1
L LL
C1=.49 pF C2=.98 pF L=1.2 nH
Figure 6.4a: The schematic of the lumped element circuit.
The schematic for the circuit and the simulated phase shift and insertion
loss performance are shown in Figure 6.4a-c. A photograph of the phase shifter is
provided in Figure 6.5. The final design values for L, C1 and C2 were 1.2 nH, 490
fF, and 980 fF, respectively.
-20
0
20
40
60
80
100
0 1 2 3 4 5 6
Phas
e Sh
ift (D
egre
es)
Frequency (GHz)-4
-3.5-3
-2.5-2
-1.5-1
-0.50
0 1 2 3 4 5 6 7 8
Inse
rtion
Los
s(dB
)
Frequency(GHz) Figure 6.4b-c: The simulations for the phase shift and insertion loss of the lumped element
phase shifter.
124
The total size of the circuit is 1.2 mm x 2.4 mm. This circuit, to our
knowledge, is the smallest phase shifter circuit with comparable performance
implemented using BST films. It is also the first time the BST varactors have been
implemented together with lumped element inductors.
2.4 mm
1.2 mm
BST VaractorsAir Bridge
Figure 6.5: A photograph of the fabricated BST lumped element circuit.
Figure 6.6a-c show the measurement results from the lumped element phase
shifter. The circuit provided 630-phase shift with only 1.1 dB insertion loss at 5
GHz. The return losses were better than 20 dB at the design frequency for all the
voltages.
It was found that the capacitance density was lower than the design value
(15 fF/µm2) by 20-30% on the large area capacitors. This difference in the
capacitor density is the reason why the circuit yielded a lower phase shift and
insertion loss at the design frequency. The actual tunability was also lower than 3:1.
125
-20
0
20
40
60
80
100
0 1 2 3 4 5 6Diff
eren
tial P
hase
Shi
ft (D
egre
es)
Frequency (GHz)
Bias=0V
Bias=8V
Bias=12V
-6
-5
-4
-3
-2
-1
0
0 1 2 3 4 5 6
Inse
rtio
n Lo
ss(d
B)
Frequency(GHz)
(a) (b)
-50
-40
-30
-20
-10
0
0 1 2 3 4 5 6
Ret
urn
Loss
(dB
)
Frequency(GHz) (c)
Figure 6.6a-c: The measurement results for the BST lumped element phase shifter The differential phase, the insertion and return loss are shown.
The overall performance of lumped element BST varactor phase shifter is
still comparable to semiconductor alternatives. This design has provided a figure of
merit of 57.3 Degree/dB. A similar design, which was implemented with GaAs
varactors, provided 950 phase shift with 1.7 dB insertion loss (56 Degree/dB) [7].
126
6.4 Tunable Impedance Matching Networks
Impedance matching networks are extensively used in both passive and
active microwave circuits [8]. They are used in connecting two different sections or
components of different impedances to ensure maximum power transfer from one
port to another. In solid-state circuits such as amplifiers and mixers, the matching
networks have an important role when low noise amplifiers and broadband
characteristics are desired. The impedance matching networks are designed at
microwave frequencies by employing both lumped and distributed circuit elements.
These units can be placed in the radio communication circuits and systems in order
to obtain maximum power transfer. Highly efficient power transmission is
particularly important today as low power design requirements become more and
more important in mobile communication systems.
Most general impedance matching circuit networks employ lumped element
inductors and capacitors connected in a L-shaped configuration. The major
disadvantage of L-networks is that the Q-factor of the circuit is entirely determined
by the source and load resistances. The addition of one element to the L-shaped
configuration results in the π -section and T -section impedance configurations,
which provide control of bandwidth with more practical circuit elements [8]. They
can be visualized as two L-networks where the two components in the center are
the same type. The impedance transformation is achieved in two steps, first to an
127
intermediate impedance level, which can be chosen in order to control the amplifier
bandwidth, and then to the source resistance [9].
Tunable active matching networks can improve the performance and yield
of MMICs. For example, the output impedance of an RF amplifier depends on the
signal level and it is thus not easy to maintain a good impedance match over the
entire amplitude range. Adaptive impedance circuits can be used to tune the output
impedance of the amplifier so that the maximum power transfer can be achieved
regardless of variations due to temperature changes or large signal phenomena [10].
Active matched circuits are reported in the design of interstage networks to provide
wideband interstage impedance matching [11]. Gain and significant return loss
improvements were reported. The matching frequency was effectively tuned
without affecting noise figure and power performance. A tunable matching network
with desired noise and power performance can be used also in the input and output
stages.
Our efforts for tunable matching networks focused on material and process
development to address the system requirements for low voltage wireless
applications. The component was designed to be used at the output terminal of the
power amplifiers to increase power efficiency and thus battery life. It also can
change the frequency response of PA module by using it in the interstage matching
network. The schematic for such an application is shown in Figure 6.7. Large value
DC blocking capacitors can be employed on the same chip using the high dielectric
128
constant of BST material to reduce the component count. The thin film resistor
process is also included to apply bias voltages to BST varactors.
BST device
Vtune
Vcc
Ca
Cb
Figure 6.7: The schematic of the BST tunable matching network used in the power amplifier
circuits.
Wireless applications require electronic components that can be operated at
relatively low voltages, below 5V. Low leakage currents are also desirable to
extend the battery life. For this particular tunable matching network, a moderate
tunability (25-50%) is sufficient for the system requirements. The required BST
tunable capacitor sizes are typically in the range of 10-30 pF. The DC blocking
with a value more than 200 pF is desired on the same chip.
129
Because of tight voltage requirements, high Ba content BST films were
grown using . .Ba Sr TiO0 5 0 5 3 targets. Thinner films are grown (typically 50 nm) to
further reduce the control voltage. As the film thickness becomes thinner, the edge
coverage of bottom electrode becomes potentially problematic for overlay
capacitors. The sharp bottom electrode edge makes short-circuit failure more likely
and reduces the breakdown voltage rating of the capacitor. In industry, this problem
has been solved by connecting upper electrode to the rest of the circuit with an air-
bridge [4]. In this work, a sacrificial oxide/nitride dielectric layer was used to
increase the total film thickness at the edge improving breakdown voltages.
The process flow for the tunable matching network is very similar to the
two capacitor in series configuration described in Chapter 3. However, only a
single capacitor was employed to have low bias voltages. The modified process
flow is shown in Fig 6.8 and the details are provided in the Appendix B. First, BST
films were grown on the prepatterned sapphire substrates with the e-beam
evaporated bottom electrodes. Then, the top electrodes were evaporated followed
by the BST etch. As mentioned earlier, the top electrodes didn’t extend over the
bottom electrode edge to avoid the shorting problems due to thin films. Next, the
thin film resistor was evaporated. This is followed by sputtering of SiN film and
liftoff. Finally, thick contact metals were evaporated for contact pads and
interconnecting lines. The completed device picture is shown in Figure 6.9.
130
Thick Metal
(e)
Ground Signal
Thin Film Resistor
(d)
SiN LayerThin Film Resistor
(b)
BST Film
Sapphire Substrate
(a)
Bottom Electrode
(c)
BottomElectrode
Top ElectrodeBST Film
BST Varactor
Figure 6.8: The fabrication process for the tunable impedance matching network.
131
DC Blocking Capacitor
BST Varactors
Tuning Pad
Thin film resistor
Figure 6.9: The picture of the tunable matching network. The DC voltage is applied to the BST varactors using on-chip resistors.
Figure 6.10a-b show the measurements results for the BST capacitors in the
tunable matching networks. A tunability of almost 2:1 was observed with a
maximum voltage of 5 V. The capacitance measurements at high frequencies
indicate that the dispersion in the material is minimal and the curve is in accordance
with low frequency measurement. Low bias voltages make the circuits very
attractive for the wireless applications.
132
8
9
10
11
12
13
14
0 1 2 3 4 5
RFMD 15pF nom.
Cap
acita
nce,
pF
Voltage, V
1MHz
Figure 6.10a C-V measurement for the varactors used in the tunable matching network
7
8
9
10
11
12
13
14
0 1 2 3 4 5
Cap
acita
nce(
pF)
Frequency, GHz
RFMD 15pF nom.
0v
1v
2v
3.5v
5v
Figure 6.10b The capacitance vs. frequency measurement at different bias voltages.
133
References
[1] G. Carchon, B. Nauwelaers, P. Pieters, K. Vaesen, W. De Raedt, and E.
Beyne, "Multi layer thin film MCM-D for the integration of high
performance wireless front end systems," Microwave Journal, Euro-
Global Edition, vol. 44, pp. 96-110, 2001.
[2] S. Donnay, P. Pieters, K. Vaesen, W. Diels, P. Wambacq, W. De Raedt, E.
Beyne, M. Engels, and I. Bolsens, "Chip-package codesign of a low-power
5-GHz RF front end," Proceedings of the IEEE, vol. 88, pp. 1583-97,
2000.
[3] T. H. Lee and S. S. Wong, "CMOS RF integrated circuits at 5 GHz and
beyond," Proceedings of the IEEE, vol. 88, pp. 1560-71, 2000.
[4] A. A. Rezazadeh and C. Sansom, "Active Devices and Fabrication
Technology," in MMIC Design, I. D. Robertson, Ed.: IEE, 1995.
[5] S. M. Duffy and M. A. Gouker, "High combining-efficiency X-band
spatial power-combined array using a multilayered packaging
architecture," IEEE Transactions on Microwave Theory and Techniques,
vol. 48, pp. 1769-71, 2000.
[6] P. Pieters and E. Beyne, "Spiral inductors integrated in MCM-D using the
design space concept," 1998.
134
[7] F. Ellinger, R. Vogt, and W. Bachtold, "Ultra compact, low loss, varactor
tuned phase shifter MMIC at C-band," IEEE Microwave and Wireless
Components Letters, vol. 11, pp. 104-5, 2001.
[8] I. J. Bahl, "Filters, Hybrids and Couplers, Power Combiners and Matching
Network," in Handbook of Microwave and Optical Components, vol. 1, C.
K, Ed. John Wiley & Sons, 1989.
[9] I. D. Robertson and M. W. Geen, "Amplifiers," in MMIC Design, I. D.
Robertson, Ed., 1995.
[10] M. Lapinoja and T. Rahkonen, "An active tuning and impedance matching
element," 1998.
[11] K. Yamanaka, K. Sugaya, Y. Horiie, T. Yamaguchi, N. Tanahashi, and Y.
Itoh, "A Ku-band frequency-tunable active matched feedback MMIC
amplifier using variable-capacitance elements," 2000.
135
Chapter 7
Summary and Future Work
7.1 Integrated BST Varactor Technology
The motivations for the development of Barium Strontium Titanate (BST)
thin film varactor technology have been discussed for tunable microwave circuit
applications. The advantages/disadvantages of the different varactor technologies
have been studied together with more emphasis on the applications that can benefit
from the BST thin film technology immediately. An overview on the fundamental
BST thin film material properties has been provided. Certain desirable features of
this technology, which will ensure the widespread application, have been the focus
of our research efforts. Available BST varactor device topologies have been
compared. The development of BST parallel plate varactor technology was studied
in detail. We attempted to resolve the material and device integration challenges.
Innovative device topologies and fabrication approaches were developed to
successfully overcome the device issues. New high performance planar BST
varactors, which look similar to Schottky diodes, have been implemented. Most of
the technology challenges have been overcome. Device measurements and new
device models have been compared. The BST varactors have been incorporated as
136
the tuning element in microwave circuits including the distributed analog phase
shifters, lumped element circuits and tunable matching networks to demonstrate the
potential of this technology for low cost components.
Future efforts must be directed toward improving the device quality factor
at high frequencies. A good understanding of the material properties is essential to
improve the varactor loss and tunability performances for optimizing the device
performance. Further studies on the effect of the doping to lower losses in the BST
films are needed. At the same time, the conductor losses in the BST varactors can
be minimized by employing the thicker base electrodes and the multi-finger BST
varactors, which will dramatically improve the device performance. Long time
reliability, dominant failure mechanisms and temperature dependent
characterization of the BST varactors need further studies. High power
performance of the BST varactors must be further explored for potential circuit
applications.
7.2 BST Varactors for Loaded Transmission Line Phase
Shifters
The potential for low cost high performance phase shifters for phased array
systems using BST varactors has been discussed. The BST varactor loaded
transmission lines are studied in detail. The theory and the design equations for the
phase shifter circuits with the minimum loss have been reviewed. An optimally
137
designed 1800 phase shifter at X-Band has been fabricated on sapphire substrate
using CPW lines. The measurement results and the circuit simulations have shown
good agreement. The phase shifter has provided continuous 0-250°- phase shift at
10 GHz with a maximum insertion loss of only 3.1 dB. The same phase shifter has
shown a figure of merit (93°/dB) at 6.2 GHz, the highest figure of merit (FOM)
reported for BST phase shifters at room temperature.
A non-uniformly loaded phase shifter with improved return loss designed at
Hughes Research Labs (HRL) was fabricated using the BST varactor technology.
The return losses better than 20 dB are demonstrated over the design band (8-10
GHz).
Circuit simulations show that the majority of the circuit losses are due to the
BST varactors. Thus future efforts must concentrate on reducing the BST varactor
losses for lowering the total circuit loss. Multi-finger BST varactors that maximizes
the device periphery with thicker base electrodes will reduce the device losses.
Other analog phase shifter topologies such as reflection type phase shifters or phase
shifters with heavy BST loadings to reduce the circuit areas are possible
7.3 Tunable Passive Integrated Circuits and Lumped Element
BST Phase Shifters
Very compact, small size high performance lumped element BST phase
shifters have been demonstrated for lower GHz frequencies. Inductors with high Q
138
values are integrated into the BST fabrication process. Equivalent lumped element
inductors and BST capacitors are used to replace transmission line sections of the
varactor loaded phase shifters. Simple design equations have resulted in desired
phase shift. Promising results are obtained from a 90° phase shifter, which has
provided 63° phase shift at 5.2 GHz with only 1.1 dB insertion loss. The return
losses were better than 20 dB. This circuit has the smallest size reported for BST
phase shifters. The figure of merit is comparable to other similar designs
implemented using GaAs MMICs.
The performance of the synthetic transmission line phase shifter can be
improved further by designing low loss inductors and BST varactors. A thicker
metallization layer or a high conductivity material such as Cu can be used for
inductor process and underpass metal. A variety of small size circuits are possible
using the lumped element circuit approach. These include reflection type phase
shifters using Lange or hybrid couplers, tunable lumped element hybrid couplers,
filters etc. Insertion loss and phase shift characteristic can be further investigated to
optimize the circuit performance.
BST varactors are developed for interstage amplifier matching networks for
wireless applications. Material properties and fabrication process are optimized to
comply with low voltage system requirements. The tunable matching networks are
suitable for post-production tuning of the power amplifier circuits to obtain higher
amplifier efficiency and can extend the battery life can change the frequency
139
characteristic of the PA. Inexpensive BST components can potentially reduce the
number of parts in modules and increase functionality.
140
Appendix A
BST Finger Capacitor Fabrication
1. Solvent clean
• Acetone (ACE) rinse for 3 min
• Isopropyl alcohol (ISO) rinse for 3 min
• De-ionized water (DI) rinse for 3 min
• Dehydration bake for 30 min in 120°C oven
2. Bottom Electrode Lithography (Image Reversal)
• Spin on HMDS at 6000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 6000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 45 sec @ 7.5 mW/cm2 intensity w/o filter at Karl
Suss Aligner
• Develop in AZ 400K:DI (1:5 by volume) solution for 45 sec
• Mask exposure for 8 sec @ 7.5 mW/cm2 intensity w/o filter
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:4 by volume) solution for 30 sec
141
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
3. Bottom Electrode Metallization (Ti/Au/Pt)
• Load the samples into E-beam evaporator #3
• Evaporate the following metals after pumping below 7 10-7 Torr
• Ti (50 Å , evaporation rate less than 1Å/sec)
• Au (1000 Å evaporation rate ~1-2 Å/sec)
• Pt (1000 Å evaporation rate ~1.5 Å/sec)
• Finish the liftoff in ACE
• Solvent clean and blow dry using N2
Next, BST thin film is grown on the sample.
3. Top Electrode Lithography (Image Reversal)
• Solvent clean and dehydration bake
• Spin on HMDS at 6000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 6000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 45 sec @ 7.5 mW/cm2 intensity w/o filter at Karl
Suss Aligner
• Develop in AZ 400K:DI (1:5 by volume) solution for 45 sec
142
• Mask exposure for 8 sec @ 7.5 mW/cm2 intensity w/o filter
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-40 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 90°C oven for 5 min
4. Top Electrode Metallization (Pt/Au)
• Load the samples into E-beam evaporator #3
• Evaporate the following metals after pumping below 2 10-7 Torr
• Pt (1000 Å , evaporation rate less than 1.5-2 Å/sec)
• Au (5000 Å evaporation rate ~5-10 Å/sec)
• Finish the liftoff in ACE
• Solvent clean and blow dry using N2
5. BST Etch Lithography
• Solvent clean ACE, ISO, DI and dehydration bake
• Spin on HMDS at 5000 rpm for 30 sec
• Spin on AZ 4210 photoresist at 5000 rpm for 30 sec
• Soft bake on 95°C hotplate for 60 sec
143
• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
• Mask exposure for 12 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:4 by volume) solution for 60-70 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 120°C oven for 10 min
6. BST Etch
• Use the hotplate with stirrer turned on
• Etch in Buffered HF:DI (1:1) in three minute steps
• Check the sample under microscope to determine if the etch is complete.
• DI rinse for 1 min, blow dry with N2
• Remove PR with solvent cleaning. Heating of the solvents may be needed
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec may help to
remove photoresist residues
7. Thick Metal –CPW- Lithography (Image Reversal)
• Solvent clean and dehydration bake
• Spin on HMDS at 3000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 3000 rpm for 30 sec
144
• Soft bake on 95°C hotplate for 90 sec
• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
• Mask exposure for 23 sec @ 7.5 mW/cm2 intensity with blue filter
• Post bake on 105°C hotplate for 90 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-35 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 90°C oven for 5 min
8. Thick Metal Metallization (Ti/Au)
• Load the samples into E-beam evaporator #1
• Evaporate the following metals after pumping below 1-2 10-6 Torr
• Ti (100 Å , evaporation rate less than 1.5-2 Å/sec)
• Au (1.2 µm evaporation rate ~10-20 Å/sec)
• Finish the liftoff in ACE
• Solvent clean and blow dry using N2
145
Appendix B
Tunable Matching Network Process
First, BST “Finger” varactors are fabricated using the following steps
• Bottom electrode metallization on the substrate
• The BST film growth on the pre-patterned templates
• The top electrode metallization followed by the BST etch.
The details of these steps are to be found in Appendix A.
1. Thin Film Resistor Lithography (light field mask, image reversal)
• Solvent clean in ACE, ISO and DI rinse
• Dehydration bake in 120° C oven for 30 min
• Spin on HMDS at 5000 rpm for 40 sec
• Spin on AZ 5214 IR at 5000 rpm for 40 sec (2 µm thick)
• Soft bake on 95°C hotplate for 65 sec
• Mask exposure for 10 sec @ 7.5 mW/cm2 intensity
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-35 sec
146
• DI rinse for 1 min, blow dry with N2
• O2 plasma descum (300 mT, 100 W, low frequency) for 30 sec
2. Thin Film Resistor (TFR) Metallization
• Load samples in E-beam evaporator #1
• Evaporate the following metal after pumping down to 1 10-6 Torr
• Ti/Ta (50/1000 Å at slow rates) or
• NiCr alloy (400 Å at 1-2 Å/sec)
Ta becomes very hot during the evaporation. The evaporation should be done
in 2-3 steps cooling the sample for 5 min between each steps.
• Liftoff the undesired metal by removing photoresist in ACE
• Solvent clean and DI rinse and blow dry using N2
3. SiN Lithography (light field mask, image reversal)
• Solvent clean in ACE, ISO and DI rinse
• Dehydration bake in 120° C oven for 30 min
• Spin on HMDS at 6000 rpm for 40 sec
• Spin on AZ 5214 IR at 6000 rpm for 40 sec (2 µm thick)
• Soft bake on 95°C hotplate for 65 sec
• Mask exposure for 8 sec @ 7.5 mW/cm2 intensity
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
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• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-35 sec
• DI rinse for 1 min, blow dry with N2
• O2 plasma descum (300 mT, 100 W, low frequency) for 30 sec
4. SiN Sputtering
• Pressure settings:
• Capacitance Mamometer: 1.8 mTorr, Convectron: 46 mTorr Deposition rate:
5nm/min (20 minutes per 1000 angstroms)
Stop sputtering by closing shutter
As the last step, the thick metals are evaporated for contacts and CPW metals
(See Appendix A).
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Appendix C
Fabrication Details for Passive Integrated
Circuits
First, BST “Finger” varactors are fabricated using the following steps
• Bottom electrode metallization on the substrate
• The BST film growth on the pre-patterned templates
• The top electrode metallization followed by the BST etch.
• The thick metals are evaporated for contacts to the bottom and top electrodes,
underpass section for the inductors and CPW metals
• Deposit the thin film resistor (TFR) metals
The details of these steps are to be found in Appendix A.
1. Airbridge post lithography
• Solvent clean in ACE, ISO and DI rinse
• Dehydration bake in 120° C oven for 30 min
• PMGI SF11 application
• Spin on SF11 at 5000 rpm for 40 sec
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• Soft bake on 200° C hotplate for 2 min
• Cool down for 30 sec
• Spin on SF11 at 5000 rpm for 40 sec
• Soft bake on 200° C hotplate for 3 min
• Edge bead removal
• Spin on AZ 4330 at 4000 rpm for 40 sec
• Soft bake on 95° C hotplate for 1 min
• Image exposure for 4330--- 1.5 min @ 7.5 mW/cm2
• Develop in AZ 400K:DI (1:4) for 1 min
• Deep UV flood exposure of PMGI SF11 (dosage 3500 mJ/cm2)
• Develop in SAL 101 developer (full strength) for 1 min
• Repeat deep UV expose and SAL develop step 2 times
• O2 plasma descum (300 mT, 100 W, low frequency) for 5 min
• Remove AZ 4330 in ACE, ISO rinse
• DI rinse , blow dry with N2
2. Spiral Inductor Lithography ( image reversal)
• Solvent clean and dehydration bake
• Spin on HMDS at 3000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 3000 rpm for 30 sec
• Soft bake on 95°C hotplate for 90 sec
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• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
• Mask exposure for 23 sec @ 7.5 mW/cm2 intensity with blue filter
• Post bake on 105°C hotplate for 90 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-35 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 90°C oven for 5 min
3. Thick Metal Metallization (Ti/Au)
• Load the samples into E-beam evaporator #1
• Use lowered boom to hold sample (thickness is 2 times larger)
• Evaporate the following metals after pumping below 1-2 10-6 Torr
• Ti (100 Å , evaporation rate less than 1.5-2 Å/sec)
• Au (1.2 µm evaporation rate ~10-20 Å/sec)
• Finish the liftoff in ACE
• Solvent clean and blow dry using N2
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Appendix D
Two BST Capacitors in Series: Early Device
1. BST Etch Lithography
• Solvent clean ACE, ISO, DI and dehydration bake
• Spin on HMDS at 5000 rpm for 30 sec
• Spin on AZ 4210 photoresist at 5000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
• Mask exposure for 12 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:4 by volume) solution for 60-70 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 120°C oven for 10 min
2. BST Etch
• Use the hotplate with stirrer turned on
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• Etch in Buffered HF:DI (1:1) in three minute steps Etch rate may
fluctuate.
• Check the sample under microscope to determine if the etch is complete.
• DI rinse for 1 min, blow dry with N2
• Remove PR with solvent cleaning. Heating of the solvents may be needed
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec may help to
remove photoresist residues
9. SiO2 Lithography (Image Reversal)
• Spin on HMDS at 6000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 6000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 45 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:5 by volume) solution for 45 sec
• Mask exposure for 8 sec @ 7.5 mW/cm2 intensity w/o filter
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:4 by volume) solution for 30 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
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• Post-bake in 90°C oven for 5 min
10. SiO2 Evaporation
• Load the samples in E-beam #1 or #2.
• Deposit 5000Å of SiO2
• Lift-Off in ACE. Ultrasonic may help in liftoff. 4.
11. Top Metal/Oxide Lithography (Image Reversal)
• Solvent clean and dehydration bake
• Spin on HMDS at 6000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 6000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 45 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:5 by volume) solution for 45 sec
• Mask exposure for 8 sec @ 7.5 mW/cm2 intensity w/o filter
• Post bake on 105°C hotplate for 65 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-40 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 90°C oven for 5 min
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12. Top Metal/Oxide Evaporation
• Load the samples into E-beam evaporator #1
• Evaporate the following metals/oxide after pumping below 1-2 10-6 Torr
• Ti /Pt/Au/Pt/SiO2 (50 Å /1000 Å/2000 Å/500 Å/3000 Å)
• Finish the liftoff in ACE
13. Pt Etch
• Don't forget Pt and SiO2 monitor sample
• Use thick Si carrier with SiO2 deposited on it which etches in Cl2 slowly
• Put Pt monitor sample in the center. Align the laser.
• Set Chamber Pressure = 5 mtorr
• He = 5-10 sccm. Pressure 7-9 mT.
• C12 = 10 sccm.
• Power = 400 W constant power (monitor the voltage)
• Time = 5-6 min
• Make sure the electrode spacing is 3.2". Turn on He gas first. Let it
stabilize. Note the chamber pressure. Increase the desired pressure by this
He background
• Turn on Gas flow. See the chamber pressure. (This has to be smaller than
your desired pressure). Turn on Pressure. Turn on the Power. Etch for
desired amount. 1OOO A Pt is etched in 4-5 min. Etch TiO2 layer.
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• Pt may redeposit on the sample. DI rinse. 1 min ultrasonic
• Solvent Clean
14. PECVD SiN Deposition
• Solvent clean and dehydration bake
• Deposition 2000A of SiN at 150C. (Program name: SiN20). Don't forget
to put 2 Si monitor samples! Some suggest to do this in two steps.
• Measure the oxide thickness and refractive index on the monitor samples.
• Isopropanol 30 sec ultrasonic, DI rinse, N2 blow.
15. Nitride Etch Lithography
• Solvent clean ACE, ISO, DI and dehydration bake
• Spin on HMDS at 5000 rpm for 30 sec
• Spin on AZ 4210 photoresist at 5000 rpm for 30 sec
• Soft bake on 95°C hotplate for 65 sec
• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
• Mask exposure for 12 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:4 by volume) solution for 60-70 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
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16. SiN Etch for Contact Window
• RIE3 Chamber Clean with O2 = 20 sccm, 50 mTorr, 500V constant
voltage, 20 min
• Put monitor sample with SiN. Align the laser. Start the monitor program.
• Etch: O2 = 3 sccm, Ar = 10 sccm , SF6 = 5 sccm Etch Rate: ~370 A/min.
• Pressure = 20 mTorr Voltage = 250 V constant voltage. (Increase voltage
from 0 volt to 250 V).
• Etch in RIE #3. O2 20 sccm, 50 mT, 200V. 1-2 min to clean
• Strip resist with ACE
• Solvent clean: Acetone, Isopropanol, DI.
• Check in under microscope
• Do 02 plasma descum for 30 sec. (300 mT, 100W)
• Solvent clean
17. Thick Metal Lithography
• Solvent clean and dehydration bake
• Spin on HMDS at 3000 rpm for 30 sec
• Spin on AZ 5214 IR photoresist at 3000 rpm for 30 sec
• Soft bake on 95°C hotplate for 90 sec
• Edge bead exposure for 1min @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ 400K:DI (1:4 by volume) solution for 45 sec
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• Mask exposure for 23 sec @ 7.5 mW/cm2 intensity with blue filter
• Post bake on 105°C hotplate for 90 sec
• Flood exposure for 55 sec @ 7.5 mW/cm2 intensity w/o filter
• Develop in AZ400K:DI (1:5.5 by volume) solution for 30-35 sec
• DI rinse for 1 min, blow dry with N2
• Check the pattern under microscope
• O2 plasma descum (300 mT, 100W, low frequency) for 30 sec
• Post-bake in 90°C oven for 5 min
18. Thick Metal Metallization (Ti/Au)
• Load the samples into E-beam evaporator #1
• Use lowered boom to hold sample (thickness is 2 times larger)
• Evaporate the following metals after pumping below 1-2 10-6 Torr
• Ti (100 Å , evaporation rate less than 1.5-2 Å/sec)
• Au (1.2 µm evaporation rate ~10-20 Å/sec)
• Finish the liftoff in ACE
• Solvent clean and blow dry using N2