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31/03/2010 Spreading Excellence Report 1

HIGH PERFORMANCE AND EMBEDDED ARCHITECTURE AND COMPILATION

D3.6 SPREADING EXCELLENCE REPORT

March 31, 2010

PERIOD COVERED: FEBRUARY 01, 2009 – DECEMBER 31, 2009

FINANCIAL PERIOD COVERED: FEBRUARY 01,2009 – JANUARY 31, 2010

Grant Agreement no: ICT-217068


Note:

the text below is a copy from page 31 until 63 of the Periodic Project report

WP3: Spreading Excellence Program Coordinator: Chalmers, Per Stenström

An important aspect of a network of excellence is to create visibility for its members and for

the research carried out in the network, while at the same time integrating the network

members.

Improving the visibility of our community

The role of the Conference and Journal are to improve the scientific visibility in the area of

high-performance and embedded processors. They will help in the promotion of talented

young researchers by inviting them in the visible role of program committee member or

reviewer for the journal.

On top of this, publications at other major conferences will be stimulated through an original

Award program.

The Newsletter aims at publicising the activities of our community beyond the strict scientific

community: within industry, among public officials, and towards Asia, whose researchers

only infrequently participate in scientific forums at this moment. At the same time, it is a

means for promoting HiPEAC groups and achievements beyond the standard scientific

articles.

The HiPEAC Technical Reports

allow the rapid presentation and

dissemination of academic work,

time stamping hot research ideas,

and help showing the breadth and

scope of the HiPEAC community.

The Roadmap helps the HiPEAC

community to regularly revisit the

key scientific challenges, and it helps disseminating the HiPEAC vision beyond the HiPEAC

community.

Integrating our community

The Summer School aims at raising the standards of our PhD students and members by

confronting them with renowned teachers in our domains. It is also a networking event

resulting in long-lasting individual links among students, between students and faculty or

engineers, and among faculty and engineers.

The Web Seminars offers a continuous training cycle for the community, and they also offer

an opportunity for researchers, junior and senior alike, to publicise their activity within the

HiPEAC community and beyond, possibly triggering new collaborations. The industrial

workshops are networking events between academia and companies where the academics

learn more about the industrial challenges, and the industrial researchers are confronted with

the lastest academic research results.

Beyond the cooperation with large companies, we also aim at stimulating the development of

Start-ups by HiPEAC researchers.


Finally, the Web Site serves as a meeting place for all HiPEAC activities.

The Spreading Excellence Program consists of 11 specific tasks:

Task 3.1: Conference (Coordinator: Chalmers, Per Stenström) The conference is one of the main public events organized by the HiPEAC network. It is quite

successful, attracting a wide audience and offering high quality workshops and tutorials.

The topics called for in the conference and the workshops are the topics of the HiPEAC

research agenda as described in the research program. The conference and workshops are

completely open to both HiPEAC members and non-members from all over the world.

The conference is supervised by a steering committee, which decides on the chairs and the

location of the conference and reports to the HiPEAC steering committee. The logistics of the

conference are handled by the chairs, supported by the HiPEAC technical and administrative

staff.

HiPEAC 2010 Conference, Pisa, Italy The HiPEAC 2010 Conference took place in Pisa, Italy. It was organised by the University of

Pisa.

The Conference

The conference took place in the

“Palazzo dei Congressi di Pisa”. It

started with two days of tutorials and

workshops on January 23-24. The

conference itself started on January 25

and ends January 27.

Paper Acceptance Rate

The Program Committee, chaired by Paolo Faraboschi and Evelyn Duesterwald accepted 24

papers of 94 submitted. This corresponds to an acceptance rate of 25 %.

There are 10 accepted papers from the US. Other countries are the UK (3), Israel, Norway and

Spain (2). France, Greece, Switzerland, Germany and Russia have 1 accepted paper.

Conference Committee

The following people were involved in the organization of the conference:

General Chairs

Yale N. Patt UT Austin USA

Pierfrancesco Foglia Università di Pisa Italy

Program Chairs

Evelyn Duesterwald IBM T.J. Watson Research

Center

USA

Paolo Faraboschi HP Labs Spain

Program Committee.


Erik Altman IBM USA

Albert Cohen INRIA Saclay France

Jesus Corbal Intel Spain

Jack Davidson University of Virginia USA

Koen De Bosschere Ghent University Belgium

Jim Dehnert Google USA

Giuseppe Desoli STMicroelectronics Italy

Pedro C. Diniz Technical University of

Lisbon (IST) / INESC-ID

Portugal

Carol Eidt Microsoft USA

Babak Falsafi EPFL Switzerland

Georgi Gaydadjiev TU Delft The Netherlands

Thomas Gross ETH Zurich Switzerland

Rajiv Gupta Univ. of California USA

Mary Jane Irwin Penn State University USA

Wolfgang Karl Karlsruhe Institute of

Technology (KIT)

Germany

Josep Llosa UPC Spain

Scott Mahlke University of Michigan USA

Sally A. McKee Chalmers University of

Technology

Sweden

Avi Mendelson Microsoft Israel Israel

Michael O'Boyle University of Edinburgh United Kingdom

Daniel Ortega HP Labs Spain

Emre Ozer ARM United Kingdom

Keshav Pingali UT Austin USA

Milos Prvulovic Georgia Tech USA

Cristina Silvano Politecnico di Milano Italy

David Whalley Florida State University USA

Donald Yeung University of Maryland USA

External Review Committee

Eduardo Argollo HP Spain


Hans Boehm HP Spain

Rajesh Bordawekar IBM USA

Greg Bronevetsky Lawrence Livermore

National Lab

USA

Anton Chernoff AMD USA

Bruce Childers University of Pittsburgh USA

Dave Christie AMD USA

Tom Conte Georgia Tech USA

Al Davis University of Utah USA

Chen Ding University of Rochester USA

Amer Diwan University of Colorado USA

Jose Duato UPV Valencia Spain

Lieven Eeckhout Ghent University Belgium

Ayose Falcon HP Spain

Hubertus Franke IBM USA

Maria Garzaran UIUC USA

Roberto Gioiosa IBM Spain

Wei Hsu University of Minnesota USA

Michael Huang University of Rochester USA

Robert Hundt Google USA

Paolo Ienne EPFL Switzerland

Ravi Iyer Intel USA

Mahmut Kandemir Penn State University USA

Steve Keckler UT Austin USA

Mikko Lipasti University of Wisconsin USA

Gabriel Loh Georgia Tech USA

Grant Martin Tensilica USA

Frank Mueller NC State USA

Walid Najjar University of California

Riverside

USA

Nacho Navarro UPC and BSC Spain


Kevin O'Brien IBM USA

David Penry Brigham Young University USA

Luigi Raffo University of Cagliari Italy

Partha Ranganathan HP USA

Erven Rohou INRIA France

Yannakis Sazeides University of Cyprus Cyprus

Andre Seznec IRISA France

Uma Srinivasan Intel USA

Per Stenstrom Chalmers University Sweden

John Stratton UIUC USA

Olivier Temam INRIA France

Osman Unsal BSC Spain

Manish Vachharajani University of Colorado USA

Neil Vachharajani Google USA

Sami Yehia Thales France

Cliff Young DE Shaw Research USA

Antonia Zhai University of Minnesota USA

Workshops/Tutorials Chair

Sandro Bartolini Università di Siena Italy

Finance Chair

Wouter De Raeve Ghent University Belgium

Local arrangement Chair

Alessandro Bardine Università di Pisa Italy

Publicity Chair

Roberto Giorgi Università di Siena Italy

Publications Chair

Xavier Martorell BSC Spain

Submissions Chair

Michiel Ronsse Ghent University Belgium

Web Chair

Klaas Millet Ghent University Belgium


Steering Committee

Anant Agarwal MIT USA

Koen De Bosschere Ghent University Belgium

Joel Emer Intel USA

Wen-mei W. Hwu UIUC USA

Margaret Martonosi Princeton University USA

Michael O’Boyle University of Edinburgh U.K.

André Seznec IRISA France

Per Stenstrom Chalmers University Sweden

Theo Ungerer University of Augsburg Germany

Mateo Valero UPC Spain

Conference Program

Mon Jan 25

Opening/ welcome

Keynote 1 Embedded System as

Datacenter

Bob Iannucci, CEO and Co-founder, Sensaré

LLC

Break

Session 1

Architectural Support for

Concurrency Chair: Avi Mendelson, Microsoft Israel

Remote Store

Programming: Mechanisms

and Performance

Henry C. Hoffmann (MIT), David Wentzlaff

and Anant Agarwal (Tilera)

Low-overhead, High-speed

Multi-core Barrier

Synchronization

John Sartori and Rakesh Kumar (Univ. of

Illinois)

Improving Performance by

Reducing Aborts in

Hardware Transactional

Memory

Mohammad Ansari, Behram Khan, Mikel

Lujan, Christos Kotselidis, Chris Kirkham, and

Ian Watson (Univ. of Manchester)


Energy and Throughput

Efficient Transactional

Memory for Embedded

Multicore Systems

Cesare Ferri (Brown University), Samantha

Wood (Bryan Mawr College), Tali Moreshet

(Swartmore College), Iris Bahar, and Maurice

Herlihy (Brown University)

Lunch

Session 2

Compilation and Runtime

Systems Chair: Carol Thomson Eidt, Microsoft

Split Register Allocation:

Linear Complexity Without

the Performance Penalty

Boubacar Diouf, Albert Cohen (INRIA),

Fabrice Rastello (ENS Lyon), and John

Cavazos (Univ. of Delaware)

Trace-Based Data Layout

Optimizations for Multi-

Core Processors

Olga Golovanevsky, Alon Dayan, Ayal Zaks

(IBM Israel) and David Edelsohn (IBM)

Buffer sizing for self-timed

stream programs on

heterogeneous distributed

memory multiprocessors

Paul Carpenter, Alex Ramirez and Eduard

Ayguade (BSC Barcelona)

Automatically tuning sparse

matrix-vector multiplication

for Alexander Monakov and Arutyun Avetisyan

(Russian Academy of Science), Anton

Lokhmotov (Imperial College London)

GPU architectures

Break

Session 3

Reconfigurable and

Customized Architectures Chair: Cristina Silvano, Politecnico di Milano

Virtual Ways: Efficient

Coherence for

Architecturally Visible

Storage in Automatic

Instruction Set Extensions

Samuel Burri, Theo Kluter, Philip Brisk,

Edoardo Charbon and Paolo Ienne (EPFL

Lausanne)

Accelerating XML query

matching through custom

stack generation on FPGAs

Roger Moussalli, Mariam Salloum, Walid

Najjar, and Vassilis Tsotras (Univ. of

California Riverside)

An Application-aware Load Rainer Ohlendorf, Michael Meitinger, Thomas


Balancing Strategy for

Network Processors

Wild, and Andreas Herkersdorf (TU Munich)

Memory-Aware

Application Mapping on

Coarse Grain

Reconfigurable Arrays

Yongjoo Kim, Jongeun Lee, Aviral

Shrivastava, Jonghee Yoon, and Yunheung

Paek (Arizona State Univ.)

Tue Jan 26

Keynote 2

Larrabee: A Many-Core

Architecture for Visual

Computing

Roger Espasa, Principal Engineer, Intel

Break

Session 4

Multicore Efficiency,

Reliability and Power Chair: Thomas Gross, ETH Zuerich

Maestro: Orchestrating

Lifetime Reliability in Chip

Multiprocessors

Shuguang Feng, Shantanu Gupta, Amin

Ansari, and Scott Mahlke (Univ. of Michigan)

Combining Locality

Analysis with Online

Proactive Job Co-

Scheduling in Chip

Yunlian Jiang, Kai Tian, and Xipeng Shen

(College of William and Mary)

RELOCATE: Register File

Local Access Pattern

Redistribution Mechanism

for Power and Thermal

Management in Out-of-

Order Embedded

Processors

Houman Homayoun, Aseem Gupta, Alex

Veidenbaum, and Fadi Kurdahi (Univ. of

California Irvine)

Performance and Power

Aware CMP Thread

Allocation Modeling

Yaniv Ben-Itzhak, Israel Cidon, and Avinoam

Kolodny (Technion Israel)

Lunch

Panel "Heterogenous vs.

Homogenous Computing"

Yale Patt (UT Austin), Roger Espasa (Intel),

Hank Hoffmann (Tilera/MIT), Walid Najjar

(UC Riverside)


Moderator: Paolo

Faraboschi, HP Labs

Guided Pisa Tour

Banquet

Wed Jan 27

Session 5

Memory Organization and

Optimization Chair: Jim Dehnert, Google

Multi-Level Hardware

Prefetching using Low

Complexity Delta

Correlating Prediction

Tables with Partial

Matching

Marius Grannaes, Magnus Jahre and Lasse

Natvig (Norwegian Institute of Science and

Technology)

Scalable Shared Cache

Management by Containing

Thrashing Workloads

Yuejian Xie and Gabriel H. Loh (Georgia

Tech)

SRP: Symbiotic Resource

Partitioning of the Memory

Hierarchy in CMPs

Shekhar S. Srikantaiah and Mahmut T.

Kandemir (Penn State University)

DIEF: An Accurate

Interference Feedback

Mechanism for Chip

Multiprocessor Memory

Systems

Magnus Jahre, Marius Grannaes and Lasse

Natvig (Norwegian Institute of Science and

Technology)

Break

Session 6

Programming and Analysis

of Accelerators Chair: Albert Cohen, INRIA

Tagged Procedure Calls

(TPC ): Efficient runtime

support for task-based

parallelism on the Cell

Processor

George Tzenakis, Konstantinos Kapelonis,

Michail Alvanos, Konstantinos Koukos,

Dimitrios Nikolopoulos, and Angelos Bilas

(FORTH, Greece)


Analysis of Task

Offloading for Accelerators

Roger Ferrer, Vicen Beltran (BSC Barcelona),

Marc Gonzalez, Xavier Martorell (UPC

Barcelona), and Eduard Ayguade (BSC

Barcelona)

Offload -- Automating code

migration to heterogeneous

multicore systems

Pete Cooper, Uwe Dolinsky (Codeplay),

Alastair F. Donaldson (Oxford Univ.), Andrew

Richards, Colin Riley, and George Russell

(Codeplay)

Computer Generation of

Efficient Software Viterbi

Decoders

Frederic de Mesmay, Srinivas Chellappa,

Franz Franchetti, and Markus Pschel (Carnegie

Mellon Univ.)

Closing/

awards

Attendance

238 people attended the conference or workshops. 50 of those were from industry,

representing 34 companies.

The country distribution is as follows:

Belgium 11

Brazil 1

Canada 1

China 3

Cyprus 7

Denmark 1

Finland 1

France 26

Germany 13

Greece 6

Ireland 2

Israël 11

Italy 31

Japan 2

Korea (South) 6

Norway 5


Poland 1

Portugal 2

Romania 1

Russia 3

Singapore 1

Spain 30

Sweden 9

Switzerland 4

The Netherlands 11

Turkey 4

USA 34

United Kingdom 15

Of the 238 attendants, there were 57 members, 26 affiliated members and 27 PhD students

with linkage to HiPEAC.

Student Grants

Only 20 student grants were requested. All of them were granted.

Workshops and Tutorials

In 2009 in Cyprus 7 workshops and 1 tutorial were organised on 1 day.

Due to the increased interest and activity, we decided to organise the workshops and tutorials

as a 2-day event.

We now host 8 workshops and 5 tutorials.

This is the program for the workshops and tutorials:

Saturday January 23rd

o (Workshop) Workshop on Computer Architecture and Operating System co-

design (CAOS)

o (Workshop) GCC Research Opportunities Workshop (GROW)

o (Workshop) Interconnection Network Architectures: On-Chip, Multi-Chip

(INA-OCMC) - part 1/2

o (Workshop) Workshop on Reconfigurable Computing (WRC)

o (Tutorial) Networks-on-chip: the New Frontier for Interconnection Networks

Sunday January 24th

o (Workshop) Interconnection Network Architectures: On-Chip, Multi-Chip

(INA-OCMC) - part 2/2

http://caos.ac.upc.edu/

http://caos.ac.upc.edu/

http://ctuning.org/workshop-grow10

http://polimage.polito.it/~lajolo/wina10.html


http://ce.et.tudelft.nl/HiPEACRC_WS/

http://polimage.polito.it/~lajolo/noc-tutorial-short.htm




o (Workshop) Workshop on Rapid Simulation & Performance Evaluation:

Methods and Tools (RAPIDO)

o (Tutorial) Speedup-Test: Towards Statistical Methodology to Evaluate

Program Speedups and their Optimisation Techniques

o (Tutorial) Adaptability: the Key for Future Embedded Systems

o (Workshop) Workshop on Statistical and Machine learning approaches to

ARchitecture and compilaTion (SMART)

o (Workshop) Workshop on the Design for Reliability (DFR)

o (Tutorial) Teaching Introductory Computer Architecture and Programming:

What, When, How?

o (Tutorial) Programming FPGA-Based Accelerators using ROCCC 2.0

o (Workshop) Workshop on Programmability Issues for Multi-Core Computers

(MULTIPROG)

Progress indicators: # submitted papers: 94

# accepted papers: 24

# workshops/tutorials: 8/5

# participants: 238

http://www2.lifl.fr/rapido/

http://www2.lifl.fr/rapido/

http://www.hipeac.net/conference/pisa/speedup

http://www.hipeac.net/conference/pisa/speedup

http://www.hipeac.net/conference/pisa/adaptability

http://ctuning.org/workshop-smart10

http://ctuning.org/workshop-smart10

http://www.ece.ucy.ac.cy/labs/easoc/DFR/

http://www.hipeac.net/conference/pisa/icap

http://www.hipeac.net/conference/pisa/icap

http://www.hipeac.net/conference/pisa/roccc

http://multiprog.ac.upc.edu/

http://multiprog.ac.upc.edu/


Task 3.2: Summer School (Coordinator: Ghent, Koen De Bosschere)

The successful international ACACES Summer School continues to be one of the most

attractive events organised by HiPEAC.

The International Summer School on Advanced Computer Architecture and Compilation for

Embedded Systems is open to a wide audience, while we keep a balance between country,

senior-junior, gender and industry-academia.

The Summer School programme consists of a combination of courses on the different topics

covered by the HiPEAC research agenda. This is guaranteed by letting the different HiPEAC

clusters suggest the best possible teachers for their own topic. This list of teachers is

supplemented by topics considered to be of general interest to the whole network (e.g.,

dealing with cross-cutting concerns like power, reliability, …). The teaching staff consists of

academics and industrial researchers, Europeans and non-Europeans alike. Former Summer

School teachers normaly keep their links with the cluster that proposed them (as associate

member).

Besides the courses, we organise a poster session where the PhD-students can present their

own research to the other participants of the school. This is an excellent networking event for

the young PhD students, which can lead to extra research ideas and contacts.

During this poster session, we take the opportunity to present our network, and related FP6

and FP7-projects. Every project representative is available to give more information about

their project.

5th International Summer School – 2009

The Summer School

Due to the events in the city of L’Aquila, Telecom Italia Learning Services (TILS) was not

able to host us at their site in L’Aquila. In the meantime we learned that this will not be

possible in the future either. An alternative location was found in the area of Barcelona, at the

La Mola Conference Centre in Terrassa in Spain.

Location

It is a high quality and professional environment that provides an unique location to host our

event.

It offers spacious classrooms, as well as possibilities for extra meetings and interaction.


Summer School Program

The Summer School program consists of 12 courses, covering the research domains our

network is focused on.

Apart from the courses, the Summer School also offers a keynote speech, as wel as an invited

talk from industry. We adjust the program’s focus based on the feedback we receive from the

participants.

The 2009 Summer School courses where:

Lecturer Course title

Slot 1 David Albonesi Power- and Reliability-Aware Microarchitecture

Walid Najjar Opportunities and Challenges of Reconfigurable Computing

Peter Puschner WCET Analysis: Problems, Methods, and Time-Predictable

Architectures

Slot 2 Jaejin Lee Compilers and Runtimes Support for Explicitly Managed

Memory Hierarchies

Radu Marculescu Networks-on-Chip: Why, What, and How?

Paul McKenney Performance, Scalability, and Real-Time Response From the

Linux Kernel

Slot 3

David Wood Transactional Memory

Grant Martin Practical System-Level Design Methodologies for Processor-

Centric SoC and Embedded Systems

Kim Hazelwood Process Virtualization and Symbiotic Program Optimization

Slot 4

Bruce Jacob Embedded Systems, Memory Systems, and Embedded

Memory Systems

J. (Ram) Ramanujam Optimizations for multicore and GPGPU architectures

Lieven Eeckhout Performance Evaluation and Benchmarking

The keynote was given by Steve Furber (University of Manchester). It was titled

“Computing beyond a million processors- bio-inspired massively parallel architectures”.

The invited talk was given by Alasdair Rawsthorne (former CTO and founder of

Transitive), titled “How to Survive A Startup - from University Research to

Multinational - a Highly Personal View”. The topic and speaker were chosen as part of

the initiative to promote start-ups in the HiPEAC network.

Poster session

On Wednesday afternoon, the yearly poster session was held. This poster session gives PhD

students the opportunity to present and discuss their work with fellow students or with the

senior researchers and teachers present at the Summer School.

The increasing number of posters displayed shows the appreciation of the PhD students for

this event. 92 posters were presented during the afternoon.

Attendance

For the 2009 edition, we received 316 applicantions.


When selecting the participants, our focus is to maximise the goals of the network, and to

balance the audience.

Selection criteria are:

Gender: we stimulate female attendance to improve the gender-balance;

Affiliation: all industry applicants are accepted in order to increase industry

participation;

Country: we try to get a maximum number of different nationalities in order to make it

a truly international event;

Experience: our goal is to have an optimal mix of senior researchers and young phd-

students and postdocs. PhD-students who never attended the summer school have

priority over students who have attended a previous edition.

Eventually, we admitted 219 participants.

The attendance-breakdown was as follows.

Industry attendance

We had 25 participants coming from 11 different companies:

ARM

ESA ESTEC

ST Microelectronics

Floralis

IBM

Intel

NXP

Tensilica

Thales Research & Technology

T-Mobile

Vector Fabrics

During the Summer School, there was a industry meeting on the SWOT analysis for

computing systems in Europe, chaired by the HiPEAC roadmap coordinator. This event

gathered the input of 25 company people, giving the view of 11 companies.

Additionally, Intel organised a special and well-attended tutorial on their tools for the

applicants.

Gender balance

26 out of 219 attendants were female. All female applicants were admitted and female

students that request a grant have priority over other students.


Members/non-members

104 of the people who attended the summer school are members or affiliated members:

22 members

69 HiPEAC PhD students

11 affiliated members

2 staff members

Summer School Grants

112 students applied for a student grant. The student grant waves the registration fee. 55

students were given a grant.

Feedback

Every year we ask all Summer School participants for feedback on the Summer School

through an extensive survey. 150 People, or 69% filled in the survey. All scales go from 0 to

5; with 5 indicating the highest score.

Organisation

The administration (admission, registration, payment) 4.5

The website (organisation, content) 4.3

The course schedule (1 week, 4 slots, 12 courses) 4.4

The location (La Mola) 4.0

Shuttle busses (Terrassa - La Mola) 4.0

The course material (booklets) 4.1

Price/quality (1200 euro, all-in, full week) 3.9

Period (third week of July) 4.2

The organisation was highly appreciated.

The location and price were rated a bit lower than last year. Due to the very late organisation

and the new facility this was to be expected. As we did not know the facility we couldn’t

completely tune our format with the center.

This also showed in the comments:

Reduced possibility for networking

Difficult to reach due to limited train service

Less interaction with the teachers

We have taken these things into account and are negotiating with La Mola to see how we can

improve on these comments.

The program

The course offering 4.1

The keynote talk on Sunday evening 3.9


The invited talk on Monday evening 3.8

The poster session 4.1

All aspects of the program were rated highly. We continue to try to offer an attractive

program and interesting speakers.

Overall appreciation

Would you recommend ACACES to a colleague? 4.7

Will you come back next year? 4.3

We were happy to see that people who filled out the survey were very eager to recommend

the Summer School to their colleagues. The high score for the second question shows that

there is great interest to attend the Summer School more than once.

Course evaluation

Co

urs

e

Tea

cher

Ov

eral

l

Rec

om

man

dat

ion

Av

erag

e Walid Najjar 4.2 4.4 4.3 4.3 4.3

Kim Hazelwood 4.2 4.4 4.3 4.2 4.3

David Wood 4.4 4.4 4.3 4.6 4.4

Paul McKenney 4.3 4.3 4.3 4.1 4.3

Bruce Jacob 4.1 4.3 4.2 4.0 4.2

David Albonesi 4.1 4.1 4.2 4.3 4.2

Peter Pushner 4.1 4.1 4.0 4.1 4.1

Lieven Eeckhout 4.0 4.1 4.0 3.8 4.0

Radu Marculescu 4.0 4.1 4.0 4.8 4.2

Jaejin Lee 4.0 4.0 3.8 3.8 3.9

Grant Martin 3.7 3.9 3.7 3.9 3.8

J. (Ram) Ramanujam 3.3 3.5 3.3 3.6 3.4

All courses were evaluated high to very high. The result of the evaluation forms was sent to

the respective teachers, including the detailed comments.

Progress indicators: #applicants: 316


# participants: 219

# participants from industry: 24

# senior participants: 71


Task 3.3: Journal (Coordinator: Chalmers, Per Stenström)

The HiPEAC Journal was first published in 2006.

The fourth volume of the journal received 21 submissions, of which 15 were accepted for

publication.

Accepted papers

Volume 4 accepted the following papers:

A High Performance Adaptive Miss

Handling Architecture for Chip

Multiprocessors. T

Magnus Jahre, Lasse Natvig

Characterizing Time-Varying Program

Behavior using Phase Complexity Surfaces

Frederik Vandeputte, Lieven Eeckhout

Compiler Directed Issue Queue Energy

Reduction

Timothy M. Jones, Michael F.P. O’Boyle,

Jaume Abella, and Antonio González

A Highly Scalable Parallel Implementation

of H.264

Arnaldo Azevedo, Ben Juurlink, Cor

Meenderinck, Andrei Terechko, Jan

Hoogerbrugge, Mauricio Alvarez, Alex

Ramirez, Mateo Valero

Communication Based Proactive Link Power

Management

Sai Prashanth Muralidhara, Mahmut

Kandemir

Finding Extreme Behaviors in

Microprocessor Workloads

Frederik Vandeputte, Lieven Eeckhout

Tiled Multi-Core Stream Architecture Nan Wu, Qianming Yang, Mei Wen, Yi He,

Ju Ren, Maolin Guan, Chunyuan Zhang

An Efficient and Flexible Task Management

for Many Cores

Yuan Nan, Yu Lei, Fan Dong-rui

Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb,

and Shuvra S. Bhattacharyya

Advanced Packet Segmentation and

Buffering Algorithms in Network Processors

Daniel Llorente, Kimon Karras, Thomas

Wild and Andreas Herkersdorf

A Systematic Design Space Exploration

Approach to Customising Multi-Processor

Architectures: Exemplified using Graphics

Processors

Ben Cope, Peter Y.K. Cheung, Wayne Luk

and Lee Howes

On Two-layer Brain-inspired Hierarchical Valeriu Beiu, Basheer A.M. Madappuram,


Topologies – A Rent’s Rule Approach Peter M. Kelly, and Liam J. McDaid

Signature-based Calibration of Analytical

Performance Models for System-level

Design Space Exploration

Stanley Jaddoe, Mark Thompson, and Andy

D. Pimentel

A Cost Model for Partial Dynamic

Reconfiguration

Markus Rullmann and Renate Merker

Reduction by Systematic Run-Time

Reconfigurable Hardware Deactivation

W.G. Osborne, W. Luk, J.G.F. Coutinho and

O. Mencer Energy

Future Work

In order to increase the prestige and visibility of the journal, we think it is essential to make it

available in visible digital libraries such as the ones provided by ACM (ACM DL) or IEEE

(IEEExplore). To this end, we contacted representatives at the ACM publication board who

brought up the case at the agenda for its October 30, 2009 meeting.

The view of the board is that the HiPEAC journal is overlapping too much with the scope of

some of the ACM Transactions, in particular (TACO and TECS). Unless we make a case that

the scope of the HiPEAC journal complements that of TACO and TECS, it will be very

difficult for the ACM publication board to approve it. TACO addresses architecture and

compiler topics but not so much embedded. TECS addresses embedded systems in general but

not so much architecture and compilers.

If we can make the case that the HiPEAC journal addresses the gap between them, the ACM

pubs board may reconsider. We will pursue this route in the short-term. Another option we

want to explore is to make a similar proposition to IEEE. The scope of the HiPEAC journal

would have less or no overlap with any IEEE Transactions.

Progress indicators: #submitted papers: 21

# accepted papers: 15

Task 3.4: Roadmap (Coordinator: NXP, Marc Duranton)

The first HiPEAC roadmap was published in 2007. In 2009, the second version of the

roadmap has been published. The roadmap is a separate deliverable, and contains all details

about the roadmap process.

The "HiPEAC Vision" is the first deliverable of this HiPEAC activity. This document

presents the vision of the HiPEAC community on the future of High Performance and

Embedded Architectures and Compilers, and also preliminary recommendations. This

document will be updated in 2010-2011 to realize the complete "roadmap" with the active

help of the clusters.

The final version of the document was delivered to the Commission by September 2009, and

an improved formatted version will be available for wide distribution during the HiPEAC

conference in January 2010. The editorial board of the roadmap is also working in a

summarized version to be published in Communications of the ACM journal.

The document is the results of various consultations and workshops (with people not

necessarily in the network), and interaction with the clusters. It started in 2008 by a survey


that was sent to all the HiPEAC clusters and task forces. The clusters discussed the survey at

the spring cluster meeting, and during the ACACES 2008 summer school, the industrial

participants and the teachers of the school held a brainstorming session based on this report.

All this resulted in about 100 pages of raw material which is the starting point of the current

document.

During a first one-day brainstorm session in Ghent on December 16th, 2008, all material was

analyzed and structured. This initial version was presented to the HiPEAC community during

the HiPEAC general assembly following the HiPEAC 2009 conference in Paphos, and

feedbacks were collected. During a second one-day brainstorm in Ghent on February 11th,

2009, the document was further improved and discussed by the HiPEAC steering committee

during the HiPEAC1 review on March 20 in Barcelona. In the meantime, this material was

analyzed, restructured, complemented and shaped during several workshops and

teleconferences, and through numerous emails exchanges and updates of the document by

members of the HiPEAC community, under the supervision of an editorial board. Further

improvements coming from the steering committee members were incorporated after the

HiPEAC2 review 5th of June. A "token based" approach was used, allowing volunteers to

update the documents (with track change on) during a period of time were the document was

allocated exclusively. The modifications were analyzed and approved by the editorial board.

The ACACES 2009 gave the opportunity to the industry participants and the teachers to

brainstorm about the Strengths, Weaknesses, Opportunities and Threats that Europe is facing

in the domain of Information & Communication Technology. The results were analyzed and

complemented to form section 6 of the document, leading to recommendations. Two meeting

were held during ACACES, on July 14th and on July 15th for the industrial meeting where 38

attendees, including committee members, industrial members and teachers, improved the

content.

The vision was presented several times during 2009, in various contexts, during the

Computing Systems consultation meetings of 16-17 November 2009, at a workshop of the

ARCS conference, at the university of Bochum, at the ARTIST_Design summer school.

Task 3.5: Newsletter (Coordinator: RWTH Aachen, Rainer Leupers)

The newsletter workgroup is currently preparing the 21st issue. The issues are printed

quarterly and mailed around the world.

The newsletter also serves as a dissemination tool to present the HiPEAC start-ups. It also

provides room for members and students who received a grant (either for a mini-sabbatical, a

collaboration grant or an internship) to report on their activities.

The volume of the newsletter has grown from an average of 12 pages to 16-20 pages.

All members automatically receive the quarterly newsletter.

Period 2 issues

During the reporting period, 3 issues of the HiPEAC newsletter were printed:

Issue 18: April 2009

Message from the HiPEAC coordinator

Message from the project officer

HiPEAC Activity:


o SDR Pioneers visited SoC 2008

o Technology Transfer: A New Methodology

o Joint Computer Architecture Seminar: RWTH

Aachen University and University of Edinburgh

o Release of DDG version 2.0

o CUDA Seminar at the University of Patras

Community News

o Load Balancing for Mobile Devices

o NAccess to the Collective Optimization Database

o Best paper Award: 1st Data Prefetching

Championship, HPCA-15

o Sabbatical: Enrique F. Torres

Guest Column: Agnieszka Skotarczyk, Microtech International S.A.

HiPEAC Students and Trip Reports

in the Spotlight:

o EC FP7 CRISP Project

PhD News

Upcoming Events

This issue was sent to 733 subscribers.

Issue 19: July 2009



HiPEAC Activity:

o HiPEAC sets flag at DATE 2009

o HiPEAC 2010 Conference

o Static Single-Assignment Form Seminar in France

o HiPEAC Computing Systems Week in Munich

Community News:

o Best Paper Award: Design Automation and Test in

Europe (DATE)

o HiPEACinfo Staff Changes

o Announcing the Open Source Release of TTA-

Based Codesign Environment 1.0

o HiPEAC Mini-sabbatical Program

Member Profile:

o ACE Associated Compiler Experts bv

o Professor Thomas Fahringer, University of

o Innsbruck, Austria

HiPEAC Start-ups:

o Sigasi Enters EDA Market with Public Beta Program

HiPEAC Students

PhD News

Upcoming Events

This issue was sent to: 749 subscribers (+16).


Issue 20: October 2009



o HiPEAC Activity:

o HyperTransport Tutorial at Stanford University

o Rainer Leupers on his mini-sabbatical at ACE bv

o Joint Seminar: RWTH Aachen University visits

FORTH

Community News:

o Gadgets could go greener with high-speed computer

chip

o Newsletter spell checking transition

o Ozcan Ozturk received the IBM Faculty Award

Announcement:

o ALaRI institute invites to attend Doctoral School on

Complexity Management in Embedded Systems

In the Spotlight:

o 9th International Forum on Embedded MPSoC and Multicore (MPSoC 2009)

New HiPEAC Member:

o RuChip, Russian startup in Moscow

HiPEAC Students and Trip Reports

PhD News

Upcoming Events

This issue was sent to 839 subscribers (+106).

Progress indicator: # subscriptions: 733/749/839

Task 3.6: Technical reports (Coordinator: DELFT, Georgi Gaydadjiev)

This task comprises a publication database and a time stamping service for technical reports.

Publication database

This database is a list of all publications by HiPEAC members and affiliates. While the

database is mostly automatically generated, users have the possibility to add publications

manually or by requesting changes to existing publications.

These publications are unfortunately not all directly related to HiPEAC work. It is therefore

the task of the cluster coordinators to select those publications that present an accurate

overview of cluster and task force activities. An easy-to-use interface was created to facilitate

this process.

Our database currently holds 3570 publications, from 2006 on, which are publicly visible at

the HiPEAC website.

Tech Reports

This service offers HiPEAC members the possibility to time stamp ideas prior to publication

even when only very preliminary results are available in support of the main claim and to

share early ideas that will advance the HiPEAC research field. It is a zero overhead service

allowing HiPEAC members to time stamp any document of interest. The submitted

documents are NOT be reviewed. The responsibility for the technical content, its originality


and soundness remains with the document author as well as the document copyrights. One can

consider this process as publishing technical reports at his/hers own organization, hence the

alternative service name “HiPEAC Technical reports”.

Submission in “HiPEAC Technical Reports” does not preclude subsequent publication in

conferences or journals. In contrary we believe that the HiPEAC time stamped reports will

eventually result in one or more high-quality scientific publications when all of the

experimental work is completed. The focus of this service is early time stamping of novel

work. If the work is already mature enough to be submitted as normal paper at any venue, the

author is strongly advised to consider that option. This is of course only a general suggestion.

For each time stamped document, a unique sequence number is automatically generated after

submission (e.g., TR-HiPEAC-0001, TR-HiPEAC-0002 etc.). During the submission process,

the author is asked to indicate whether the content of the submitted document is to be made

publicly available or not. In the first case, everyone will have read access (this means

members AND people outside the HiPEAC network). Otherwise only the document author

(HiPEAC logged in member) will have a read-only access. In that case, the author is supposed

to provide a short abstract summarizing the document content.

Since the review in Munich, the Tech Report service has become fully functional.

The timestamping technology is provided by Timestamp, Inc. (http://www.digistamp.com/)

which provides the following service: a digital time stamp gives you unequivocal proof that

the contents of any data file existed at a point-in-time and that the contents have not changed

since that time.

The time stamping service was announced to the HiPEAC members in October 2009.

Currently it has not yet been used by the members.

Progress indicators:

# reports published: 1

# reports downloaded: 0

Task 3.7: Web Site

The HiPEAC web site is the most important instrument for HiPEAC’s internal and external

communication. It serves both as an extranet to disseminate information, as an intranet to

disseminate research information among participants, and to provide the members and

affiliates with the necessary information and tools. Several services have been added during

the last year: the reimbursement service, the registration system for meetings, membership

management, a publication database, the membership services, a reorganisation of the mailing

lists, ...

In 2009 the website received a whole new interface and structure to make it visually more

attractive and informative for the users.

Developments/New features

During the second reporting period, the following changes to the website have been made

Instructors list

The websit now keeps a list of instructors teaching HiPEAC related topics in Europe. A new

address book has been implemented. The instructor list currently has 351 instructors. These

instructors can opt to receive the HiPEAC newsletter and HiPEAC public mails.


Summer School website

Due to the new physical location (La Mola), some aspects of the website had to be

redesigned. For next year the summer school website will be integrated as an integral part of

the HiPEAC website.

Conference website integration

Previously the conference website was managed as a separate website. We decided to

integrate the conference website with the HiPEAC website. While still allowing to have it’s

own theme and focus, the integration allows for easier registration and management. For

example people only have to register once (at the main website) to be able to register for the

conference. Moreover, this facilitates the tracking of the progress indicators. It will also be

easier to create future conference websites.

Tools section

The website now hosts a tools section, which contains relevant tools which can be used by the

community. All tools are related to the HiPEAC members. Currently there are 9 tool

descriptions available.

Industry section

The industry section is redesigned using feedback from the industry partners. Every company

has its personal page which offers it the possibility to announce news, events, calls, job

opportunities… It will also offer the reports on the industry-related HiPEAC activities.

The new section is part of the plan to make the HiPEAC website more attractive to industry.

Cluster website

Several cluster websites are have been redesigned in order to improve the quality and

attractiveness.

Website statistics

Since February 2008, we use Google Analytics to keep track of the website visits and data.

The most important metrics will be discussed.

Visitors Report

In the period from January 1st until December 31

st, Google reports the following statistics.

Visits 76 191

Unique visitors 41 862

Page Views 274 394

Avg Pages/visit 3.60


New visits 54,90%

The visitors come from 160 different countries:

United States 10.402 20.15%

Spain 6.158 11.93%

India 5.971 11.57%

Germany 5.411 10.48%

Belgium 4.907 9.51%

United Kingdom 4.801 9.30%

France 4.547 8.81%

Netherlands 3.651 7.07%

Greece 3.005 5.82%

Italy 2.765 5.36%

The numbers are in line with our expectations, except for the high number of visitors from

India. This might be students looking for good places to study.

The numbers also show we have a high percentage of new visitors.

Content

The most visited pages are (except from the homepage):

Internship pages

Journal page

Memberslist

Job Page

Research page


Registrations

Since February 2009 we received 359 new registrations to the website.

Progress indicators: # hits: 274 394

# new registrations: 359

Task 3.8: Web Seminars (Coordinator: BSC, Mateo Valero) The goal of these joint seminars is to increase integration of different research groups by

enabling frequent interaction, and facilitate presentations of their research work.

Recorded Web Seminars

Since February 2009, the following seminars were recorded:

Dec 2nd 2009, Portable, Scalable, per-Core Power Estimation for Intelligent Resource

Management Sally A. McKee (Chalmers University)

(hit count: 9)

Oct 26th 2009, Efficient Resource Management for Large Scalle Parallelism Christos

Kozyrakis (Stanford University)

(hit count: 31)

Oct 22nd 2009, Chapel, the Cascade High-Productivity Language Brad Chamberlain

(Cray)

(hit count: 8)

Oct 6th 2009, Parallel Computing in Pisa: Structured Parallel Programming, Fault

Tolerance, Adaptivity and Dynamicity Carlo Bertolli (University of Pisa)

(hit count: 18)

May 28th 2009, Fault injection attacks on cryptographic devices and countermeasures

Israel Koren (Umass Amherst)

(hit count: 25)

April 14th 2009, Two recent works on power and thermal-aware load-balancing

techniques for massive multi-core architectures Enric Musoll (Consentry)

(hit count: 60)

March 4th 2009, Caches In the Many-Core Era Hillery Hunter (IBM) (no data

available)

During the same period last year, we had 3 recorded seminars. Also the amount of downloads

has gone up significantly (from 7-20 last year to 8-60 this year).


# seminars: 7

# downloads: 60/25/18/8/31/9/-

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Portable,_Scalable,_per-Core_Power_Estimation_for_Intelligent_Resource_Management

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Portable,_Scalable,_per-Core_Power_Estimation_for_Intelligent_Resource_Management

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Efficient_Resource_Management_for_Large_Scale_Parallelism

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Chapel,_the_Cascade_High-Productivity_Language

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Parallel_Computing_in_Pisa._Structured_Parallel_Programming,_Fault_Tolerance,_Adaptivity_and_Dynamicity

http://recerca.ac.upc.edu/HPCseminar/SEM0910/abs.html#Parallel_Computing_in_Pisa._Structured_Parallel_Programming,_Fault_Tolerance,_Adaptivity_and_Dynamicity

http://recerca.ac.upc.edu/HPCseminar/SEM0809/abs.html#Fault_injection_attacks_on_cryptographic_devices_and_countermeasures

http://research.ac.upc.edu/HPCseminar/SEM0809/abs.html#_Hardware-based_load_balancing_for_massive_multi-core_architectures_implementing_power_gating__and__Trading_off_higher_execution_latency_for_increased_reliability_in_tile-based_massive_multi-core_architectures_

http://research.ac.upc.edu/HPCseminar/SEM0809/abs.html#_Hardware-based_load_balancing_for_massive_multi-core_architectures_implementing_power_gating__and__Trading_off_higher_execution_latency_for_increased_reliability_in_tile-based_massive_multi-core_architectures_

http://research.ac.upc.edu/HPCseminar/SEM0809/abs.html#Caches_In_the_Many-Core_Era


Task 3.9: Industrial workshops

This activity, which started during HiPEAC1, aims to increase relevance of the HiPEAC

research to industry, and to strengthen the relationships between industrial and academic

organisations.

The participating companies organise an Industrial Workshop twice a year, one in spring and

one in fall. The Industrial Workshop is organised in conjunction with the cluster meetings.

Spring Industrial Workshop

The Workshop

The spring industrial workshop was organised by Infineon in Munich, on June 2, 2009,

during the Computing Systems Week.

Workshop program

The program:

Session 1 Welcome Attila Bilgic (Infineon)

INFINEON wireless solutions

overview

Prof. Dr. J. Hausner (Infineon)

Session 2 HiPEAC vision 2012-2020 Marc Duranton (NXP)

"System Engineering" Dr. Matthias Sauer (Infineon)

Session 3 FP7 eMuCo Dr. E. Gonzalez (RUB)

FP7 MERASA: Towards a Predictable

Embedded Multi-core Processor

Theo Ungerer (Augsburg)

Automatic and portable optimizing

compilation using machine learning:

results from the EU MilePost project

Mike O’Boyle, Grigori Fursin

Session 4 HyperTransport: Extending

Technology Leadership

José Duato, Mario Cavalli

System Level Approaches for

Designing Embedded Computing

Systems

Christian Haubelt, University of

Erlangen-Nuremberg, Germany

Workshop Attendance

106 people attended the workshop.

The participants’s distribution was as follows:

Members: 44

Affiliated members: 20

Affiliated PhD students: 24

Staff: 2

Others: 15


The country distribution:

Austria: 2

Belgium: 7

Cyprus: 1

Finland: 1

France: 9

Germany: 27

Greece: 6

Ireland: 1

Israël: 3

Italy: 5

No country: 3

Norway: 2

Poland: 3

Portugal: 2

Spain: 16

Sweden: 1

Switzerland: 2

The Netherlands: 6

Turkey: 1

United Kingdom: 7

44

20

24

2

15

Members

Aff. Members

PhD Students

Staff

Other


Some engineers from Infineon attended the meetings (not listed above).

13 members from companies attended the workshop, representing:

Splitted Desktop

Thales

SAP

Nanochronous

Movidia

IBM

ST Microelectronics

Microtech

NXP

Participants’ Feedback

The participants of the workshop were asked for their feedback on the event.

27 attendants filled out the survey, about 1/4 of the participants.

Low Neutral High

Industrial Workshop 5 9 13

The average rating is 2.3 out of 3.

The comments indicated they appreciated the increased company input compared to previous

industrial workshops.

Autumn Industrial Workshop

The workshop

The autumn industrial workshop was organised by Zbigniew Chamski from Infrasoft and took

place in the Sofitel Hotel in Wroclaw, Poland on October 26th

.

Workshop program

The entire program of the workshop follows.

9:15-10:00 A. Galik: HiPEAC-related R&D in Poland

10:00-10:30 G. Gaydadjiev: HiPEAC addresses the long-term multicore research challenges: the SARC

project

11:00-12:00 Industrial R&D in Poland

Z. Chamski, M Borzęcki, K. Pawlak, Infrasoft IT Solutions/Proximetry Poland: "Domain-

driven optimisation of high-performance embedded communication devices"

Pawel Musial, " Tiny, robust security devices - low power vs. performance", Gdynia,

Poland: "Ultra-low power security systems"

G. Mrugalski, Mentor Graphics Poland: Testing of Digital Systems

13:30-15:00 European processor research


Nigel Topham, University of Edinburgh, UK, EnCore: A Low-power Extensible

Embedded Processor

Anirban Lahiri, ARM Ltd, Cambridge, UK: The Osprey A9 core

15:30-16:30 Academic research in Poland

A. Ziębiński, Silesian University of Technology, Gliwice, Poland: "Domain-specific

FPGA-based coprocessors for complex computational algorithms"

W. Mikanik, Silesian University of Technology, Gliwice, Poland: "Portability of

Performance in High-Level Parallel Programming"

16:30-17:30 Panel session HiPEAC-related R&D _with_ Poland: where, how, with whom? Participants:

HiPEAC Steering Committee, Poland-based HiPEAC members, representatives of Polish

R&D

Workshop Attendance

The industrial workshop was attended by 67 people.

Members: 34

Affiliated members: 10

Affiliated PhD students: 8

Staff: 2

Others: 12

Austria: 1

Belgium: 8

Cyprus: 1

Finland: 1

France: 6

Germany: 7

Greece: 5

Ireland: 1

Israël: 1

No country: 3

Poland: 5

Portugal: 1

Russia: 1

Spain: 6

34

10

8

2

12

Members

Aff. Members

PhD Students

Staff

Other


Sweden: 2

The Netherlands: 10

Turkey: 1

United Kingdom: 6

The industrial workshop received representatives from Ericsson, Thales, IBM, Infrasoft,

Ru.Chip and Nema Labs


Participant’s feedback

The appreciation on the industrial workshop was answered by 17 people, more than ¼ of the

attendants.

Their feedback:

Low Neutral High

Industrial Workshop 3 7 7

This averages to a rating of 1.65 out of 3. This was the lowest rating we had for an industrial

workshop.

The comments show that the quality of the presentations and the content did not match the

expectations of the attendants.


Workshop Date # participants

Infineon, Munich, Germany June 3-4, 2009 106

Wroclaw, Poland October 26-29,2009 67

Task 3.10 Promoting HiPEAC Start-Ups (Coordinator: ST Micro, Christian Bertin)

This task aims to stimulate members to create new start-ups by organising one yearly event.

Additionally, we embrace start-up companies by quasi-automatically inviting them as member

companies, so they get access to all the resources of the network. By promoting these

companies, we hope to contribute to their success.

This was the list of HiPEAC Start-Ups:

Acumem http://www.acumem.com/pub/ Erik Hagersten

Caps Enterprise http://www.caps-entreprise.com/ François Bodin

Nanochronous http://www.nanochronous.com/home/ Manolis Katevenis

Nema Labs http://www.nemalabs.com/ Per Stenström

QuviQ http://www.quviq.com/ John Hughes

Splitted desktop http://www.splitted-desktop.com/fr/ Olivier Temam

INOCS http://www.inocs.com Federico Angiolini

Kalray http://www.kalray.eu Benoît Dupont de Dinechin

In 2009, we welcomed the following start-ups in the network:

Ateji http://www.ateji.com Patrick Viry

Movidius http://www.movidius.com David Moloney

Ru.Chip http://www.ruchip.com Anton Gerasimov

Vector Fabrics http://www.vectorfabrics.com Andrei Terechko

http://www.acumem.com/pub/

http://www.caps-entreprise.com/

http://www.nanochronous.com/home/

http://www.nemalabs.com/

http://www.quviq.com/

http://www.splitted-desktop.com/fr/

http://www.inocs.com/

http://www.kalray.eu/

http://www.ateji.com/

http://www.movidius.com/

http://www.ruchip.com/

http://www.vectorfabrics.com/


Codeplay http://www.codeplay.com Paul Kelly

In order to promote the start-ups, Alasdair Rawsthorne, former CTO and founder of

Transitive, gave a keynote titled “How to Survive A Startup - from University Research to

Multinational - a Highly Personal View” at the summer school.

Since October, the coordinator of this task, Marco Cornero, left the consortium. The

coordination of this task has, since the second period of HiPEAC, been taken over by the new

partner, ST Grenoble, and its responsible scientist, Christian Bertin.

Future plans

To further increase the integration of start-ups in the future, we plan the following activities:

Course on entrepreneurship at the summer school organized by Chalmers University.

Focus on SME’s and start-ups in the spring 2010 industrial workshop

Invited talks by venture capitalists and business angels at the spring industrial workshop


# HiPEAC start-ups per HiPEAC activity

ACACES 2009 Summer School: 1

# new HiPEAC start-ups:5

Task 3.11 – Award Program

In computing systems, the best possible means for achieving international visibility is to

publish in, to be a program committee member of, or even to organise a major conference.

The HiPEAC award program aims to encourage the members to publish their work in one of

the selected conferences (based on the quality of the conference, and the relative low number

of European papers in these conferences).

Selected conferences

The SC agreed in 2008 to stimulate publishing in one of the following conferences:

Symposium on Principles of Programming Languages (POPL)

Conference on Programming Language Design and Implementation (PLDI)

Conference on Architectural Support for Programming Languages and Operating

Systems (ASPLOS)

International Symposium on Computer Architecture (ISCA)

International Symposium on High Performance Computer Architecture (HPCA)

Symposium on Field-Programmable Custom Computing Machines (FCCM)

Design Automation Conference (DAC)

Symposium on Microarchitecture (MICRO)

The award consists of a certificate and a financial award of € 1000 for the HiPEAC member

that authored the paper. A HiPEAC member can get the financial award only once.

2009 results

In 2008, 15 papers were eligible for the paper award:

Conference # Papers eligible

http://www.codeplay.com/


POPL 0

PLDI 1

ASPLOS 1

ISCA 2

HPCA 2

FCCM 2

DAC 5

MICRO 2

In 2009, 22 papers were eligible for the paper award:

Conference # Papers eligible

POPL 0

PLDI 1

ASPLOS 2

ISCA 3

HPCA 0

FCCM 6

DAC 4

MICRO 6

We see a significant increase in eligible papers.

List of eligible publications

These publications by HiPEAC members are published at the selected conferences:

Paper Title Authors Conference

Towards a Holistic Approach to Auto-

Parallelization: Integrating Profile-Driven

Parallelism Detection and Machine-

Learning Based Mapping

Georgios Tournavitis, Zheng Wang, Björn

Franke, Michael O'Boyle

Programming

Language Design and

Implementation 2009

Per-Thread Cycle Accounting in SMT

Processors

Stijn Eyerman, Lieven Eeckhout Architectural Support

for Programming

Languages and


Operating Systems

Producing Wrong Data Without Doing

Anything Obviously Wrong!

Todd Mytkowicz, Amer Diwan, Univ. of

Colorado, USA, Matthias Hauswirth,

Univ. of Lugano, Switzerland, Peter

Sweeney, IBM Research, USA

Architectural Support

for Programming

Languages and

Operating Systems

Hardware Support for WCET Analysis of

Hard Real-Time Multicore Systems

Marco Paolieri, Eduardo Quiñones,

Francisco J Cazorla, Guillem Bernat,

Mateo Valero

International

Symposium on

Computer

Architecture 2009

Stream Chaining: Exploiting Multiple

Levels of Correlation in Data Prefetching

Pedro Diaz, Marcelo Cintra International

Symposium on

Computer

Architecture 2009

Reconciling specialization and flexibility

through compound circuits

Sami Yehia, Sylvain Girbal, Hugues

Berry, Olivier Temam

International

Symposium on High-

Performance

Computer

Architecture 2009

Accelerating Quadrature Methods for

Option Valuation

Anson H.T. Tse, David B. Thomas, Wayne

Luk

Field-Programmable

Custom Computing

Machines

FPGA Accelerated Simulation of

Biologically Plausible Spiking Neural

Networks

David B. Thomas, Wayne Luk Field-Programmable

Custom Computing

Machines

Benchmarking Reconfigurable

Architectures in the Mobile Domain

Peter Jamieson, Tobias Becker, Wayne

Luk, Tero Rissa, Teemu Pitkanen, Peter

Y.K. Cheung

Field-Programmable

Custom Computing

Machines

Compact and Flexible Microcoded

Elliptic Curve Processor for

Reconfigurable Devices

Samuel Antao, Ricardo Chaves, Leonel

Sousa

Field-Programmable

Custom Computing

Machines

FPGA Implementation of a Single-

Precision Floating-Point Multiply-

Accumulator with Single-Cycle

Accumulation

Arun Paidimarri, Alessandro Cevrero,

Philip Brisk, Paolo Ienne

Field-Programmable

Custom Computing

Machines

IMORC: Application Mapping,

Monitoring and Optimization for High-

Performance Reconfigurable Computing

Tobias Schumacher, Christian Plessl,

Marco Platzner

Field-Programmable

Custom Computing

Machines

Way Stealing: Cache-Assisted Automatic

Instruction Set Extensions

Theo Kluter, Philip Brisk, Paolo Ienne,

Edoardo Charbon

Design and

Automation

Conference

Designing Heterogeneous ECU Networks

via Compact Architecture Encoding and

Michael Glaβ, Martin Lukasiewycz,

Jürgen Teich, Unmesh D. Bordoloi,

Design and

Automation


Hybrid Timing Analysis Samarjit Chakraborty Conference

NOC Topology Synthesis for Supporting

Shutdown of Voltage Islands in SOCs

Ciprian Seiculescu, Srinivasan Murali,

Luca Benini, Giovanni Di Micheli

Design and

Automation

Conference

Dynamic Thread and Data Mapping for

NOC Based CMPs

Mahmut Kandemir, Sai Prasanth

Muralidhara, Ozcan Ozturk

Design and

Automation

Conference

Portable Compiler Optimization Across

Embedded Programs and

Microarchitectures using Machine

Learning

Christophe Dubach, Timothy M. Jones,

Edwin V. Bonilla, Grigori Fursin, Michael

F.P. O'Boyle

42nd International

Conference on

Microarchitecture

EazyHTM: Eager-Lazy Hardware

Transactional Memory

Saša Tomic, Cristian Perfumo, Chinmay

Kulkarni, Adrià Armejach, Adrián Cristal,

Osman Unsal, Tim Harris, Mateo Valero

42nd International

Conference on

Microarchitecture

An Hybrid eDRAM/SRAM Macrocell to

Implement First-level Data Caches

Alejandro Valero, Julio Sahuquillo,

Salvador Petit, Vicente Lorente, Ramón

Canal, Pedro López, José Duato

42nd International

Conference on

Microarchitecture

Multiple Clock and Voltage Domains for

Chip Multi Processors

Efraim Rotem, Ran Ginosar, Avi

Mendelson, Uri Weiser

42nd International

Conference on

Microarchitecture

Characterizing the Resource-Sharing

Levels in the UltraSPARC T2 Processor

Vladimir Cakarevic, Petar Radojkovic,

Javier Verdú, Alex Pajuelo, Francisco J.

Cazorla, Mario Nemirovsky, Mateo Valero

42nd International

Conference on

Microarchitecture

Optimizing Shared Cache Behavior of

Chip Multiprocessors

Mahmut Kandemir, Sai Prasanth

Muralidhara, Sri Hari Krishna Narayanan,

Yuanrui Zhang, Ozcan Ozturk

42nd International

Conference on

Microarchitecture

Based on the rules set by the steering committee (a member can only receive a financial

award once), the following 14 members were given a HiPEAC Financial Award:

Michael O'Boyle

Matthias Hauswirth

Guillem Bernat

Sami Yehia

Peter Cheung

Leonel Sousa

Paolo Ienne

Marco Platzner

Jürgen Teich

Luca Benini

Ozcan Ozturk

Timothy Jones

Osman Unsal

Avi Mendelson


This means that now 24 members have received a financial award:

Francisco Cazorla Marco Platzner

Adrian Cristal Mateo Valero

Albert Cohen Matthias Hauswirth

Avi Mendelson Michael O'Boyle

Guillem Bernat Osman Unsal

Jörg Henkel Ozcan Ozturk

José Duato Paolo Ienne

Jürgen Teich Peter Cheung

Leonel Sousa Rainer Leupers

Lieven Eeckhout Sami Yehia

Luca Benini Timothy Jones

Marcelo Cintra Wayne Luk

Progress indicator:

# of publications awarded: 22

# financial awards: 14 Eligible

high performance and embedded architecture and … · d3.6 spreading excellence report march 31,...

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