Sadhana Vol. 41, No. 2, February 2016, pp. 147–159 c© Indian Academy of Sciences

High performance AC–DC control power supply for low voltage ridethrough inverters

K SAICHAND∗, AKSHAY KUMRAWAT and VINOD JOHN

Department of Electrical Engineering, Indian Institute of Science,Bengaluru 560012, Indiae-mail: kasicheyanula@ee.iisc.ernet.in; akshayclk@gmail.com; vjohn@ee.iisc.ernet.in

MS received 11 February 2015; accepted 2 August 2015

Abstract. This paper presents a control power supply (CPS) design which is used to feed power to the subsys-tems of a power converter. The CPS design presented here maintains a constant 24Vdc output even over a wide(90Vrms to 270Vrms) ac voltage variation at its input for a High Power Converter (HPC). The circuit design andclosed loop control design of such a CPS are presented. During starting, the power supply to the control circuitryof the CPS in turn is obtained using a separate start-up power supply. The various design issues and details ofthe on-board power supply and start-up power circuit to ensure the reliable start-up and shut down of the CPSare analyzed. The CPS was tested for wide input voltage range (vin) and the performance validates the design.The CPS has also been tested for an input side voltage sag and its performance allows the HPC to meet the lowvoltage ride-through requirements.

Keywords. Control power supply; double switch forward converter; start-up power supply; pre-regulator; aver-age current control; peak current control.

1. Introduction

High Power Converters (HPCs) play a key role in micro-grids and smart grid technologies, as they are used in powerquality, drive applications and grid connected converters.For reliable operation, HPC requires robust sub-systems likegate drive card, protection and delay unit of the converter,annunciation card and sensing cards. A typical converterapplication block diagram is shown in figure 1, in whichhigh power converter processes the input ac power withthe help of various sub-systems. These sub-systems needpower at specified voltage to perform their task. The powerrequired for these sub-systems is drawn from the CPS, whichin turn is powered by the input ac voltage. The operationof the sub-systems of a HPC should not be affected by thevariation in the input ac voltage (Vin) and under transientvoltage sags and swells.

The inability to meet the voltage specifications of thesub-systems can result in malfunctioning of the CPS, whichin turn can cause undesirable operation in the HPC [1].Thus, power to the sub-systems of a HPC, using CPSplays a critical role in the overall operation of a HPC.References such as Ravi & John [2] reports work on ridethrough during momentary blackouts for various sub-sytemsof HPC. Although references such as Kelley et al [3]and Sarmiento & Estrada [1] report work on Low Voltage

∗For correspondence

Ride-Through (LVRT) in solar and wind applications, nowork has been reported on LVRT of various sub-systems ofa HPC. In this paper, a CPS with wide input voltage varia-tion (90Vrms to 270Vrms) is designed which provides LVRTfor various sub-systems of a HPC.

The performance of these HPC sub-systems also dependson the reliable start-up and shut down of the CPS. The oper-ational relation of HPC, CPS and start-up circuit of the CPSis as shown in figure 1. Xu & Yifan [4] compares variousstart-up power circuit topologies for different voltage lev-els. In this paper, a simple, modified version of the start-upcircuit proposed in Xu & Yifan [4] is considered. The num-ber of circuit components of the start-up circuit proposed inthis paper is comparatively low because features such as theauto-restart are not necessary in the CPS of a HPC [4]. Thepaper also analyzes the working of the start-up power circuitduring shut-down period. The various design issues of thegate drive circuits and on-board power supply which powersthe control circuit of the CPS during steady operating stateare also discussed in this paper.

The organization of the paper is as follows: The voltageand power specifications of the CPS designed are providedin section 2. The topology and design of pre-regulator, iso-lated dc–dc converter, start-up power circuit and on-boardpower supply are discussed in section 3. The control sys-tem design for pre-regulator and isolated dc–dc converter isdiscussed in section 4. The experimental results on the CPSunder various loading and line voltage conditions as well as

147

148 K Saichand et al

Figure 1. Typical block diagram of CPS feeding the high powerconverter (HPC) subsystems.

under transient conditions such as input voltage sag as perdesign are discussed in section 5. Section 5 also discussesthe evaluation of start-up and shut down operations of theCPS. The experimental results in section 5 show that mea-sured performance matches the requirements used for theCPS design.

2. Specifications of the CPS

The required characteristics of a CPS are that it should:(1) be reliable and inexpensive, (2) have tight line and loadregulation, (3) have good dynamic performance, (4) haveisolation with capability of rejection of input disturbance

in the output, and (5) have high efficiency [5]. The CPSconsidered in this paper consists of two stages – the pre-regulator stage and an isolated dc–dc converter stage. Theregion inside dashed line in figure 2 shows the configurationof the CPS considered for a 3φ-HPC rated at 250kVA, 415V,50Hz, switching at fsw =10kHz [6].

Table 1 shows the power consumed by various invertercontrol cards based on measurements made in the labora-tory. The CPS designed for this HPC supplies 200W powerat 24Vdc to not only cater to control sub-systems’ powerrequirements for two parallelly operating HPCs, but alsoto provide power to charge an ultracapacitor based energystorage system [2, 7]. The pre-regulator stage is designedfor 300W input power so as to allocate 250W at Vdc =400V for output stage and 50W for losses of system assum-ing ηpre = 83.33%. The isolated dc–dc converter stageis designed for 250W input power so as to allocate 200Wat 24Vdc for output power and 50W for losses of systemassuming ηdsf c = 80%.

It is preferred that the input to the CPS be ac ratherthan from a source such as the dc bus of a HPC. This isbecause the working of the afore-mentioned subsystems ofa HPC (such as protection and dead time generation cir-cuit) is essential during the process of energizing the dcbus of HPC. This would not be possible if the input to theCPS is obtained from the dc bus of the HPC. The CPScircuit design and closed loop control design discussed insections 3 and 4 achieve the above-mentioned desired char-acteristics which is verified using the experimental results insection 5.

Figure 2. Schematic structure of a control power supply used in a HPC.

Table 1. Power consumed by the 250 kVA high power converter control cards.

Inverter cardCurrents drawn (A)

Power (W)+15V −15V 5V

Annunciation card 0.052 0.005 1.71Voltage sensing cards (ac + dc) 0.238 0.033 8.13Current sensing cards (4 channels) 0.736 11.04Protection, delay and timing card 0.122 0.066 0.504 10.64DSP card 0.1 0.1 1.5 10Gate drive cards (6 channels) 3 45Total power 78

High performance LVRT power supply 149

Figure 3. Circuit diagram of pre-regulator stage used.

3. CPS power circuit design

This section presents the topology and hardware design forpre-regulator and isolated dc–dc converter which includescomponent selection, loss calculations which is required forCPS power circuit board design.

3.1 Design of pre-regulator power circuit

The pre-regulator stage circuit considered in CPS is asshown in figure 3. This stage provides rectification, as dcrequired to use in next power stage of CPS from availableac. A boost converter is used in pre-regulator stage to pro-vide a regulated Vint of 400Vdc for wide range of inputvoltage vin (90Vrms to 270Vrms). The output voltage of thepre-regulator stage is chosen to be 400Vdc, so as to keepVint > |vin_max(peak)|. Also, a boost converter ensurescontinuous input current which requires less filtering [8]. Bycontrolling the duty cycle of switch, Sb, inductor currentcan be shaped as rectified sine wave and output capaci-tor voltage can be regulated. The switching frequency ofswitch, Sb is chosen to be 100kHz. The other design detailsof the pre-regulator circuit are provided in the reference [9].The gate-drive circuit for boost converter switch, Sb of pre-regulator circuit is as shown in figure 4. A gate resistancebased drive of 15� during turn on and 10� during turn offis chosen, which gets PWM from control IC UC3854 of thepre-regulator. A RCD turn off snubber circuit as shown infigure 4 is used to limit dV

dtacross switch during turn off

period. The part numbers of various components used inboost gate drive circuit are tabulated in Appendix I(a).

Figure 4. Gate drive circuit and snubber circuit of the boost pre-regulator stage.

3.1a Loss calculation of pre-regulator: The designvalues and part numbers of the various components ofthe pre-regulator and their corresponding losses are calcu-lated for worst case operating conditions which is shown intable 2. The total losses in pre-regulator is around 30W forPin = 300W at low input voltage of vin = 90Vac makingthe worst case efficiency of pre-regulator, ηpre = 90%.

3.2 Isolated DC–DC converter circuit design

For isolated dc–dc converter, a Double Switch Forward Con-verter (DSFC) is chosen which is shown in figure 5. Bothswitches, S1 and S2 get the same PWM signals switching at afsw of 120kHz. DSFC is chosen for isolated dc–dc converterstage because it exhibits the following advantages: (1) sim-ple transformer design, (2) device voltage rating is the sameas the dc bus voltage, (3) simple dynamic model and closedloop control, (4) clamp diodes recovers magnetizing energyin the core avoiding a separate demagnetizing winding, (5)output filter requirement is low, and (6) better utilization ofwinding copper. In contrast to the pre-regulator’s simple gatedrive circuit, a transformer based gate drive circuit is used inthe DSFC as a high side drive to drive switch S1 is requiredis as shown in figure 6. Due to the DSFC operation at highswitching frequency and duty ratio being limited to 50%,the gate drive circuit’s transformer Xt1’s design is simple.It consists of a forward converter utilizing a HF transformerXt1 with reset winding and two secondary windings. Thetransformer’s primary is driven by transistor Q1, as shown infigure 6. Rb_q1 provides steady state base current, while C1and R1 are used to provide signal conditioning during turnon and off of Q1. A gate resistance of 12� is used duringturn on, while PNP based turn off circuit is used. The partnumbers of various components used in DSFC gate drivecircuit are tabulated in Appendix I(c).

3.2a Loss calculation of DSFC: Table 3 tabulates thecomponent values/part-numbers of the various componentsand their corresponding losses at rated input power of DSFCat 250W and input voltage of 400Vdc. The total loss inDSFC under these conditions is found to be around 15Wwith efficiency, ηdsf c = 94.3%. The loss calculation detailsof the pre-regulator and the DSFC provided in the table 2and table 3 play a crucial role in the electrical layout andthermal design of the power circuit board consisting of thepre-regulator and the DSFC, which is shown in figure 19(b).

3.3 On board power supply and start-up circuit

For the closed loop operation of the pre-regulator and iso-lated dc–dc converter during normal operating conditions,on board power supply (OBPS) is essential. Also during thestarting conditions, when OBPS is inactive, a start-up circuitis necessary. In this subsection, the role of start-up power cir-cuit as well as on-board power supply (OBPS) is discussed.

150 K Saichand et al

Table 2. Loss tabulation of the pre-regulator.

Device Loss type Parameters Loss calculation Loss

Rectifier diode- Conduction Vf 1 = 0.85V, rd =30m�, 4 ∗ (Vf 1 ∗ iav1 5.8WSK3GL10 iav1 =1.5A, irms1 = 2.4A +rd ∗ i2

rms1)

Inductor, Lb-1mH Conduction RLb= 0.22�, irms2=3.3A RLb

∗ i2rms2 2.4W

Boost diode, Conduction Vf 3=1.5V, iav3=0.75A Vf 3 ∗ iav3 1.125WDb-MUR860 Reverse Qrr=195nC, Vr=400V, (Qrr ∗ Vr/2) ∗ fsw 3.9W

recovery fsw =100kHz

Boost switch, Switching tr=35ns, tf =30ns, Ts = 10μs, (2/π) ∗ [(tr + tf ) 7.8WSb-IRF840 Vb=400V, ipeak = 4.7A ∗Vb ∗ ipeak]/Ts

Conduction Rd_on = 0.85�, irms4=2.44A Rd_on ∗ i2rms4 5.06W

Capacitor, Conduction ESR120Hz = 0.84�, (ESR120Hz ∗ i2rms_100Hz)

Cint -235μF ESR<50kHz = 0.37�, +(ESR<50kHz ∗ i2rms_100kHz) 1.0W

irms_100Hz=0.53A,irms_100kHz=1.46A

Sensing resistor, Conduction Rsens = 0.2� 3.32 ∗ 0.2 2.2WRsens

Figure 5. Circuit diagram of double switch forward converterwith fly-back winding for onboard power supply used in the CPS.

The start-up power supply presented here is simple with lin-ear elements. The on-board power supply is more efficientsince it utilizes switched mode circuits. The start-up powersupply designed provides appropriate Vcon for entire 90Vac

to 270Vac input.

3.3a Circuit operation during start-up: In figure 7,start-up power circuit implemented for CPS is shown. Itshould be noted that the control ICs in figure 7 refers toUC3854, UC3844 and UC3901 and UC3844 datasheets [10].During startup, the output voltage of pre-regulator circuit(Vint ) would be charged to Vin

√2. This is because, neither

the pre-regulator nor the isolated dc–dc converter works dur-ing the start-up, since there is no power to the control circuitof the CPS. It should also be noted that, the power to the con-trol circuit of the entire CPS is generated from Vobps whichis obtained from a tertiary winding of the high frequencytransformer of DSFC Xt2 as shown in figure 6. Hence asurge diode (D5) as shown in figure 3 is used, which chargesthe Cint during start-up period to Vin

√2, without Lb-Cint

resonant overshoot. Once both the ICs (UC3844 and UC3854)start working based on Vint due to start-up circuit operation,the closed loop control of Vint begins and Cint is chargedfrom Vin

√2 to 400V (Vref ) and is regulated at that voltage.

Figure 6. Gate drive circuit, snubber and on-board power supply in DSFC.

High performance LVRT power supply 151

Table 3. Loss tabulation of power devices in DSFC.

Device Loss type Parameters Loss calculation Loss

MOSFETs, Switching tr5=35ns, tf 5=30ns Ts5 = 8.3μs, [(1/2){(tr5 + tf 5) 5.44WIRF840 Vb=400V, imax=1.8A ∗Vb ∗ imax}/Ts5] ∗ 2

Conduction Rd_on6 = 0.85�, irms6=1.1A (Rd_on6 ∗ i2rms6) ∗ 2 2.19W

Diode D1, Conduction Vd7=0.7V, iav7=3.75A Vd7 ∗ iav7 2.63WMBR202 − 00CT

(Secondary)Diode D2, Conduction Vd8=0.7V, iav8=6.67A Vd8 ∗ iav8 3.27WMBR202 − 00CT

(Secondary)Inductor,Lo-80μH Conduction RL0 = 0.01�, irms9=10.4277A i2

rms9*RL0, where 1.09W

irms9 =√

P 2o

V 2o

+ a2

3 , and

a = (Vg [ N2

N1]−Vo

2Lo) ∗ dTs

Capacitor,Co-1320μF Conduction Rc0=77m�, irms10=0.46A i2rms10*Rc0, where 0.016Wirms10 = a

3H-F transformer Primary Rp = 0.12�, irms11=1.04A i2

rms11*Rp , where 0.130Wirms11 = PoN2

VoN1

√d

Secondary Rs=5.2m�, irms12=6.25A i2rms12*Rs , where 0.201Wirms12 = Po

Vo

√d

In the absence of power from the on-board power supplyduring starting, voltage at Cap is built by charging of Cap

through high voltage, Vint with resistance, Rst_lmt to limitthe current as seen from figure 7. MOSFET, Sst is turned oninitially by providing biasing voltage through Rsb1 and Rsb2.A zener diode, Z1 across Cap is used to clip the voltage,Vcon. After on-board power supply is available, MOSFET,Sst is turned off by turning on switch, Qsoff , which willmake gate-source voltage across Sst negative. The turning-off of Sst is necessary because, it would otherwise result inincreased loss in resistance Rst_lmt . Qsoff is turned on byusing on-board power supply as biasing voltage. Resistance,Rr is used to reduce voltage Vrelay to 12V from partiallyregulated voltage, Vobps .

3.3b Design of start-up power circuit: The power tocontrol ICs of pre-regulator, isolated dc–dc converter andrelay (UC3854 and UC3844) during starting period is taken

care by start-up power circuit which is as shown in figure 7.For supplying power to control ICs under steady operatingconditions, an on-board power supply is built, which uses atertiary winding to the HF transformer of isolated dc–dc con-verter connected in fly-back mode as shown in figure 6. Theoutput voltage of an on-board power supply under normalrated operating conditions is given as

Vobps = N3

N1

d

1 − dVint . (1)

It should also be noted that the closed loop control has beendone for forward converter operation such that Vo is 24V forVint of 400Vdc at d=0.36. The transformer design for such amixed fly-back, forward mode operations is done such that,during the on period of switches (S1 and S2) the HF trans-former Xt2 works for forward converter whereas during theswitches’ turn off period, fly-back operation is performedbetween primary and tertiary windings (refer figure 5). The

Figure 7. Schematic diagram of start-up power circuit of the CPS.

152 K Saichand et al

design of the tertiary winding of the HF transformer is donesuch that under no-load conditions, when Vint is 400Vdc,the OBPS voltage Vobps is 30V . Under these conditions,when primary winding turns N1 are 54, the tertiary windingturns N3 are 4. Based on these design criteria, diode Dobps

is selected as MUR110 with voltage rating of 100V andcurrent rating of 1A and Cobps is selected as 22μF. ControlICs (UC3854 and UC3844) and gate drive circuit requiresaround 70mA. While isolated dc–dc converter control ICUC3844’s turn on voltage is 16V from off condition, the turnoff voltage from on condition is 10V . Hence, the capacitorCap is chosen based on (2).

Cap = 2Pcontstarting

(V 2i − V 2

f ), (2)

where Pcon is the control IC power, tstarting is the timefrom system starting up to on-board power supply becom-ing active which is around 20ms, Vi is turn on voltage ofIC from off condition (16.8V ) and Vf is IC turn off volt-age (10.5V ) (UC3844 datasheet). Using (2), Cap is chosenas 420μF . Rst_lmt is selected as 4.7k�, which will requirearound 0.35s for Vcon to rise from 0V to 16V during startingat low line voltage of Vin = 90Vrms . Also, Rsb1 is selectedas 1.5M�. For VRsb2 to be 3.5V at Vint = 120V (low line),it is required for Rsb2 to be around 42k�. At input highline voltage Vin = 265Vrms , VRsb2 is found to be around14V . Also, Rbe_off is chosen to be 10k�. For VRbe_off

to bearound 0.6V at Vobps of 10V , it is required for Rb_off tobe 180k�. While, MOSFET IRF820 is selected as switchSst having a voltage rating of 500V and continuous currentrating of 2.5A, BJT 2n2222 is selected as switch Qsoff hav-ing a voltage rating of 40V and maximum current rating of800mA.

During start up conditions, the circuit is prone to highinrush currents. In order to limit these high in-rush currents,resistance, Rcurr_lmt is employed. But once the circuit tran-sits into normal operating state, this resistance has to bebypassed in order to prevent the losses. Hence, a relay isused in parallel to the resistance Rcurr_lmt such that basedon Vrelay shown in figure 7, Rcurr_lmt is bypassed. Dur-ing normal operating conditions, control voltage Vcon is alsomaintained by on-board power supply (Vobps) using zenerbased regulated supply. Appendix I(b) summarizes values ofvarious components used in start-up power circuit of CPS.

Overall, the entire starting procedure can be summarizedbased on the following sequence:

• After energizing the circuit, the Vint is initially chargedto Vin

√2 through diode, D5.

• The start-up power circuit based on Vint charges Cap

through Rst_lmt . When Vcon charges beyond ICs’ turnon threshold voltage (16V for UC3854 and 16.5V forUC3844), DSFC starts working.

• With DSFC working, Vobps turns off the start-up circuitusing BJT, Qsoff .

• The presence of Vobps results in relay closure, sinceVrelay is dependent on Vobps . Also Vobps starts supply-ing required power to all control ICs.

• Once both the ICs start functioning, the Vint also startscharging from Vint

√2 to Vref = 400V . Hence, the

circuit transits into normal operating state.

The role of startup circuit and OBPS discussed in subsec-tions 3.3a and 3.3b is verified using experimental results insection 5.

4. Control system design for the CPS

This section discusses the various design issues encounteredin the corresponding closed loop controls of pre-regulatorand isolated dc–dc converters. While the pre-regulator’sclosed loop control maintains UPF operation and regulatesvoltage Vint at 400Vdc, the isolated dc–dc converter’s closedloop control regulates output voltage Vo at 24V .

4.1 Control design for pre-regulator circuit

A dedicated IC UC3854AN and UC3844 datasheets [10]from Texas Instruments has been chosen for UPF recti-fier control. It uses average current mode control (UC3844datasheet) in the inner current control loop and an outeroutput voltage control loop as shown in figure 8 [11]. Therectified sinusoidal current reference is generated using amultiplier which has three inputs. They are: (1) the bridgerectifier’s output voltage, (2) the output voltage error, and(3) a feed forward term, which are shown as x, y and zin figure 8, respectively. The input z is proportional to theRMS value of input voltage, and is obtained by passing therectified input voltage through a low pass filter.

In the absence of the feed forward term, any change ininput voltage gets reflected in the current reference, mak-ing input current to change by the same ratio as to the

Figure 8. Control structure of the UPF rectifier.

High performance LVRT power supply 153

(a) (b)

Figure 9. Control loop models of average current controlled UPF rectifier: (a) Current loop model (b) Voltage loop model.

input voltage, which makes input power change by squareto the change of input voltage. This generates power imbal-ance between input and output, resulting in output voltagetransients. This issue is resolved by dividing the current ref-erence by square of the RMS value of input voltage reducingthe input current by same ratio. This results in unchangedinput power, which generates no output voltage transientbecause of the input voltage change. The corresponding cur-rent and voltage control loop is represented in figure 9,where Vosc is peak-peak value of PWM carrier and equalto 5.5V in selected PWM IC UC3854. The control transferfunction of inductor current to duty cycle for average modecontrol is given as [11]:

iL(s)

ds(s)= Vint

R(1 − Ds)2

[2 + sCR

1 + sLe

R+ s2LeCo

], (3)

where Le = Lb

(1−Ds)2 . On substituting the circuit parametersprovided in table 2 in (3), we have

iL(s)

ds(s)= 0.75

[2 + 0.125s

1 + 1.876 ∗ 10−6s + 0.235 ∗ 10−6s2

].(4)

In figure 9(a), Hi(s) which is a current controller is cho-sen as Proportional Integral (PI) controller. The zero of thenumerator polynomial is kept at 1√

LeCorad/s. The corre-

sponding current controller bandwidth is tuned for 15kHz.A high frequency pole is added in Hi(s) so as to attenuatethe noise. Hence, Hi(s) is selected as

Hi(s) = 1.4(1 + s

2π340

)s

2π340

1(1 + s

2π100e3

) . (5)

Bode plots of G1(s) and G1(s)Hi(s) are shown in figure 10.The pre-regulator voltage transfer function is given as [5]:

vint (s)

vvea(s)= KacRmo

2VintRsK2ff

R(1 − Ds)

1 + s RCo

2

. (6)

On substituting design values in (6), we have

vint (s)

vvea(s)= 51

1 + 0.0625s. (7)

In figure 9(b), the voltage controller Hv(s) is chosen as PIcontroller. Zero of the PI controller is kept at RCo

2 rad/s. Apole is added near the bandwidth of voltage controller. Band-width of voltage controller is kept near at 25Hz so as toattenuate 100Hz ripple content in Vint . This ensures that theTHD in input current is minimized to 1% of 100Hz com-ponent to dc value in output of voltage error amplifier andthis produces 0.5% of 3rd harmonic to fundamental in inputcurrent iin. Hence, Hv(s) is selected as

Hv(s) = 0.282

1 + s2π27.2

1 + s2π2.72s

2π2.72

. (8)

The bode plots of G2(s) and G2(s)Hv(s) are shown infigure 11.

4.2 Control design for isolated dc–dc converter

For the closed loop operation, IC UC3844 which uses peakcurrent control in inner current loop and output voltage inouter voltage loop is utilized (UC3844 datasheet). The peakcurrent control exhibits faster dynamic response and simplecontrol implementation due to absence of inductor current as

−100

−50

0

50

100

Mag

nitude

(dB)

Frequency (Hz)10

−110

010

110

210

310

410

510

610

7−180

−90

0

90

Pha

se(deg

)

mm

Figure 10. Bode plot of G1(s) and G1(s)Hi(s) corresponding to current loop of pre-regulator.

154 K Saichand et al

−60

−40

−20

0

20

40

60

Mag

nitude

(dB)

Frequency (Hz)10

−110

010

110

210

3−180

−135

−90

−45

0

Pha

se(deg

)

Figure 11. Bode plot of G2(s) and G2(s)Hv(s) corresponding to voltage loop of pre-regulator.

a state variable in the control loop. This reduces the secondorder plant transfer function to first order transfer function.Also, peak current control inherits current limit in its controlstructure and when used in buck based converters makes theoutput voltage independent of the input voltage variation.

Input voltage variation has small impact on the outputvoltage in peak current control, which can be avoided byproper choice of compensating ramp [12]. Since, the peakcurrent control is sensitive to noise, current blanking circuitis used to remove leading edge noise present in system dur-ing switching operation. Also slope compensation is added,which improves noise immunity. IC UC3901 along with asmall toroidal transformer for electrical isolation is used toprovide output voltage to the secondary (UC3844 datasheet).The IC works on the principle of amplitude modulationand the information on the secondary of the toroidal trans-former is extracted using a peak detector circuit, as shown infigure 12(a). The DSFC outer voltage loop is as shown infigure 12(b), where Co = 1320μF , Rs = 0.45�, Lo =80μH, n =6, RESR = 0.06425�, RLCo = 1

2π52 ,

(a)

(b)

Figure 12. Closed loop control structure of DSFC: (a) Schematicfor closed loop control in DSFC; (b) Outer voltage control loopmodel of DSFC.

RESRCo = 12π1.9k

and Rd

Lo= 1

2π17k. The voltage controller

transfer function Gv(s) is selected as

Gv(s) = 700

s

s2π50 + 1(

s2π1.9k

+ 1) (

s2π40k

+ 1) . (9)

This gives bandwidth of voltage loop 3.5kHz and phase mar-gin of 68o. Bode plots of G3(s) and G3(s)Gv(s) are shownin figure 13. The voltage controller Gv(s) is split into Gv1(s)

in IC UC3901 and Gv2(s) in IC UC3844 as given in (10)and (11).

Gv1(s) = 300

s

s2π50 + 1(

s2π1.9k

+ 1) (10)

Gv2(s) = 2.3(s

2π40k+ 1

) . (11)

The control system design for the closed loop operation ofthe CPS provided here is done in such a way that opti-mised stability and performance is achieved. The dynamicperformance of the CPS so designed is verified using theexperimental results in section 5.

5. Experimental results

The pre-regulator and DSFC hardware was experimen-tally tested for various load and line conditions. At ratedload power (RL) at DSFC with low line input conditionsof 90Vrms , the combined system performance is given infigure 14. Under these conditions, the THD is 12% withunity power factor and ηe = 84%. The THD in current ismeasured using FLUKE Power Analyser.

5.1 Performance of pre-regulator

Figure 14 shows the pre-regulator waveforms at Vin =95Vrms for high and low loads of RL = 2.3� and

High performance LVRT power supply 155

Frequency (Hz)

100

101

102

103

104

105

106

−270

−180

−90

0

Pha

se(deg

)

−150

−100

−50

0

50

100

Mag

nitude

(dB)

Figure 13. Bode plot of G3(s) and G3(s)Gv(s).

(a) (b)

Figure 14. Complete system performance at low line input voltage condition for (a) Low load condition: [Ch.1: Vo 20V/div., Ch.2: iin2A/div., Ch.3: Vcon 5V/div., Ch.4: Vint 100V/div., time scale: 10ms/div.] (b) High load condition: [Ch.1: vin 80V/div., Ch.2: iin 5A/div.,Ch.3: V0 3.80V/div., Ch.4: Vint 56V/div., MATH: Pin 500VA/div., time scale: 10ms/div.].

Table 4. Analytical and measured efficiencies, current THD inpre-regulator.

EfficiencyParametres Analytical Measured T HDi

RL = 550�, vin = 95Vrms 92.86% 90% 12%RL = 1500�, vin = 260Vrms 94.55% 93% 7.5%

RL = 11.5� at the DSFC respectively. The efficiency andTHD of input current in pre-regulator for various load andline voltage conditions are tabulated in table 4 and are foundto match the design values.

Also, at low grid voltage, cusp distortion increases theTHD in the current. At higher input voltages, efficiencyof system improves due to decrease in conduction andswitching losses in the components. Figure 15, shows theunloading of pre-regulator from 250W to 100W with vin =230Vrms . The control loop gets Vint back to the steady statein 28ms, which is close to the designed settling time of23.5ms. Transient loading or unloading of pre-regulator isdone by increasing or reducing the load at the DSFC.

5.2 Performance of isolated dc–dc converter

Figure 14 also shows the DSFC waveforms at vin = 90Vac

and Vint = 390V for Po = 50W, Po =220W respectively.Figure 14 also shows that output voltage Vo is regulated at24Vdc for various load and line conditions. The measuredefficiencies of DSFC at different operating conditions aretabulated in table 5. The measured efficiencies are found tobe close to the design based calculations.

Figure 16(a) shows the loading of DSFC from 125W to250W. It can be observed that the high bandwidth effect ofvoltage loop can be seen in the output inductor current ascurrent reference is generated through voltage loop and iLo

responded to load change within 40μs. Thus, output voltagehas very small transients. Due to the inductance associatedwith incoming resistor load, output current rises smoothly.Figure 16(b) shows the current limiting capability in its con-trol structure of DSFC during overload. It can be observedthat in the case of an overload, DSFC has maximum cur-rent limit of 12.5A which causes the output voltage to drop.Hence any load fault will not cause damage to the CPS.

156 K Saichand et al

Figure 15. Waveform for performance of pre-regulator: Step loadchange from 250W to 100W [Ch.1: Vo 10V/div., Ch.2: I2 5A/div.,Ch.4: Vint 200mV/div., time scale: 10ms/div].

Table 5. Analytical and measured efficiency of the DSFC.

Efficiency ηe

Parametres Analytical Measured

Po =250W, Vint = 350V 90.12% 88%Po =55W, Vint = 400V 94.64% 92%

5.3 Experimental result of the CPS start-uppower circuit

The performance of the start-up power circuit is presentedin figure 17 during the starting period for various load andline conditions. Figure 17(a) and figure 18(a) readings aretaken during starting period and shut down period for Vin =90Vac with 50W output load respectively. Figure 17(b) andfigure 18(b) readings are taken during starting and shut downperiods for Vin = 265Vac with 220W output load. Tests

were also carried out at 90Vac with higher loads and 265Vac

for lighter loads and results for start-up performance arefound to be satisfactory.

5.3a Performance during starting period: In figure17(a) and figure 17(b), at instant a, when input voltage isapplied, inrush current flows in the circuit to charge theVint up to peak value of Vin. These inrush currents are lim-ited by resistance Rcurr_lmt . Vcon starts building by chargingthrough Rst_lmt from Vint , which at starting is at Vin

√2. At

instant b, when Vcon reaches to around 16V , pre-regulatorcontrol IC starts and time taken to charge from 0V to 16V

is 350ms, which is as same as the calculated value. It can beobserved that for figure 17(b), the time taken to charge from0V to 16V is much lesser, which is generally around 150ms.Hence this delay will be maximum at low line input condi-tion. At instant c, Vcon reaches to ∼16.5V , at which isolateddc–dc converter control starts. After instant c, Vcon startsdecreasing due to supplying power to control IC’s. It can benoted that output voltage charges upto 20V after starting ofDSFC control.

The reason behind that the soft start feature involves inpre regulator control IC and Vint reaches upto 300V andsoft start nature of Vint can be seen in the output volt-age between instant c and instant d. In figure 17(a), afterinstant d under normal operating condition, Vcon is beingsupplied through on board power supply. Hence, the exper-imental results correspond to the design criteria in section3.3b according to which the design of on board power sup-ply, gate drive circuits and start up circuit of the CPS hasbeen performed.

5.3b Performance during shut-down period: Figure18 gives the dynamics of CPS and start-up power circuit dur-ing shut-down period for various line and load conditions. Atthe instant a, when the shut-down is initiated, the DSFC dutyratio varies accordingly to maintain the V0 at 24V . During

(a) (b)

Figure 16. Waveforms for performance of DSFC: (a) Step load change from ∼ 125W to ∼ 250W in DSFC [Ch.1: Vo 10V/div.,Ch.2: Io

2A/div., Ch.3: IL0 2A/div., Ch.4: Vint 200V/div., time scale: 2.5ms/div.] (b) During overload [Ch.2: ILo 2A/div., Ch.3: Vo 10V/div., timescale: 25μs/div.].

High performance LVRT power supply 157

(a) (b)

Figure 17. Waveforms during starting of pre-regulator and DSFC: (a) Waveforms for 90Vac and 50W load (b) Waveforms for 265Vac

and 220W load. Ch.1: V0 20V/div., Ch.2: iin 5A/div., Ch.3: Vcon 5V/div., Ch.4: Vint 100V/div., time scale 100ms/div.

(a) (b)

Figure 18. Waveforms during shut down of pre Regulator and DSFC: (a) Waveforms for 90Vac and 50W load. Ch.1: V0 20V/div.,Ch.2: Iin 2A/div., Ch.3: Vcon 10V/div., Ch.4: Vint 100V/div., time scale 250ms/div. (b) Waveforms for 265Vac and 220W load. Ch.1: V0

20V/div., Ch.2: Iin 2A/div., Ch.3: Vcon 10V/div., Ch.4: Vint 100V/div., time scale 250ms/div.

this period, the Vobps as shown in figure 6 reduces becauseof Vint reduction, resulting in Vcon reduction. Once the Vcon

is below 10V at b, the pre-regulator IC (UC3854) and DSFCcontrol IC (UC3844) turn off. It should be noted that theVint is still a large value (250V ). This results in activationof start-up power circuit again and charging of Vcon to 16V .When Vcon charges to 16V , Vobps comes into play, whichresults in discharge of Vcon once again. This process contin-ues in cycle until Vint discharges below a point (here instante) where start-up power circuit does not re-initiate.

5.4 System performance during input voltage sag

To further verify the CPS’s dynamic performance, the CPSis tested during the voltage sag period. A five cycle sag of50% depth is created in the laboratory. The voltage sag isemulated by a setup as shown in figure 19(a). An inductordivider consisting of L1 and L2 is provided to apply reducedvoltage of Vin = 115Vrms across the CPS for a time dura-tion of 0.1s. For this an inductor of 8.8mH with continuouscurrent rating of 30A and surge current rating of 300A

is chosen. The duration of voltage sag is dependent onMiniature Circuit Breaker (MCB)’s tripping characteristics.A INDIKOPP made C-type MCB with the nominal cur-rent rating of 10A is chosen. Based on the MCB magnetictripping characteristics, it would trip in 0.1s when the currentthrough the MCB is 100A.

The procedure for emulating the voltage-sag is asfollows:

• When the knife-switch is in off state, only inductanceL1 is included in the circuit and hence voltage acrossthe CPS is 230V.

• When the knife switch is closed, inductance L2 isincluded in the circuit. This results in high current of125A through the L2 branch.

• Since the current is nearly 10 times the Inominal of theMCB, it results in MCB trip in 0.1s.

• The instant from closing of knife switch to the instantof opening of MCB is characterized as the period ofvoltage sag. Once the MCB trips, the 230V is appliedagain.

158 K Saichand et al

(a) (b)

Figure 19. (a) Schematic for emulation of input voltage (Vin) sag, (b) Control Power Supply (CPS) under test.

(a) (b)

Figure 20. Waveforms for performance of CPS during voltage sag at (a) 70W load at DSFC: [Ch.1: IL2 50A/div., Ch.2: vin 200V/div.,Ch.3: Vo 5V/div., Ch.4: iin 5A/div., time scale: 25ms/div.], (b) 200W load at DSFC: [Ch.1: IL2 100A/div., Ch.2: Vint 200V/div., Ch.3:Vo 5V/div., Ch.4: Vin 200V/div., time scale: 50ms/div.].

The performance of the CPS during the voltage sag periodis as shown in figure 20. It can be seen from figure 20 thatCPS’s dc output voltage (Vo) is constant during the period ofvoltage sag. It can be observed from figure 20(b) that, for theload power of 200W, the pre-regulator output voltage dipsby 20V before returning to its rated operated value, owingto the low bandwidth of pre-regulator voltage control loopwhich is around 23Hz. It can be seen from figure 20 thateven during this period, the output voltage of the CPS (V0)is maintained constant for both 70W load and 200W loads.

6. Conclusions

This paper explains the hardware, control design and startupcircuit design and operation of a CPS rated to supply 250Wto the control circuitry of HPC. The CPS allows wide vari-ation of input voltage from 90Vrms to 270Vrms while main-taining dc output voltage of Vo = 24Vdc. The near unitypower factor operation of CPS over the wide input voltagevariation for various loading conditions has been observed.Low THD is observed in input current for various ac inputvoltages as well as loading conditions. The response of thesystem for step change in load for both pre-regulator and

DSFC is observed individually, and it matches the designanalysis. The CPS’s dynamic performance is also observedunder input voltage sag condition and is found to be good.Thus based on the response time for step load change andvoltage sag studies, the control system design of CPS meetsthe requirements of both pre-regulator as well as DSFC.Also, the starting procedure of CPS and its advantages arediscussed. The working of start-up power circuit during shutdown period is analyzed. The experimental results also ver-ify the design criteria of on board power supply, gate drivecircuits of pre-regulator, DSFC and start up circuit. Theworking of start-up power circuit and on-board power sup-ply for CPS is found to be quite efficient under variousloading and input line conditions. Such a CPS can be usedin a HPC that is required to meet low voltage ride throughrequirements.

Acknowledgements

The authors would like to thank DST IRHPA, India,under project “Facility for design, development anddemonstration of advanced batteries and ultracapacitors(Proj.No:S1/CV/1001/2010)” for their financial support inthis work.

High performance LVRT power supply 159

Appendix I

The part numbers of various components used in boost andDSFC’s gate drive circuits and start-up power circuit aretabulated in Appendix 1(a–c).

Design values of (a) Pre-regulator gate drive circuit; (b)Start-up power circuit; (c) DSFC gate drive circuit.

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