high-frequency ic design & test webinar part 2 (test)€¦ · cover actual product development...
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High-Frequency IC Design & Test Webinar
Part 2 (Test)
Inphi CorporationJune 25, 2003
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IntroductionIntroduction! Why this webinar is important
– Attendees will learn innovative techniques for high-frequency and high-speed design. This seminar will give engineers access to experts who will share techniques applicable for design and test.
! What to expect– This webinar focuses on best practices for high-frequency and
high-speed design and test. Development engineers will present techniques for creating leading-edge products. All presentations cover actual product development and test results.
! Who should attend– Engineers developing instrumentation, military, microwave, or
optical network equipment components, modules, or subsystems. The common thread is high-frequency and broadband design at 0–5 GHz and up to 0–100 GHz, and the drive for significant performance improvements.
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LogisticsLogistics! If you experience any technical difficulties, call
WebEx technical support– (866) 779-3239 toll free– (916) 463-8262 toll
! Brief Q&A session to follow each presentation– Please submit questions online using the Q&A tab– If you have additional questions following the event,
please send an email to [email protected]
! To download the presentation after the event, please visit www.inphi-corp.com and follow the instructions on the home page
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June 25, 2003 Page 4
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Outline Outline ! Test Equipment Needs and Limitations
– Dr. Kevin Nary, VP Engineering
! Jitter Measurements for ≥10 Gbps PMD ICs– Dr. Steffen Nielsen, Principal Design Engineer– Dr. Paul van der Wagt, Principal Design
Engineer
! Frequency Domain Measurements for High-Speed PMD ICs– Dr. Carl Pobanz, Principal Design Engineer
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Test Equipment Needs and LimitationsDr. Kevin Nary, VP of Engineering
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OverviewOverview! Characterization of broadband (1–60 GHz) ICs
– Devices under test (what are we characterizing)– Equipment requirements– Cables, connectors
! Understanding the test set– Equipment limitations– Calibration
! A real world example– Sampling head differences, bandwidth limits,
models
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What Are We Testing?What Are We Testing?! Optical components
– 10 & 40 Gbps modulator drivers, transimpedance amplifiers, NRZ-to-RZ converters, multiplexers, demultiplexers
! Very high speed logic circuits – Type D and T flip-flops, dividers, fanout buffers, encoders,
XOR/NOR/NAND gates, etc.
! Microwave components– Prescalers, VCOs, active splitters
! Process technologies– Fine-line CMOS, SiGe BiCMOS, GaAs pHEMT, InP, etc.;
60–180 GHz transistor Fts
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Packaged DevicesPackaged Devices50 Gbps InP HBT
D Flip-Flop10 Gbps GaAs pHEMT
Modulator Driver43 Gbps GaAs pHEMT
Modulator Driver
Evaluation Board 25 Gbps D Flip-Flop50 Gbps InP HBT 4:1 MUX
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Wafer-Level CharacterizationWafer-Level Characterization! Automated wafer probe with RF probes
enables rapid characterization of designs at speed over temperature
! Automated wafer probe with RF probes enables rapid characterization of designs at speed over temperature
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Equipment NeedsEquipment Needs! Time domain characterization
– Signal sources: synthesizers, pattern generators– High-speed sampling scopes
! Time domain characterization– Signal sources: synthesizers, pattern generators– High-speed sampling scopes
Anritsu MG3690A Synthesizer
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Equipment Needs (con’t.)Equipment Needs (con’t.)! Time domain characterization
– Bit error rate testers (BERTs)! Time domain characterization
– Bit error rate testers (BERTs) Anritsu ME7760A 43.5 Gbps BER test system
Agilent 81250 ParBERT with 4868A mux and 4869B demux
4-channel, 12.5 Gbps error detector
4-to-1, 43 Gbps mux1-to-4, 43 Gbps demux
4 X 12.5 Gbps Pattern Generator
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Equipment Needs (con’t.)Equipment Needs (con’t.)! Frequency domain
– Network analyzers– Spectrum analyzer– Phase noise analyzer
! Frequency domain– Network analyzers– Spectrum analyzer– Phase noise analyzer
Agilent PSA Series Spectrum Analyzer
Anritsu ME7808A 40 MHZ to 110 GHz Vector Network Analyzer
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Cables & ConnectorsCables & Connectors! Understand bandwidth, loss characteristics of
cables, connectors, probes . . .– Cable attenuation – skin effect and dielectric loss
! Understand bandwidth, loss characteristics of cables, connectors, probes . . .– Cable attenuation – skin effect and dielectric loss
Attenuation versus frequency of good 3.8 mm coax
DC
Atte
nuat
ion
(dB
/m)
1
2
3
4
25° C
85° C
10 20 30 40 50Frequency (GHz)
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Cables & Connectors (con’t.)Cables & Connectors (con’t.)! Connector and cable bandwidths
– Coax connectors and cables support higher order electromagnetic modes at frequencies dependant on their geometry and dielectric
! Connector and cable bandwidths– Coax connectors and cables support higher order
electromagnetic modes at frequencies dependant on their geometry and dielectric
Bandwidth of good 3.8 mm cable with different connectors
Fc = 2c π √ εr (D+d)
DC 10 20 30 40 50
SMA3.5 mm
N
2.4 mmK
Frequency (GHz)
V TE mode cutoff frequency GPPO
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Cables & Connectors (con’t.)Cables & Connectors (con’t.)! Understand bandwidth, loss characteristics of
cables, connectors, probes… – Example: TE cutoff frequency of SMA connector
! Understand bandwidth, loss characteristics of cables, connectors, probes… – Example: TE cutoff frequency of SMA connector
Response of 5.5 mm cable with SMA connector
-70
-60
-50
-40
-30
-20
-10
0
0 10 20 30 40 50Frequency (GHz)
dB
S11S21
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Real World ExampleReal World Example! Characterization of 10 Gbps modulator driver! Characterization of 10 Gbps modulator driver
Wafers come back from the fab… you get everything set up, turn on the supplies and test equipment, and get the ugly-looking eye shown here.
What’s going on?
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10 Gbps Modulator Driver Test Set10 Gbps Modulator Driver Test Set! What does the test setup look like?! What does the test setup look like?
Pattern Generator Oscilloscope
25” cable with 3.5 mm
connectors
3.5 mm connector
Wafer
Probes
2.4 mm connector
DC block36” cable with
3.5 mm connectors
2.4 mm to 3.5 mm adaptor
Test setup for wafer level test of 10 Gbps modulator driver
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Equipment DifferencesEquipment Differences! Characterize the sampling heads! Characterize the sampling headsVendor A Vendor B
10 Gbps pattern through cables, connectors, probes, 50 Ω through substrate to sampling head
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Test Set LimitationsTest Set Limitations! Calibrate all components! Calibrate all components
10 Gbps pattern generator connected directly to
sampling head
10 Gbps pattern through cables, connectors, probes,
50 Ω through substrate
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Modeling the Test SetModeling the Test Set! Correlation requires simulating the circuit with
electrical models of the test set ! Agilent EEsof ADS model for the test set
! Correlation requires simulating the circuit with electrical models of the test set
! Agilent EEsof ADS model for the test set
SCOPE
SCOPE
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Modeling the Test SetModeling the Test Set! Electrical models for sources, probes and scope! Electrical models for sources, probes and scope
GSG Probe
Sampling Head
Data & Clock Sources
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Sampling Head: Model vs. MeasuredSampling Head: Model vs. Measured! Correlate measured and simulated results
for each component in the test set– Sources, sampling head
! Correlate measured and simulated results for each component in the test set– Sources, sampling head
Measured (10 Gbps) Simulated (10 Gbps)
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Test Set: Model vs. MeasuredTest Set: Model vs. Measured! Good correlation between measured and
simulated results of the test enables correlation of DUT
! Good correlation between measured and simulated results of the test enables correlation of DUT
Simulated (2 Gbps)Measured (2 Gbps)
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June 25, 2003 Page 24
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Summary Summary ! Know the characteristics and limitations
of your cables, connectors, and probes
! Know the limitations of your equipment
! Model and correlate all equipment used in time domain characterization so that you can correlate measurement and simulation of the DUT
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Jitter Measurements for ≥ 10 Gbps PMD ICsDr. Steffen Nielsen, Principal Design Engineer
Dr. Paul van der Wagt, Principal Design Engineer
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Overview! Equipment limitations at ≥ 10 Gbps! Jitter basics
– Jitter spec in data sheets– Jitter components– Jitter and scope eyes
! Measuring random jitter! Measuring deterministic jitter
– Shortcut– Edge-by-edge method– DCD– Example
! Summary
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Equipment Limitations at ≥ 10 Gbps
! Advanced jitter analysis equipment not available at present– Lack of sufficiently fast real-time sampling
scopes (roughly ≥ 40 Gbps would be needed)
! 50–70 GHz equivalent time sampling scope (DCA) readily available – let’s try to use that…
! Equipment impacts measurement accuracy – use the best you have
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Jitter Spec in Data SheetsJitter Spec in Data Sheets! Added jitter is key parameter for PMD ICs
– Some spec total output jitter" Only valid if you have a jitter-free input
(a clocked driver is close)– Must be separated into random jitter
(RJ) and deterministic jitter (DJ) components to correctly predict system margins
– Pattern must be stated for DJ spec
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Jitter ComponentsJitter Components! Random jitter (RJ)
– Unbounded value, rms “unit”– Thermal noise, shot noise
! Deterministic jitter (DJ)– Has a pattern-dependent probability density– Bounded value, peak-to-peak “unit”– Intersymbol interference (ISI), coupling, duty
cycle distortion (DCD), supply noise
! Some deterministic jitter can look random depending on the measurement technique used (e.g. DJ uncorrelated to trigger)
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Jitter & Scope EyesJitter & Scope Eyes! “Jitter” is convolution of DJ and RJ components
! DJ also has a probability density (though bound)
! DJ often buried in a pseudo-Gaussian distribution (no distinct double peaks)– No double peaks does NOT mean no DJ!
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Jitter & Scope Eyes (con’t.)Jitter & Scope Eyes (con’t.)! Why DJ generally isn’t the distance
between the peaks
! DJ extends beyond peaks!
DJ
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Measuring Added Jitter Using DCAMeasuring Added Jitter Using DCA
DUTPPGDCA
! Measure DUT output as well as input– Eliminates source / setup DJ and potential
DCA time base wander problem– Use a low jitter input whenever possible in
order to get accurate added jitter numbers– Clocked DUTs: measure CLK instead of
DUT input data
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Added Random JitterAdded Random Jitter! 1010 pattern, trigger on either edge
! Measure rms value: 2IN
2OUTDUT RJRJRJ −=
! Triggering on one edge prevents DCD effects
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Added Deterministic JitterAdded Deterministic Jitter! DJ transfer input # output is unknown
! Thus one cannot assume thatDJDUT = DJOUT – DJIN
?
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Estimating DJEstimating DJ! Bounds on added DJ can be found from input and output
eyes alone (sum and difference are extremes)! Measure input and output DJ (eye mode, few samples to
avoid outer RJ tails in result, peak-to-peak measurement)
– Above example results in 3.7 ps ≤ DJ ≤ 7.1 ps (a clean input is important here)
– This method does not yield the exact added DJ value!
1.7 ps 5.4 ps
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Edge-by-Edge MethodEdge-by-Edge Method! Pattern trigger, use averaging (more is better), max
horizontal resolution (e.g. Maxim app note)! Measure bit-aligned input & output simultaneously to
eliminate DCA time base wander
Problem: DCA accuracy with large time span– 27 – 1 @ 10 Gbps, 4050 points # 3 ps resolution
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Edge-by-Edge Method (con’t.)Edge-by-Edge Method (con’t.)! Walk through entire pattern in high time resolution
mode, e.g. 2 bits span → 100 fs resolution
Problems– Very time consuming when averaging– Limits pattern length to < 1000 bits in reality
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Edge-by-Edge Method (con’t.)Edge-by-Edge Method (con’t.)
! Measure delay between all falling input / output edge pairs – define ∆fall = tpdfmax – tpdfmin
! Measure delay between all rising input / output edge pairs – define ∆rise = tpdrmax – tpdrmin
! DJpp = max ∆fall , ∆rise
! Method does not include DCD in DJ number– This automatically separates DCD from correlated DJ
! Uncorrelated DJ not captured
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DCD MethodDCD Method! 1010 pattern, trigger on either edge! Averaging on (eliminates RJ & uncorrelated DJ)! Measure narrow pulse width! Calculate peak-to-peak jitter by
DJDCD, pp = 1/B – PW
PW
1 / B
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Example: 1015EA Electro-Absorption Driver
Example: 1015EA Electro-Absorption Driver
! PRBS 27 – 1 @ 10.7 Gbps, 4050 points
! Added RJ = 240 fs rms
! Added DJ outer bounds: 3.7 ps ≤ DJ ≤ 7.1 ps
! Added DJ – accurate measurement– DJ = 5.4 ps with averaging = 16 (time 5 min)– DJ = 4.6 ps with averaging = 64 (time 20 min)
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ConclusionsConclusions! For 10 Gbps and beyond, measuring
added deterministic jitter accurately is difficult but important
! High accuracy is time consuming and not well suited for production test
! With a very clean input, the outer bounds of added DJ can be estimated quickly with reasonable accuracy
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Frequency Domain Measurements for High-Speed PMD Integrated Circuits
Dr. Carl Pobanz, Principal Design Engineer
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Frequency Domain Measurements! Discussion will focus on network analysis for 10 & 40
Gb/s lightwave physical media–dependent (PMD) ICs – Data amplifiers, modulator drivers, TIAs
! PMD ICs for telecom / datacom are “time domain” components – why consider frequency domain at all?
Time Domain Frequency Domain
Rise / Fall TimeJitter
Overshoot
Amplitude BandwidthPhase Noise
Group DelayReturn Loss
Gain
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Frequency Domain Network Analysis! Vector network analyzers (VNAs)! Truly calibrated in-situ measurements at high frequencies (> 1 GHz)
– Remove all effects of attenuation, dispersion, reflections in cables and test fixtures. Can define and translate reference planes.
– Very difficult to do in time domain – no commercial instrumentation available (prototype: Agilent LSNA – Large Signal Network Analyzer1)
! Impedances are naturally handled in freq domain (e.g. Smith chart)
! Limitations for PMD ICs– Assumes “linear” time-invariant circuits under small-signal excitation
" Digital circuits, limiting / switching drivers are neither . . .
– Mapping measured parameters to time domain is often non trivial
" Bandwidth # rise time, group delay # deterministic jitter, etc.
" Not always a useful exercise
1J. Scott, et al., 2002 IEEE MTT Symposium
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Network Analysis: Differential Circuits! Differential PMD integrated circuits
– 16 “mixed mode” S-parameters, complete analysis requires 4-port VNA
– Balanced DUT may be measured one mode at a time with 2-port VNA
" Requires 180° hybrid balun" Band limited – frequency range typically 3 octaves max" Must fabricate calibration standards – can use TRL" Mode conversion is not allowed, symmetry is critical
DUT
Common / Even Mode (Σ)Differential / Odd Mode (∆)
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Differential PMD Circuits (con’t.)! Transmission
– Symmetric differential ICs # high common mode rejection (CMR)– Measure single-ended gain, add +6 dB for differential output
! Reflection– Differential & common mode impedances with 2-port VNA technique
(S11 + S22) – (S21 + S12)2ΓDIFF =
(S11 + S22) + (S21 + S12)2ΓCM =
port 1port 2
2-port VNA
50 50
200
GND Differential mode50 Ω each side to ground
Common mode450 Ω each side to ground
Example:“not so good”
CML input stage
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Typical Spectrum of Data Signals in PMD Circuits
tr = 2 ps(0.1 UI)
tr = 10 ps(0.4 UI)
40 GHz 40 GHz80 GHz 80 GHz
40 Gbps NRZ 215 – 1 PRBS spectrum
Discrete tones related to PRBS sequence length fn = n fclk / (2m – 1) or data frame rate
1.22 MHz0 Hz
40 Gbps Data Lowest Tone27 – 1 PRBS 315 MHz215 – 1 PRBS 1.2 MHzSONET OC-768 8.0 kHz231 – 1 PRBS 18.6 Hz
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Effect of Low Frequency Cutoff on NRZ Data
! LF cutoff removes lowest discrete tones in data spectrum– Causes droop on long consecutive bit runs– Another view: “negative tones” added that upset baseline level– Baseline ripple occurs at these tone frequencies
! DC blocking capacitors– Typically 0.1 µF in 50 Ω system, flow = 16 kHz
# Cutoff causes deterministic jitter, “fuzz” on eye rails
8 kHz cutoff 50 kHz cutoff
20 µs/div 20 µs/div
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Modulator Drivers / Limiting Amplifiers! Two major architectures
– “Microwave” distributed / traveling wave amplifiers (TWAs)– Switching drivers based on differential pair circuits
! Typical VNA measurementsGain (S21)
" Not always measurable or usefulReturn loss (S11, S22)
" Output impedance is time varying in switched circuits
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Bandwidth vs. Rise Time in Linear Circuits
Linear, first-order system with time constant τ
3 dB bandwidth fo = 2π τ1
Rise time tr = τ HI %ln ( )LO %
fo · tr = HI %ln ( )LO %2π
1
Bandwidth–rise time product # 350 GHz-ps (10–90%)# 220 GHz-ps (20–80%)
# Relationship also holds empirically for higher-order systems with damped (monotonic) step response, typ. < 5% error for < 5% overshoot
Ref: M. S. Ghausi, Principles and Design of Linear Active Circuits, Ch. 16, 1965
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Bandwidth vs. Rise Time: “Quasi Linear” Amplifier
Example: Inphi® 2010DZ Dual MZ Modulator Driver (GaAs pHEMT)
– 18 GHz small-signal BW3-dB
– 12 ps rise time (20–80%)– Typically 3 dB into compression # weakly limiting– Bessel-type response / flat group delay # very low jitter
typical on wafer
10 Gbps measured on wafer
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Bandwidth vs. Rise Time: Limiting Amplifier
Example: Inphi® 1310SZ MZ Modulator Driver (InP DHBT)
6.5 GHz small-signal BW with < 25 ps rise time# Linear estimate 220 GHz-ps / 6.5 GHz = 34 ps !?
# Operates in a fully switched, nonlinear mode
10 Gbps measured on wafer
typical on-wafer
25
50
40
30
20
10
S21
(dB)
FREQUENCY (GHz)
0 0 5 10 15 20
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Bandwidth vs. Rise Time in Limiting Amplifiers
Switching / limiting decreases rise time
– Fundamentally nonlinear– Effective bandwidth increased by harmonic generation
# Bandwidth–rise time relation falls apart
INPUT100 mV p-p
OUTPUT1 V p-p
OUTPUT RISE TIME
INPUT RISE TIME
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Measuring S21 of a Limiting Amplifier = Trouble
expected
measured
– Eye diagram, jitter looks fine on an oscilloscope…– What’s going on?
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Measuring S21 of a Limiting Amplifier! Limiting fixes b2 amplitude, ratioed measurement fails
– Display tracks reciprocal of source power a1 variation vs. frequency– Strange, jagged S21 response– Usually occurs at low frequency (where source power is highest)
! Measurement is bogus!– Need to reduce and/or level VNA source power– Then will data be meaningful? …
Typical VNA test set (Agilent 8510C)Unleveled source power a1
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Bandwidth of Limiting PMD Amplifier/Driver! Small-signal S21 can be measured on a VNA with low source power
! A “large-signal” S21 can be measured with VNA + source leveling – Is this useful?
" Large-signal swept tone is NOT representative of data signal" Random NRZ data has sinc2(f) type power spectral density" Data signal compresses amplifier more at low frequencies" Effective “data bandwidth” is greater than what VNA will measure
! Rise time is the true measure of speed
Large-signal S-parameter(LSSP) simulation of 10 Gbps driver using Agilent ADS
0
5
10
15
20
25
0 5 10 15 20 25FREQUENCY (GHz)
S21
(dB)
small-signal input # BW3-dB = 15 GHz
0.7 V p-p 10 Gbps equivalentsinc2(f) input # BW3-dB = 20 GHz
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Driver Output Return Loss! Output impedance is time varying with data signal! Can measure S22 with output state ‘1’ (Vhigh), ‘0’ (Vlow) or balanced
– Mostly in ‘1’ or ‘0’ state during operation, but spec sheets show balanced– ‘0’ state is typically worst case
" FET / HEMT driven into triode region (output conductance ↑)" Bipolar / HBT driven into quasi-saturation (output capacitance ↑)
10
BAL
Typical output return loss of 10 Gbps switching driver
(3 states)
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Conclusions
! Frequency domain measurements for PMD ICs are useful even for time domain circuits
! These measurements provide valuable insight into both single-ended and differential devices
! Be aware of limitations with nonlinear / switching circuits
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Reference MaterialReference Material
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Presenter BiographiesPresenter BiographiesDr. Kevin Nary, Vice President of Engineering. Dr. Kevin Nary has nearly 20 years of engineering experience with multiple corporations and organizations. Dr. Nary began his career at Westinghouse performing IC failure analysis and then joined Harris Semiconductor, where he assessed and improved Si bipolar and MOS IC reliability. During his graduate study, he designed a 26 GHz variable modulus prescaler for Hewlett Packard and a 3 GHz MESFET automatic gain control amplifier. More recently, he was President and CEO of Celerix, an IC design house, and manager of integrated circuit development at W.L. Gore and Associates. Dr. Nary holds a Ph.D. in electrical engineering from the University of California, Santa Barbara, an M.S. in applied physics from John Hopkins University, and a .B.S. in physics from the College of William and Mary.
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Presenter Biographies (con’t.)Presenter Biographies (con’t.)Dr. Steffen Nielsen, Principal Design Engineer. Dr. Nielsen has applied his extensive experience in high-speed mixed-signal analog circuit design at such companies as Ericsson, Conexant, and Vitesse. His circuit designs include 40 Gbps InP HBTs, clock and data recovery circuits and demultiplexers, limiting amplifiers, and laser drivers. Dr. Nielsen has also designed a variety of 10.7 Gbps 0.13µm CMOS circuits, including output drivers and VCOs. In 12.5 Gb/s SiGe BiCMOS, he has designed CML cell libraries, including output drivers and VCOs, limiting amplifiers, multiphase LC-VCO, and 16:1 multiplexers. Dr. Nielsen received his Ph.D. from the Technical University of Denmark, where he wrote a thesis entitled “Multi-Gigabit ASIC Design” focused on demonstrating 10 Gbps clock and data recovery circuits in standard silicon bipolar technology.
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Presenter Biographies (con’t.)Presenter Biographies (con’t.)Dr. Paul van der Wagt, Principal Design Engineer. Dr. van der Wagt has 15 years of experience in high-speed IC design and device modeling. At Inphi, he has developed high-speed logic ICs with clock rates up to 50 Gbps. Previously, he was a senior scientist at Rockwell Scientific, where he designed world-record bandwidth track-and-hold circuits for commercial use. From 1995 to 1998, Dr. van der Wagt designed and fabricated quantum device circuits for ultra high speed analog-to-digital converters and low-power memory at Texas Instruments Central Research Labs. He holds 12 patents, has authored or coauthored more than 30 papers, and is a senior member of the IEEE. Dr. van der Wagt holds M.S. and Ph.D. degrees in Applied Physics from Stanford University in addition to two M.S. degrees from Twente University, The Netherlands.
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Presenter Biographies (con’t.)Presenter Biographies (con’t.)Dr. Carl Pobanz, Principal Design Engineer. Dr. Pobanz is an authority in high-frequency integrated circuit design. At Inphi, he has designed broadband driver ICs for 10 and 40 Gbps optical systems. Throughout his career, Dr. Pobanz has developed HEMT low-noise amplifiers for Ka-band space applications, InP-based LNAs, multipliers, mixers, and power amplifier MMICsfor 10–200 GHz systems. Published designs include millimeter-wave IC amplifiers with record high frequency and low noise performance. Dr. Pobanzcame to Inphi from Broadcom, where he contributed to the design of 10 Gbps Ethernet SERDES and satellite TV tuner integrated circuits in CMOS. Dr.Pobanz received his B.S., M.S., and Ph.D in electrical engineering from the University of California, Los Angeles.