high frequency divider (ilfd)...ilfd prog. div pfd + cp チップ写真 lpf 1350um* 1100um vbt v dd...

0.455 0.46 0.465 0.47 0.475 0.48 24 18 19 20 21 22 23 Bias Voltage (V) Frequency (GHz) 22 17 17.5 18 18.5 19 19.5 20 20.5 21 21.5 5 -25 -20 -15 -10 -5 0 Frequency (GHz) Input Power (dBm) Locking Range 10 3 10 4 10 5 10 6 10 7 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 Phase Noise plot 19.44GHz 70uA 50uA 30uA 10uA 10 3 10 4 10 5 10 6 10 7 -140 -130 -120 -110 -100 -90 -80 -70 -60 50uA 30uA 10uA 65nm 65nm Process 1.2 1.2 Supply (v) 88.8 58.8 Total Power (mW) -94 to -97 -95 to -100 PN1MHz (dBc/Hz) -60 to -49 -71 to -51 Ref. Spurs (dBc) 19.44, 20.16, 20.74 GHz 19.44, 20.16, 20.88, 21.6 Freq. lock 17.8 – 21.4 (18.4%) 19 – 23 (19%) VCO Freq (GHZ) Measurement Sim/Cal 65nm 65nm Process 1.2 1.2 Supply (v) 88.8 58.8 Total Power (mW) -94 to -97 -95 to -100 PN1MHz (dBc/Hz) -60 to -49 -71 to -51 Ref. Spurs (dBc) 19.44, 20.16, 20.74 GHz 19.44, 20.16, 20.88, 21.6 Freq. lock 17.8 – 21.4 (18.4%) 19 – 23 (19%) VCO Freq (GHZ) Measurement Sim/Cal High Frequency Divider (ILFD) Simulation Measurement P V inj M1 M2 VDD VBias V + V - VBias + - + - + - + - + - + - Rf+ Rf - シミュレーションと実測結果の比較 Simulation Measurement Process 65nm 65nm Supply Voltage 1.2 1.2 Lock Range (GHz) 3 2.17 Total Lock Range - 12 ~ 26.15 (GHz) Free Running Freq. Range (GHz) Less then 1 ~ 17 0.27 ~ 9.48 Current (Inc. Buffer) 5.7mA 6.8mA Simulation Measurement Process 65nm 65nm Supply Voltage 1.2 1.2 Lock Range (GHz) 3 2.17 Total Lock Range - 12 ~ 26.15 (GHz) Free Running Freq. Range (GHz) Less then 1 ~ 17 0.27 ~ 9.48 Current (Inc. Buffer) 5.7mA 6.8mA 広いロックレンジをカバー周波数に対応したバイアス電圧チップ写真 380um *270um チップ写真 200um* 170um 高いQ値で発振させた20GHz 信号をインジェクションすることによって， PN=-97dBc/Hz の低位相雑音な信号を出力 VCO ILFD Prog. div PFD + CP LPF チップ写真 1350um* 1100um Vbt V DD L このPLLに接続可能なILOの設計チューナブルにしているLPFやCPをスリム化し，最適化を図る．より広帯域な周波数で駆動させる． 4Gbps

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0.455 0.46 0.465 0.47 0.475 0.48

24

18

19

20

21

22

23

Bias Voltage (V)

Fre

qu

en

cy (

GH

z)

2217 17.5 18 18.5 19 19.5 20 20.5 21 21.5

5

-25

-20

-15

-10

-5

0

Frequency (GHz)

Inp

ut

Pow

er

(dB

m) Locking Range

103 104 105 106 107-130

-120

-110

-100

-90

-80

-70

-60

-50

-40Phase Noise plot 19.44GHz

70uA50uA30uA10uA

103 104 105 106 107-140

-130

-120

-110

-100

-90

-80

-70

-6050uA30uA10uA

65nm65nmProcess1.21.2Supply (v)

88.858.8Total Power (mW)-94 to -97-95 to -100PN1MHz (dBc/Hz)-60 to -49-71 to -51Ref. Spurs (dBc)

19.44, 20.16, 20.74 GHz19.44, 20.16, 20.88, 21.6Freq. lock17.8 – 21.4 (18.4%)19 – 23 (19%)VCO Freq (GHZ)

MeasurementSim/Cal

65nm65nmProcess1.21.2Supply (v)

88.858.8Total Power (mW)-94 to -97-95 to -100PN1MHz (dBc/Hz)-60 to -49-71 to -51Ref. Spurs (dBc)

19.44, 20.16, 20.74 GHz19.44, 20.16, 20.88, 21.6Freq. lock17.8 – 21.4 (18.4%)19 – 23 (19%)VCO Freq (GHZ)

MeasurementSim/Cal

High Frequency Divider (ILFD)

Simulation Measurement

PVinj

M1 M2

VDD

VBias

V+ V-

VBias

+

- +

- +

- +

-+

- +

-

Rf+Rf -

シミュレーションと実測結果の比較

Simulation Measurement

Process 65nm 65nm

Supply Voltage 1.2 1.2

Lock Range (GHz) 3 2.17

Total Lock Range - 12 ~ 26.15 (GHz)

Free Running Freq. Range (GHz) Less then 1 ~ 17 0.27 ~ 9.48

Current (Inc. Buffer) 5.7mA 6.8mA

Simulation Measurement

Process 65nm 65nm

Supply Voltage 1.2 1.2

Lock Range (GHz) 3 2.17

Total Lock Range - 12 ~ 26.15 (GHz)

Free Running Freq. Range (GHz) Less then 1 ~ 17 0.27 ~ 9.48

Current (Inc. Buffer) 5.7mA 6.8mA広いロックレンジをカバー

周波数に対応したバイアス電圧

チップ写真

380um*270um

チップ写真

200um*170um

高いQ値で発振させた20GHz信号をインジェクションすることによって，PN=-97dBc/Hzの低位相雑音な信号を出力

VCOILFD

Prog.div

PFD + CP

LPFチップ写真

1350um*1100um

Vbt

VDD

L

このPLLに接続可能なILOの設計チューナブルにしているLPFやCPをスリム化し，最適化を図る．

より広帯域な周波数で駆動させる．

4Gbps