High Energy Density Charge Storage Capacitors

Martin Peckerar, Neil Goldsman, Zeynep Dilli

Department of Electrical and Computer Engineering

University of Maryland

College Park, MD 20742

Where the Capacitor Fits Into the System

“Rectenna”

StorageCapacitor Block

Microwave In

To System

The Basic Capacitor Structure

N+ Silicon

Metal

Hi-k Dielectric

a. Cross-section of a corrugated capacitor

b. Disposition of the silicon posts in the Corrugated array

LAYOUT WITHIN A CHIP

a

a

b

b

c

c a+b=k, a constant

c=250 microns

An n x n array, where:n=(9500/(a+b))

1 cm

1 cm

1mm

1mm

a11

b11

a12

b12

a21

b21

An m x m array, where:m = 8

aij + bij=cij

cij=160microns/(i+j)

Plate Layout

aij=(8-i)cij /8 bij=icij/8

i and j range from 1 to 8

GDS2 “Blow-Back”* Chip-In Mask Layout

Blow-up of corner squareShowing pillar tops

*This is a graphic display of theactual data used to prepare the mask

In-Chip GDS2 “Blow-Back”

Goal of the Experiment

The varying aspect ratio of the pillars will allow us to make a curve like the following:

capacitance

aspect ratio

yielding

Zero-yield

Process Flow

start

etch

dope

insulate

metal

The Final Step: Stacking the Battery Tiles

1cm

1cm

< 0.01cm