case of multicarrier amplifiers, a feedforwardconcept. What is paramount, however, is toensure that the RF power amplifier deliversthe required base performance. This articledescribes the trade-offs between linearity, gainand efficiency that can be made for state-of-the-art LDMOS technology.

AMPLIFIER PARAMETERS In order to meet the stringent linearity re-

quirements, base station RF power transistorsare operated at a much lower power levelcompared to their actual power capability.This is because most system standards usemodulation schemes where the peak powerlevels are much higher than the average out-put power. For an EDGE GSM system, for in-stance, the peak-to-average-ratio (PAR) is alittle over 3 dB. For WCDMA systems, it canvary between 6 and 10 dB, or even higher in

P.C.A. HAMMES, H.F.F. JOS, F. VAN RIJS, S.J.C.H. THEEUWENAND K. VENNEMAPhilips SemiconductorsNijmegen, The Netherlands

OEMs, operators and manufacturers ofbase station RF power amplifiers areconstantly striving for greater efficien-

cy, whether it be in the number of connec-tions (calls) that can be made via a base stationor the amount of DC power needed to makethose calls. For both scenarios, the RF poweramplifier plays a key role. First, it is the partof a base station that consumes the most DCpower in order to generate the substantialamount of RF power required to maintain areliable wireless connection for many users.Second, the linearity of the power amplifierdetermines how many calls can be handled re-liably without creating significant interferencein neighboring channels in the assigned fre-quency bands. Today, laterally diffused metaloxide semiconductor (LDMOS) technology isthe choice for base station RF power ampli-fiers because it is reliable, and meets currentmarket needs for performance and cost, witheven greater performance improvements pos-sible if the LDMOS technology is further re-fined.

Common techniques to improve efficiencyat the power amplifier level are the Dohertyprinciple, (digital) pre-distortion and, in the

HIGH EFFICIENCY, HIGH POWER WCDMALDMOS TRANSISTORSFOR BASE STATIONS

Reprinted with permission of MICROWAVE JOURNAL® from the April 2004 issue.©2004 Horizon House Publications, Inc.

the case of multicarrier amplifiers,depending on how capable the soft-ware algorithms are in reducing thecrest factor. Figure 1 shows the con-tinuous wave power capability of a100 W WCDMA (UMTS) LDMOStransistor1 that uses the current tech-nology. Power gain and drain efficien-cy are shown.

At Pout = 100 W the power gaincompression is 1 dB. Theoretically,considering a PAR of about 6 dB, andin order to avoid significant distortionunder WCDMA signal conditions,the device can be operated at a pow-er level of approximately 25 W.Where the device efficiency is 50percent at 100 W, at 6 dB back-off, itis about 26 percent. For previousgenerations of LDMOS the efficiencywould be around 18 percent. Evenwith a higher PAR, the device is still

able to meet the linearity require-ments and maintain good drain effi-ciency.

Typical linearity requirements un-der a two-carrier WCDMA signal(PAR = 8.5 dB at 0.01 percent proba-bility of the cumulative distributionfunction (CDF), that is the chancethat a peak 8.5 dB above the averageoutput power will occur) are –40 dBcfor the adjacent channel and –37 dBcfor the intermodulation distortion(IMD) product generated by the twocarriers. Figure 2 shows the two-car-rier WCDMA performance for thesame transistor.1 The linearity re-quirements are met at an RF outputpower of 43.6 dBm (approximately 23W). Obviously the relationship be-tween the average output power andPAR does not hold up for the full 100percent, since 43.6 dBm plus a PARof 8.5 dB adds up to 52.1 dBm, whichis well beyond the P1dB capability ofthe device.

The other parameter that is im-portant in order to meet a particularlinearity, in conjunction with theprobability on the CDF of the pre-sented input signal, is the peak powercapability of the LDMOS transistor.Appendix A presents the peak powercapability of the featured LDMOStransistor, where a pulsed continuouswave signal is used with a small duty

cycle (about 0.8percent) to measurethe peak power.

It could be ar-gued that it wouldmake more sense tochoose the duty cy-cle such that the av-erage power underpulsed conditionswould be more rep-resentative of theactual average

WCDMA power,

which would actually lower the re-ported peak power capability. It can-not be said that there is a 100 percentcorrelation between peak power ca-pability of a transistor and achievablelinearity. The fact is, though, that ahigher peak power capability will re-duce the amount of clipping of sig-nals with high peak-to-average ratios,and thus create a transistor that willbetter fit in a base station amplifiersystem environment.

AMPLIFIER EFFICIENCYHaving identified the important RF

parameters of a UMTS LDMOS basestation amplifier, the overall benefit ofbetter LDMOS technology can be de-termined. Figure 3 shows a block dia-gram of a UMTS amplifier arrange-ment using two of the featured 100 Wdevices in the final stage, driven by a30 W LDMOS transistor. Figure 4presents a similar arrangement, nowusing a previous LDMOS generationin the final stage.2 Both are testedwith a two-carrier WCDMA signal,and in both cases the amplifier needsto meet an IMD requirement of –37dBc and an adjacent channel powerratio (ACPR) of –40 dBc.

It can be seen from these last twofigures that the current technologydevices are 6.7 percent more efficientunder two-carrier WCDMA condi-tions. It can be concluded that an am-plifier with such LDMOS technologydraws about 2.2 A (or 61.6 W DC in-put power at Vsupply = 28 V) less cur-rent for the same output power andsame linearity. Most of the improve-ment comes from the inherentlymore efficient final stages.

The lower gain for the previousgeneration LDMOS results in theneed for a higher output power forthe driver transistor, although the in-crease in current is minimal. With thelatest LDMOS, the overall amplifier

TECHNICAL FEATURE

16

15

14

13

12

1152484440

Pout (dBm)

Vds = 28 V, Idq = 900 mA, f = 2140 MHz

363228

50

40

30

20

10

0

PO

WER

GA

IN (

dB)

DR

AIN

EFF

ICIE

NC

Y (%

)

35

30

25

20

15

10

5

04846444240383634

Pout (dBm)

Vds = 28 V; Idq = 900 mA; f = 2140 MHzTEST SIGNAL: 2 ¥ W-CDMA, 3GPP, TEST MODEL 1, 64 DPCH PAR = 8.5 dB @0.01%ACP @5 MHz offset from center of carriers in 3.84 MHz BWIMD @ 10 MHz offset from centerof carriers in 3.84 MHz BW

32302826

PO

WER

GA

IN (

dB);

EF

FIC

IEN

CY

(%)

−20

−25

−30

−35

−40

−45

−50

−55

AC

P (

dBc)

; IM

D (

dBc)

30 WGp = 15 B

Id = 715 mA

34.4 dBm2.75 W

2 ¥ 100 W GEN2Gp = 12.5 dB

Id = 4.19A each (19.5%)

VSUPPLY = 28 VDC POWER = 254.7 W

31.1 dBm 43.6 dBm

22.9 W1.29 W

46.3 dBm42.7 W

30 WGp= = 15 BId = 670 mA

33.4 dBm2.2 W

2 ¥ 100 W GEN4Gp = 13.5 dB

Id = 3.12A each (26.2%)

VSUPPLY = 28 VDC POWER = 193.5 W

30.1 dBm 43.6 dBm

22.9 W1.02 W

46.3 dBm42.7 W

efficiency is 22 percent, where previ-ously it was 16.8 percent. As a resultof this efficiency improvement, thedissipated power is reduced, which isa benefit with respect to heatsink de-sign and/or reliability of the amplifier.

LDMOS TECHNOLOGYOPTIMIZATION

The majority of the improvementsoutlined can be found in a proper de-sign of the gate shield, as well asproper drain and gate engineering ofthe LDMOS structure. However,there needs to be caution, since alter-ations to these parts of the LDMOSstructure may have a negative impact

on hot carrier degradation (resultingin Idq drift), breakdown voltage (re-sulting in a degraded ruggedness)and current capability, as well asdrain-source on-resistance (Rds-on)that can effect the peak power capa-bility of the transistor.

Figure 5 depicts a cross-section ofthe state-of-the-art LDMOS technol-ogy. It consists of a silicided poly-sili-con gate, a laterally diffused p-well, ap-sinker to connect the source to thehighly doped substrate and a lowlydoped drain extension region to ac-commodate high voltage operation. Ifthe drain extension is uniformlydoped and optimized for maximumoutput power, hot carrier degradationwill occur, which manifests itself bydrift in the quiescent current (Idq) at

constant Vgs. A step-wise doping pro-file, that is two lowly doped regions inthe drain-extension (LDD1 andLDD2),3 solves this problem at thecost of some RF performance.

However, the introduction of adummy gate as the shield4 gives abetter trade-off between Idq degrada-tion and RF performance. Due to theclose proximity of the shield to thegate and drain extension, the fielddistribution in the drain extensionimproves, reducing both degradationand feedback capacitance. Anothertrade-off now becomes dominant —that between the breakdown voltage(BV) and the current capability (Idsx)and on-resistance (Ron).

Figure 6 shows a novel steppedshield structure, which combines theadvantages of the improved field dis-tribution with a better current capa-bility and Ron. The step constructiondiminishes the pinching action of theshield near the channel giving an im-proved Ron and Idsx (see Figure 7),while BV is unaltered due to the ac-tion of the lower part of the shield.Figures 8 and 9 show the two-tonelarge signal RF performance. At lin-ear operation, at –40 dBc IMD3, theoutput power increases by 1 dB. Thelinearity-efficiency trade-off is alsoimproved by this novel stepped shield(+ 2 percent efficiency).

Furthermore, now that anLDD1-LDD2 profile is no longerneeded to keep hot carrier degrada-tion in control, it is advantageous touse a more heavily doped drain re-gion (HDD) locally, as shown withthe step shield structure in Figure10. Usually a higher drain dopingmeans a lower BV. However, when

TECHNICAL FEATURE

SOURCE

SHIELD

GATE

DRAIN

LDD1 LDD2 N+N+

P-SINKERDRAIN EXTENSIONP-TYPE EPI

P-SUBSTRATE

P-WELL

▲ Fig. 5 Typical cross-section of a state-of-the-art LDMOStechnology.

SOURCE

STEPPEDSHIELD

DRAIN

HDD LDD N+N+

P-SINKERP-WELL

DRAIN EXTENSIONP-TYPE EPI

P-SUBSTRATE

GATE

▲ Fig. 6 Cross-section of stepped shield with highly doped drainregion.

1.00

0.95

0.90

0.85

0.80

0.75

SHIELDCONSTRUCTION

DRAINCONSTRUCTION

STA

ND

AR

D

STEP

PED

LDD

UN

IFO

RM

HD

D

3.43.23.02.82.62.42.22.0

Ron

(W

)

I dsx

(A

)

▲ Fig. 7 Measured Ron and Idsx for the twoshields and three extensions constructions.

0-10-20-30-40-50-60-70

41373329Pout (dBm)

STEPPED SHIELDSTANDARD SHIELD

252117

IMD

3 (d

B)

▲ Fig. 8 IMD3 vs. Pout for a transistor with Wg = 18 mm, Vds = 26 V, f = 2.15 GHzand ∆f = 100 kHz.

0−10−20−30−40−50−60−70

47433935Pout (dBm)

STEPPED SHIELDSTANDARD SHIELD

3127231915

IMD

3 (d

B)

▲ Fig. 9 Measured IMD3 vs. efficiency forstandard and stepped shields.

DISTANCE

UNIFORMLDDHDD

DO

PIN

G C

ON

CEN

TRA

TIO

N

▲ Fig. 10 Doping profiles along the surfaceof a drain extension.

the HDD region is properly de-signed, the peak field in the re-maining drain extension does notchange (see Figure 11) and the BVremains unaltered. Also, the higherdoping concentration has a largeimpact on Ron and Idsx. Both im-prove significantly with the use ofan HDD. Figures 12 and 13 showthe two-tone large signal RF perfor-mance. At around –40 dBc IMD3,the output power increases by 2 dB,while the efficiency also improvesby 4 percent. With the higher dop-ing, the feedback capacitance in-creases, although this is limited tolow voltage.

Further improvements of the in-trinsic device efficiencies are wellwithin reach by further optimizingthe LDMOS structure, where it isreasonable to think of device efficien-cies well above 30 percent, whilepower gain will improve by morethan 2 dB.

RELIABILITYAnother key aspect in base station

amplifiers is the device reliability.The presented technology uses a duallayer gold metallization system, whichenhances the MTBF by a factor of 8.Therefore, it is possible to operatethe device at a 20° to 30°C higherjunction temperature, while main-taining similar MTBF figures com-pared to previous LDMOS genera-tions.

CONCLUSION With the presented LDMOS tech-

nology a 7 percent improvement intransistor efficiency has beenachieved under two-carrier WCDMAconditions for a 100 W WCDMALDMOS transistor, while maintaininglinearity and improving the powergain by 1 dB. ■

References1. K. Vennema, “MCPA for UMTS Using the

BLF4G22-100 LDMOS Transistor,” Appli-cation Note, Philips Semiconductors, Au-gust 2003.

2. B. Arntz and K. Vennema, “BLF2022-90:Linear LDMOS Amplifier for 3GPP Ap-plications in the 2110–2170 MHz Fre-quency Band,” Application Note, PhillipsSemiconductors, May 2001.

3. S. Xu, P. Foo, J. Wen, Y. Liu, F. Lin and C.Ren, “RF LDMOS with Extreme Low Par-asitic Feedback Capacitance and High HotCarrier Immunity,” International ElectronDevices Meeting Digest, 1999, pp. 201–204.

4. Xu, et al., “High Power Silicon RF LD-MOSFET Technology for 2.1 GHz PowerAmplifier Applications,” IEEE Internation-al Symposium on Power SemiconductorDevices Digest, 2003, pp. 190–194.

Petra Hammes studied electrical engineeringat Twente University, The Netherlands, andthen received her PhD degree at DelftUniversity, The Netherlands, in 1994. Shejoined Philips in 1995 to develop highfrequency transistors and is currently involvedin the development of LDMOS devices. Hermain interests include device and RFsimulations and RF measurements.

Rik Jos studied physics at the University ofUtrecht, The Netherlands, where he earned hisPhD degree in 1986. That same year he joinedPhilips to develop high frequency transistorsand has headed RF device technologydevelopment for the company since 1995. In2002, he was appointed Philips SemiconductorFellow. His main interests include theefficiency and linearity of RF devices. He is amember of IEEE and a subcommittee memberof the BCTM conference.

Steven Theeuwen received his MS degree inphysics from Eindhoven University ofTechnology in 1994. He subsequently went toDIMES to work on nanophysics andnanotechnology, and received his PhD degreefrom Delft University of Technology in 2000.He then joined Philips Semiconductors as anRF device physicist to develop high frequencytransistors. His current focus is on theefficiency and linearity of LDMOS powerdevices.

Korné Vennema received his BSEE degreefrom the HTS, Utrecht, The Netherlands. Hejoined Philips Semiconductors in 1987 and iscurrently a marketing application engineer, RFpower products, Foxboro, MA (US).

TECHNICAL FEATURE

DISTANCE

UNIFORMLDDHDD

ELEC

TRIC

FIE

LD

▲ Fig. 11 Electric field distribution at 26 V along the surface in the drainextension region.

0−10−20−30−40−50−60−70

41373329Po-avg (dB)Pout (dBm)

HDDUNIFORM DRAIN EXTENSIONLDD

252117

IMD

3 (d

B)

▲ Fig. 12 Measured IMD3 performance of an 18 mm device with different drainextensions at f = 2.15 GHz, Vds = 26 V and ∆f = 100 kHz.

0−10−20−30−40−50−60−70

47433935EFFICIENCY (%)

HDDUNIFORM DRAIN EXTENSIONLDD

3127231915

IMD

3 (d

B)

▲ Fig. 13 Measured IMD3 vs. efficiency fordifferent drain extensions.

Vds = 28 V, Idq = 900 mA,f = 2140 MHzPulsed CW: 8 µs on, 1 ms off

1 msec

Pou

t (d

Bm

)

56

55

54

53

52

51

50

49

48

47

464544434241403938

Pin (dBm)

P3 dB = 52.2 dBm (166 W)P1dB = 51.5 dBm (141.3 W)

373635343332

8 µsec

APPENDIX A PEAK POWER CAPABILITY