hierarchical conditional dependency graphs for false path identification

ISSS ’98

University of Rennes I IFSIC / IRISA C.Wolinski

Hierarchical Conditional Dependency Graphs for False Path Identification

A.Kountouris, C.Wolinski

ISSS ’98


Our New Co-design System Under Construction

HCDG

Specification :

SIGNAL, C, VHDL,

Code Generation

Transformations :

• scheduling

• partitioning

• optimization

Clock Calculation

Estimation of:

• timing

• size

• power

• memory

• etc.

Constraints

System Description

Parameters

C

VHDL

Assembly for Target Processor

Interface generation

Simulation

Synthesis

ISSS ’98


CCFG

TopologicalSort

High-levelspecification

Hardware C, C, VHDL, Signal

Final HCDG

Methodology used

• Scheduling under constraints• Hardware Resources Sharing• False Path Detection

Initial HCDG

Parsing

Hierarchization process

• redundant clock removal

• refining of clock inclusion relations

Treatment of arithmetic relations (rel. graphs) :

a > 5b < 5a < b

a

5b

Mutual Exclusiveness Detection Process

Clock Calculationfor each Path inCCFG Conditional Control Flow Graph

ISSS ’98


Hierarchical Conditional Dependency Graph

inc

?a

!b

?c

Nodes correspond to operations

that assign values to variables.

Clock hierarchy implemented as

a hierarchy of BDD trees and

represents the inclusion relations

between clocks

If H2 * H3 = false then H2 H3 and H2 H5 ( H5 H3)end if

Mutual Exclusiveness Detection Process

Each node is labeled by two clocks :

• utilization clock

• definition clock

H1

H1

H4

H4H5

H5

H3

H6 H6=H4+H5

H1

H2

H3

H5

H4H6

Clocks

ISSS ’98


process jian(a, b, c, d, e, f, g, x, y)in port a[8], b[8], c[8], d[8], e[8], f[8], g[8];in port x, y;out port u[8], v[8];{static T1;static T2[8], T3[8], T4[8], T5[8]; T1 = (a +1 b) < c; T2 = d +2 e; T3 = c +3 1; if (y) { if (T1) u = T3 +4 d; /*u1 */ else if (!x) u = T2 +5 d; /*u2 */ if (!T1 && x) v = T2 +6 e; } else { T4 = T3 +7 e; T5 = T4 +8 f; u = T5 +9 g; /*u3 */ }}

JIAN Benchmark

ClocksClocks

OperationsOperations

ISSS ’98


process jian(a, b, c, d, e, f, g, x, y)in port a[8], b[8], c[8], d[8], e[8], f[8], g[8];in port x, y;out port u[8], v[8];{

static T1;static T2[8], T3[8], T4[8], T5[8];T1 = (a + 1 b) < c;T2 = d + 2 e;T3 = c +3 1;if (y) {

if (T1) u = T3 + 4 d; /*u1 */else if (!x) u = T2 +5 d; /*u2 */if (!T1 && x) v = T2 + 6 e;

} else {T4 = T3 +7 e; T5 = T4 +8 f;u = T5 +9 g; /*u3 */

}}




} else {T4 = T3 +7 e; T5 = T4 +8 f;u = T5 +9 g; /*u3 */

}}

JIAN Benchmark

ISSS ’98


JIAN Benchmark




} else {T4 = T3 +7 e; T5 = T4 +8 f;u = T5 +9 g; /*u3 */

}}

?aH1

H1

+3H1

H4

?bH1

H1?d

H1

H1?e

H1

H1?c

H1

H11

H1

H1

?fH1

H1

+1H1

H2

+5H10

H10 +6H9

H9

+4H6

H6

?gH1

H1

+9H3

H3

!uH5

H5

+8H3

H3

+7H3

H3

+2H1

H7

!vH9

H9

H1

H2 H3 H4 H5

H6 H7 H8

H9 H10

Clock Boolean Definition Clock Boolean Definition

H1 1 H6 y*T1

H2 y H7 y*!T1

H3 !Y H8 y*T1 + y*!T1*!x

H4 !y+y*T1 H9 y*!T1*x

H5 !y + y*T1 + y*!T1*!x H10 Y*!T1*!x

ISSS ’98


JIAN Benchmark

Start

end

H1

H3

H2

H7

H10H9

H6

H9 H8

H1

N3

N0

N1

N2

N4

N5

N6

C01

C41

C22

C21

C32C31

C42

C51

C12

C11

CCFG?a

H1

H1

+3H1

H4

?bH1

H1?d

H1

H1?e

H1

H1?c

H1

H11

H1

H1

?fH1

H1

+1H1

H2

+5H10

H10 +6H9

H9

+4H6

H6

?gH1

H1

+9H3

H3

!uH5

H5

+8H3

H3

+7H3

H3

+2H1

H7

!vH9

H9

H1

H2 H3 H4 H5

H6 H7 H8

H9 H10

Clock Boolean Definition Clock Boolean Definition

H1 1 H6 y*T1

H2 y H7 y*!T1

H3 !Y H8 y*T1 + y*!T1*!x

H4 !y+y*T1 H9 y*!T1*x

H5 !y + y*T1 + y*!T1*!x H10 Y*!T1*!x

ISSS ’98


{path1=C01,C12;clock=H1*H3 OK}{path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NO}

{path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NOpath5= C01,C11,C22,C42;clock=H1*H2*H6*H8 OKpath6= C01,C11,C22,C31,C42;clock=H1*H2*H7*H9*H8 OKpath7= CO1,C11,C21,C32,C42;clock=H1*H2*H7*H10*H8 OK}

Start

end

H1

H3

H2

H7

H10H9

H6

H9 H8

H1

N3

N0

N1

N2

N4

N5

N6

C01

C41

C22

C21

C32C31

C42

C51

C12

C11

CCFG

JIAN Benchmark

{path1=C01,C11;clock=H1*H2 OK}

{path1=C01;clock=H1 OK}

{path1=C01,C11,C21;clock=H1*H2*H7 OK}

{path1=C01,C11,C22;clock=H1*H2*H6 OK}{path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK}{path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK path3=CO1,C11,C21,C32;clock=H1*H2*H7*H10 OK}

{path1=C01,C12,C51;clock=H1*H3 OK path2= C01,C11,C22,C31,C41 ,C51;clock=H1*H2*H7*H9*H9 OKpath3= C01,C11,C22,C42 ,C51;clock=H1*H2*H6*H8 OKpath4= C01,C11,C22,C31,C42 ,C51;clock=H1*H2*H7*H9*H8 OKpath5= CO1,C11,C21,C32,C42 ,C51;clock=H1*H2*H7*H10*H8 OK}}

Clock Calculation for each PathSTOP

ISSS ’98


C42

CCFG

Start

end

H1

H3

H2

H7

H10H9

H6

H9 H8

H1

N3

N0

N1

N2

N4

N5

N6

C01

C41

C22

C21

C32C31

C42

C51

C12

C11

CCFG

Start

end

H1

H3

H2

H7

H10H9

H6

H9 H8

H1

N3

N0

N1

N2

N4

N5

N6

C01

C41

C22

C21

C32C31

C51

C12

C11

JIAN Benchmark

Results :

ISSS ’98


Benchmark Pathstotal

FeasiblePaths

FalsePaths(%)

JianLi & GuptaEURO-DAC’97

7 5 29

FancyHLS’92

162 31 81

Ex2BergamaschiICCAD91

8 4 50

Seat_beltPolis

12284 15 99.87

hierarchical conditional dependency graphs for false path identification

Documents