heavy flavour identification at linear colliders · joel goldstein slac 9/3/08 flavour physics •...
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Heavy Flavour Identification at
Linear Colliders
Joel GoldsteinUniversity of Bristol
LCFI Collaboration
SLAC AIS 9/3/08
Joel Goldstein SLAC 9/3/08
LCFI
- Sensors
- Readout
- Mechanics
- Software
- Physics
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! Bristol
! Edinburgh
! Glasgow
! Liverpool
! Nijmegen
! Oxford
! RAL
• Linear Collider Flavour Identification
- Has been focusing on ILC
Joel Goldstein SLAC 9/3/08
Flavour Physics
• Precision detectors close to interaction point
• Distinguish tracks from secondary vertices
! Identify, separate b, c quarks and " leptons
! Measure charge3
b decay
c decay
e+
e-
primary
Joel Goldstein SLAC 9/3/08
Flavour Tagging
• b-tagging fairly robust at the ILC
• c-tagging more detector dependent
! Measure Higgs branching ratios
! . . .
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Flavour tagging
ee ! Z ! qq @ 91GeVFull Monte Carlo - LDC01_05ScFull reconstruction
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Joel Goldstein SLAC 9/3/08
Vertex Charge
• Add charge of all tracks in vertex
• Identify charge of flavoured hadron
! Can distinguish quark/antiquark
! Measure hadronic asymmetries
! Anomalous couplings, LEDs....
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b quark
bbar quark
Combined charge b and bbar
Forward – Backward Asymmetry of reconstructed bbar
Reconstructed bbar
Mis-tagged (charge or flavour)
• Sensitive to detector parameters
! Acceptance
! Material
! Geometry...
Joel Goldstein SLAC 9/3/08
ILC Vertex Detector
• 800M 20!20µm2 pixels
• 5 layers, inner radius ~ 1.5 cm
• Gas cooling
! 0.1% X0 per layer in active region
! Uniform material distribution
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Joel Goldstein SLAC 9/3/08
Mechanics
Material target equivalent to 100 !m silicon
! Thinning silicon to 50-100 #m becoming routine
! Thinning to epitaxial possible
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• Ladders with bulkheads
1. Unsupported silicon
- can’t control lateral curl
2. Laterally stiffened silicon
3. Rigid structures
Joel Goldstein SLAC 9/3/08
Thin Substrates
• Longitudinal stiffness from tensioning
• Lateral stiffness from thin substrate
! Beryllium: good specific stiffness but bad CTE
! Carbon fibre good candidate
- 0.09% X0 test model
- laterally stability insufficient
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profile of silicon along the length of a ladder
Joel Goldstein SLAC 9/3/08
Foam Ladders
• 25 micron silicon on 1.5mm 8% SiC
! Very rigid
! Achieved 0.14% X0
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• 20 micron silicon sandwiching 1.5mm 2% carbon
! Could be double-sided
! Achieved 0.07% X0
More exotic rigid structures possible
Joel Goldstein SLAC 9/3/08
RVC Foam
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RVC ladder
silicon spacers
ladder block
glue
glue
silicon block
• Reticulated Vitreous Carbon
! 2-3% relative density
! Not stiff enough for one-sided
Joel Goldstein SLAC 9/3/08
RVC Results
• Shape due to fabrication technique
! New fixtures look promising
! Difficult to control behaviour
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Joel Goldstein SLAC 9/3/08
SiC Foam Ladder
• Processed 8% SiC Foam
! A fraction of initial shape left
! 30% over material budget
! Now have 3-4% foams
• Minimally constrained
! Eliminate stiction in mountings
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Negligible deformation over 70 degrees!
Joel Goldstein SLAC 9/3/08
Foam Future
• SiC seems extremely promising! Lower density now in hand! Learning how to process
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Joel Goldstein SLAC 9/3/08
Foam Future
• SiC seems extremely promising! Lower density now in hand! Learning how to process! All-SiC foam structure...?
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Joel Goldstein SLAC 9/3/08
Foam Future
• SiC seems extremely promising! Lower density now in hand! Learning how to process! All-SiC foam structure...?
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Joel Goldstein SLAC 9/3/08
The ILC Challenge
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337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
The ILC Challenge
! Once per bunch = 300ns per frame : too fast
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337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
The ILC Challenge
! Once per bunch = 300ns per frame : too fast
! Once per train ~200 hits/mm2 : too slow
14
337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
The ILC Challenge
! Once per bunch = 300ns per frame : too fast
! Once per train ~200 hits/mm2 : too slow
! 10 hits/mm2 => 50µs per frame: just right
14
337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
The ILC Challenge
! Once per bunch = 300ns per frame : too fast
! Once per train ~200 hits/mm2 : too slow
! 10 hits/mm2 => 50µs per frame: just right
! 1.6 MPixels in 50µs (commercial ~ 1ms)
14
337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
The ILC Challenge
! Once per bunch = 300ns per frame : too fast
! Once per train ~200 hits/mm2 : too slow
! 10 hits/mm2 => 50µs per frame: just right
! 1.6 MPixels in 50µs (commercial ~ 1ms)
! And gas cooled!
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337 ns
2820x
0.2 s
0.95 ms
ILC bunch structure:
Joel Goldstein SLAC 9/3/08
Sensor R&D
• Column Parallel CCDs
! Focus so far - building on past experience
! Readout during bunch train
• Image Sensor with In-situ Storage
! Increased robustness
! Reduced driver requirements
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Joel Goldstein SLAC 9/3/08
CP CCDs
! Separate readout for each column
! 50 MHz clock rate
! Clock drive is real challenge
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N+1
Column Parallel CCD
Readout time = (N+1)/Fout
Joel Goldstein SLAC 9/3/08
CPC-1
• RAL-designed ASIC
! Bump-bonded on 20µm pitch
! Latest has cluster finding17
Charge Amplifiers(inverting)
Voltage Amplifiers(non-inverting)
Joel Goldstein SLAC 9/3/08
High Speed CPCCDs
• Two metal layers• Distributed clocks! Faster
! More uniform
• Old and new ASICs
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Stripline
Main clock
Extra pads for
Main clock
CPR-1 CPR-2
Temperatur
Charge
Four 1-stage and
2-stage SF in
Four 2-stage SF Standard Field-enhanced Standard
Clock
monitoring and
No
connection
Image area
Joel Goldstein SLAC 9/3/08
CPC-2
• 1, 4, 10 cm long variants
• Custom clock driver ASIC
• Tested up to 45 MHz
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Noise ~ 75e-
Joel Goldstein SLAC 9/3/08
ISIS
• Store charge in CCD register within each pixel
• Orders of magnitude increased resistance to RF
• Much reduced clocking requirements (readout ~1MHz)
• Combination of CCD and CMOS technology on small pitch
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To column load
Source followerReset transistor Row select transistor
p+ shielding implant
n+
buried channel (n)
storage
pixel #1
storage
pixel #20 sense node (n+)
Charge collection
row select
reset gate
VDD
p+ well
reflected charge
reflected charge
photogate
transfer
gate
output
gate
High resistivity epitaxial layer (p)
Joel Goldstein SLAC 9/3/08
ISIS-1
• Proof-of-principle in CCD process
! 16!16 array
! 5 time samples
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Joel Goldstein SLAC 9/3/08
ISIS-1 Tests
• Tested with 55Fe and 6 GeV e-
• X-rays and MIPS clearly seen
• Position resolution ~ 12µm
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Joel Goldstein SLAC 9/3/08
ISIS-1 at CERN
• Testing in CERN 120 GeV pion beam
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Joel Goldstein SLAC 9/3/08
ISIS-2
• Custom CMOS process
• 800µm2 pixels
• 20 time samples
! Close to targets
! Wafers being diced
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ISIS2 – Top Level
2Konstantin Stefanov, STFC Rutherford Appleton Laboratory
Joel Goldstein SLAC 9/3/08
Summary
• Complete ILC vertex detector package
• Good progress in
! Software and physics studies
! Mechanics
! Sensors
• Applicability beyond ILC
! Continue much as generic R&D
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