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(c) 2015 FEDEVEL & VOIPAC

V1I0

[04] - VIDEO INPUT.SchDoc

iMX6 Tiny Rex Baseboard Lite

4 18

PrototypeVariant:

Checked by

HDMI Video Input

6/5/2015 Designed by www.fedevel.com

HDMI_IN_D2_N5HDMI_IN_D2_P5

HDMI_IN_D1_N5HDMI_IN_D1_P5

HDMI_IN_D0_N5HDMI_IN_D0_P5

HDMI_IN_CLK_N5HDMI_IN_CLK_P5

Y1

28.63636MHz

HDMI_IN_XTALN

HDMI_IN_XTALP

C183220pF

C184220pF

C187100n

C188100n

C177100n

C55100n

C45220pF

C46220pF

C42100n

C43100n

C44100n

C41100n

C190100n

C47220pF

C50220pF

C52100n

C53100n

C54100n

1 2FB5

BLM15AX601SN1D

+1V8

+1V8_DVDD1 2

FB3

BLM15AX601SN1D

+1V8max 190mA

max 120mA

1 2FB11

BLM15AX601SN1D

+1V8_PVDD

1 2FB8

BLM15AX601SN1D

+3V3+3V3_TVDD

1 2FB4

BLM15AX601SN1D

+3V3+3V3_DVDDIO

I2C2_DDC_SCL5I2C2_DDC_SDA5

+5VR1040RNF

DESIGN NOTE:RXA_5V is used to detect if cableis connected.

HDMI_IN_RXA_5V

VID_IN_CSI0_INT_R

HDMI_IN_HPD 5

I2C3_SCL13, 3I2C3_SDA13, 3

R1050R HDMI_IN_CECHDMI_IN_CEC_IN5

+1V8

C561u

C574u7

C592700pF

NF

SS_+1V8 FB_+1V8

TP4TP_25MILC

R832k4

R823k

C5810u

IN_11

IN_22

PG3

BIAS4

EN5

GND

6

SS7

FB8

OUT_19

OUT_210

EPAD_1

11

EPAD_2

12

EPAD_3

13

EPAD_4

14

EPAD_5

15

U2

TPS74801DRCR

POK_3V314, 3

POK_1V8 7

R8110k

+3V3

+1V8

R6633RVID_IN_CSI0_PIXCLK_R

max 40mA

max 60mA

max 180mA

+1V8

+1V8_CVDD

R1650RHDMI_HPA_A

DESIGN NOTE:VID_IN_CSI0_INT is open drain bydefault.

DESIGN NOTE:(DDCA_SDA / DDCA_SCL):E-EDID I2C Address 0xA0HDCP I2C Address 0x74

C51220pF

HPA_A / INT2A1

RXA_5VA2

DDCA_SCLA3

PVDDA4

XTALNA5

XTALPA6

INT1A7

MCLK / INT2A8

SCLK / INT2A9

DVDD_1A10

TVDD_1B1

TVDD_2B2

DDCA_SDAB3

CECB4

CSB5

RESETB6

SDAB7

SCLB8

LRCLKB9

DVDD_2B10

RXA_C+C1

RXA_C–C2

I2S3C9

I2S1C10

RXA_0+D1

RXA_0–D2

I2S2D9

I2S0D10

GND_1D4

GND_2D5

GND_3D6

DVDD_3D7

RXA_1+E1

RXA_1–E2

GND_4E4

DVDD_4E7

VS / FIELD / ALSBE9

DEE10

RXA_2+F1

RXA_2–F2

GND_5F4

DVDDIO_1F7

HSF9

P0F10

CVDD_1G1

CVDD_2G2

GND_6G4

GND_7G5

GND_8G6

DVDDIO_2G7

P1G9

P2G10

P23H1

P22H2

P3H9

P4H10

P21J1

P18J2

P16J3

P15J4

P13J5

P11J6

P9J7

P7J8

P5J9

DVDDIO_3J10

P20K1

P19K2

P17K3

LLCK4

P14K5

P12K6

P10K7

P8K8

P6K9

DVDDIO_4K10

U1

ADV7610BBCZ-PC4815pF

C4915pF

R72

390k

DESIGN NOTE:In case of crystal problems,increase value of R72.

C18510u

DESIGN NOTE:+1.8V / max 1.5A(Required 400mA)

R1740R+5V_HDMI_IN_CON

R1090R

VID_IN_CSI0_RSTn

i

Net Class

ClassName: VID_IN_CSI0

DESIGN NOTE: HPA_A/INT2 open drain - pull up is required.

+VIN

+VIN

TP6 TP_25MILC

DESIGN NOTE:iMX6 IPU Sensor Interface Signal Mapping

DESIGN NOTE:ADV7610 SDR Output Modes

VID_IN_CSI0_D2

VID_IN_CSI0_VS

VID_IN_CSI0_HS

VID_IN_CSI0_PIXCLK

VID_IN_CSI0_D3

VID_IN_CSI0_D4

VID_IN_CSI0_D5

VID_IN_CSI0_D6

VID_IN_CSI0_D7

VID_IN_CSI0_D8

VID_IN_CSI0_D9

VID_IN_CSI0_D10

VID_IN_CSI0_D11

VID_IN_CSI0_D12

VID_IN_CSI0_D13

VID_IN_CSI0_D14

VID_IN_CSI0_D15

VID_IN_CSI0_D16

VID_IN_CSI0_D17

VID_IN_CSI0_D18

VID_IN_CSI0_D19

VID_IN_CSI0_D0

VID_IN_CSI0_D1

i

Net ClassClassName: VID_IN_CSI0

R410k

i

Net Class

ClassName: VID_IN_CSI0

R310k

R210k

R110k

TP5 TP_25MILC

TP3 TP_25MILCTP2 TP_25MILC

POKn 11, 15, 7R50RNF

DESIGN NOTE:If 1V5 power is not used fit R5and do not fit R81.

R90RR80R

R64k99NF

R74k99NF

+3V3 +3V3

I2C2_SCL10, 13, 3, 7I2C2_SDA10, 13, 3, 7

DESIGN NOTE:To separate HDMI Input from I2Cbus unfit zero ohm resistors R8 &R9 and fit pullup resistors R6 & R7.

DESIGN NOTE:CPU Audio Interface needs to be setup as a slave.AUD4_TXC 3

AUD4_TXFS 3

AUD4_RXD 3

AUD4_CLK 3R16722R NFAUD4_CLK_R

R16622R NFAUD4_TXC_R

i

Net Class

ClassName: AUD4

R16822R NFR16922R NF

AUD4_TXFS_R

AUD4_RXD_R

VID_IN_CSI0_HS 3VID_IN_CSI0_VS 3

VID_IN_CSI0_D12 3VID_IN_CSI0_D13 3VID_IN_CSI0_D14 3VID_IN_CSI0_D15 3VID_IN_CSI0_D16 3VID_IN_CSI0_D17 3VID_IN_CSI0_D18 3VID_IN_CSI0_D19 3

VID_IN_CSI0_INT 3

VID_IN_CSI0_DE 3

VID_IN_CSI0_D2 3VID_IN_CSI0_D3 3VID_IN_CSI0_D4 3VID_IN_CSI0_D5 3VID_IN_CSI0_D6 3VID_IN_CSI0_D7 3VID_IN_CSI0_D8 3VID_IN_CSI0_D9 3

VID_IN_CSI0_D10 3VID_IN_CSI0_D11 3

VID_IN_CSI0_RSTn 3

VID_IN_CSI0_PIXCLK 3

VID_IN_CSI0_D0 3VID_IN_CSI0_D1 3

VID_IN_CSI0_INT

VID_IN_CSI0_DE

I2C ADDRESS = 0x98/0x9A

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[6]

Y[5]

Y[7]

DESIGN NOTE:SS sets the regulator output soft-start ramp time:- C59 not fitted: 200us (from datasheet table page 4)- C59 fitted: 5ms

DESIGN NOTE:Signal VID_IN_CSI010 & 11 was used as default serialconsole output. If problem occurs with new consoleconfiguration use testpoints for debugging.

DESIGN NOTE:Pulldown resistors placed on VID_IN_CSI0_D0,1,10,11to support YCbCr 16 bit mode. Test. The resistors maynot be required.

DESIGN NOTE:Vadj = 0,8VVout = Vadj * (1+ R1/R2) =0,8*(1+3k/2,4k)=0,8*2,25=1,8V

DESIGN NOTE:There are double 22R resistors on signalsAUD4_CLK & AUD4_TXC. If needed replace one ofthem by zero Ohm resistor (on the module).

DESIGN NOTE:(SDA/SCL pins B7/B8):The I2C Address of the main mapis 0x98 after reset.

FREE for personal and commercial use.