hdl laboratory

QMP 7.1 D/F

Channabasaveshwara Institute of Technology (Affiliated to VTU, Belgaum & Approved by AICTE, New Delhi)

(NAAC Accredited & ISO 9001:2015 Certified Institution) NH 206 (B.H. Road), Gubbi, Tumkur – 572 216. Karnataka.

Department of Electronics & Communication

Engineering

HDL LABORATORY

17ECL58

(CBCS SCHEME)

B.E - V Semester

Lab Manual 2019-20

Name: ____________________________________

USN: ____________________________________

Batch: ________________ Section: ____________

. QMP 7.1 D/F

Channabasaveshwara Institute of Technology (Affiliated to VTU, Belgaum & Approved by AICTE, New Delhi) (NAAC Accredited & ISO 9001:2015 Certified Institution)

NH 206 (B.H. Road), Gubbi, Tumkur – 572 216. Karnataka.

Department of Electronics & Communication

Engineering

HDL LAB Manual

Prepared by: Reviewed by:

Mr. Sanjeevakumar Harihar Mr. Sanjeevakumar Harihar

Mr. Harsha G

Approved by:

Dr. Rajagopala R

Professor & Head,

Dept. of ECE

.


(NAAC Accredited &ISO 9001:2015 Certified Institution)

NH 206 (B.H. Road), Gubbi, Tumkur – 572 216.Karnataka.

Department of Electronics and Communication Engineering

Vision

To create globally competent Electronics and Communication Engineering

professionals with ethical and moral values for the betterment of the society

Mission

To impart quality technical education in the field of electronics and

communication engineering to meet over the current/future global

industry requirements.

To create the centres of excellence in the field of electronics and

communication in collaboration with industry and universities

To nurture the technical/professional/engineering and entrepreneurial

skills for overall self and societal upliftment.

To orient the student community towards the higher education, research

and development activities.

To provide a platform for equipping the students with necessary skills

through co-curricular and extra-curricular events.

To have Industrial collaboration for strengthening the Teaching-Learning

Process/Academics

To associate with industries for training the faculty on the latest

technologies through continuous education programmes.





B.E: Electronics & Communication Engineering

Program Outcomes (POs)

At the end of the B.E program, students are expected to have developed the following

outcomes.

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialisation to the solution of complex engineering

problems.

2. Problem analysis: Identify, formulate, research literature, and analyse complex

engineering problems reaching substantiated conclusions using first principles of

mathematics, natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with appropriate

consideration for the public health and safety, and the cultural, societal, and environmental

considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data, and

synthesis of the information to provide valid conclusions.

5. Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and

modern engineering and IT tools including prediction and modelling to complex engineering

activities with an understanding of the limitations.

6. The Engineer and Society: Apply reasoning informed by the contextual knowledge to

assess societal, health, safety, legal and cultural issues and the consequent responsibilities

relevant to the professional engineering practice.

7. Environment and Sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of need for

sustainable development.





8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and

norms of the engineering practice.

9. Individual and Team Work: Function effectively as an individual, and as a member or

leader in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and

write effective reports and design documentation, make effective presentations, and give and

receive clear instructions.

11. Project Management and Finance: Demonstrate knowledge and understanding of the

engineering and management principles and apply these to one’s own work, as a member and

leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognise the need for, and have the preparation and ability to

engage in independent and life-long learning in the broadest context of technological change





Program Educational Objectives (PEO’s)

After four Years of Graduation, our graduates are able to:

• Provide technical solutions to real world problems in the areas of electronics and

communication by developing suitable systems.

• Pursue engineering career in Industry and/or pursue higher education and research.

• Acquire and follow best professional and ethical practices in Industry and Society.

• Communicate effectively and have the ability to work in team and to lead the team.

Program Specific Outcomes (PSOs)

At the end of the B.E Electronics & Communication Engineering program, students are

expected to have developed the following program specific outcomes.

PSO1: Specify, design, build and test analog and digital systems for signal processing

including multimedia applications, using suitable components or simulation tools.

PSO2: Understand and architect wired and wireless analog and digital communication

systems as per specifications and determine their performance.

SYLLABUS

HDL LABORATORY

[As per Choice Based Credit System (CBCS) scheme] SEMESTER – V (EC/TC)

Subject Code: 17ECL58 IA Marks: 40

Hrs/ Week : 03 (01Hr Tutorial (Instructions) + 02 Hours Laboratory)

Exam Hours: 03 Exam Marks: 60

Part–A (Using Xilinx Tool)

1. Write Verilog code to realize all the logic gates

2. Write a Verilog program for the following combinational designs

a. 2 to 4 decoder b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer.

d. 4 bit binary to gray converter

e. Multiplexer, de-multiplexer, comparator. 3. Write a Verilog code to describe the functions of a Full Adder using

three modeling styles.

4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below

• ALU should use combinational logic to calculate an output based on

the four bit op-code input.

• ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low.

• ALU should decode the 4 bit op-code according to the example given

below. OPCODE ALU Operation

1 A+B

2 A-B

3 A Complement

4 A*B

5 A AND B

6 A OR B

7 A NAND B

8 A XOR B

5. Develop the Verilog code for the following flip-flops, SR, D, JK and T. 6. Design a 4 bit binary, BCD counters (Synchronous reset and

Asynchronous reset) and “any sequence” counters, using Verilog code.

Part – B

INTERFACING (at least four of the following must be covered using VHDL/Verilog

1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven

segment display.

3. Write HDL code to control speed, direction of DC and Stepper motor.

4. Write HDL code to accept Analog signal, Temperature sensor and display the

data on LCD or Seven segment displays.

5. Write HDL code to generate different waveforms (Sine, Square, Triangle,

Ramp etc.,) using DAC - change the frequency.

6. Write HDL code to simulate Elevator operation.

QMP 7.1 D/F


(NAAC Accredited & ISO 9001:2015 Certified Institution)


Objectives and outcomes of HDL Laboratory

Objectives: This course will enable students to:

Familiarize with the CAD tool to write HDL programs.

Understand simulation and synthesis of digital design.

Program FPGAs to synthesize the digital designs.

Interface hardware to programmable ICs through I/O ports.

Choose either Verilog or VHDL for a given Abstraction level.

Outcomes: On the completion of this laboratory course, the students will be able to:

Write efficient hardware design in Verilog/VHDL programs to simulate

Combinational circuits in Dataflow, Behavioral and Gate level Abstractions.

Describe sequential circuits like flip flops and counters in Behavioral description

and obtain simulation waveforms.

Develop and Implement Combinational and Sequential circuits on FPGA and test

the hardware.

Interface the FPGA with different external devices such as motors, relays, DAC,

Seven Segment and LCD displays.

QMP 7.1 D/F


(NAAC Accredited & ISO 9001:2015 Certified Institution)


DEPARTMENT OF ELECTRONICS AND COMMUNICATION

TABLE OF CONTENTS

Sl.N0. Experiment Names Page No

Part-A

1 Verilog code to realize all the logic gates 1-2

2 Verilog program for the following combinational designs

a. 2 to 4 decoder b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer.

d. 4 bit binary to gray converter e. De-Multiplexer and comparator.

3-16

3 Verilog code to describe the functions of a Full Adder using three

modeling styles.

17-20

4 Verilog code to model 32 bit ALU 21-24

5 Verilog code for the following flip-flops, SR, D, JK and T. 25-32

6 Verilog code for 4 bit binary, BCD counters (Synchronous reset and

Asynchronous reset) and “any sequence” counters.

33-42

PART-B (Interfacing Programs)

1 VHDL code to display messages on an alpha numeric LCD display. 43-46

2 Verilog code to display messages on an seven segment display. 47-50

3 Verilog code to control speed, direction of DC and Stepper motor. 51-56

4 Verilog code to accept 8 channel Analog signals, Temperature sensor

and display the data on LCD panel or Seven segment display.

57-64

5 Verilog code to generate different waveforms (Sine, Square, Triangle,

Ramp etc.,) using DAC - change the Frequency and Amplitude.

65-74

6 Verilog code to simulate Elevator operation. 75-80

EXTRA PROGRAMS

VHDL C ode for 4-bit Braun Multiplier

VHDL Code to control external light using relays. Verilog code realizes 4-bit Ripple Carry Adder.

81-84

Sample Viva Questions.

Question Bank

INDEX PAGE

Sl.

No

Name of the Experiment

Date

Ma

nu

al

Ma

rks

(Ma

x .

15

)

Rec

ord

M

ark

s

(Ma

x.

10

)

Sig

na

ture

(Stu

den

t)

Sig

na

ture

(Fa

cult

y)

Conduction Repetition Submission

of Record

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

Average

General Instructions to Students

1. Students should come with thorough preparation for the experiment to be

conducted.

2. Students should take prior permission from the concerned faculty before availing

the leave.

3. Students should come with formals and to be present on time in the laboratory.

4. Students will not be permitted to attend the laboratory unless they bring the

practical record fully completed in all respects pertaining to the experiments

conducted in the previous session.

5. Students will be permitted to attend the laboratory unless they bring the

observation book fully completed in all respects pertaining to the experiments

conducted in the present session.

6. They should obtain the signature of the staff-in –charge in the observation book

after completing each experiment.

7. Practical record should be neatly maintained.

8. Ask lab Instructor for assistance for any problem.

9. Do not download or install software without the assistance of laboratory

Instructor.

10. Do not alter the configuration of system.

11. Turn off the systems after use.

PART – A

EXPERIMENTS

HDL Lab (17ECL58) 2019-20

Dept. of ECE, CIT, Gubbi Page 1

RTL Schematic:

Truth Table:

UCF /Implementation Constraint File details:

HDL Lab (17ECL58) 2019-20


Experiment No 1: Date: __/__/____

Verilog Code to Realize all logic gates

module gates(input a_in,b_in,

output not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);

assign not_op=~a_in;

assign and_op=(a_in&b_in);

assign nand_op=~(a_in&b_in);

assign or_op=(a_in|b_in);

assign nor_op=~(a_in|b_in);

assign xor_op=(a_in^b_in);

assign xnor_op=~(a_in^b_in);

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2a: Date: __/__/____

Verilog Code to Realize 2:4 Decoder module decoder2_4 (d_in,en,d_op);

input [1:0] d_in;

input en;

output [3:0] d_op;

reg [3:0] d_op;

always @(d_in,en)

begin

if (en==1)

d_op=4'bzzzz;

else

case (d_in)

2'b00:d_op = 4'b0001;

2'b01:d_op = 4'b0010;

2'b10:d_op = 4'b0100;

2'b11:d_op = 4'b1000;

default:d_op=4'bxxxx;

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2b(i): Date: __/__/____

Verilog to Realize 8:3 Encoder without priority

module encoder8_3(en, a_in, y_op);

input en;

input [7:0] a_in;

output [2:0] y_op;

reg [2:0] y_op;

always @ (a_in,en)

begin

if(en==1 )

y_op =3’bzzz;

else

case (a_in)

8'b00000001: y_op = 3'b000;

8'b00000010: y_op = 3'b001;

8'b00000100: y_op = 3'b010;

8'b00001000: y_op = 3'b011;

8'b00010000: y_op = 3'b100;

8'b00100000: y_op = 3'b101;

8'b01000000: y_op = 3'b110;

8'b10000000: y_op = 3'b111;

default: y_op =3'bxxx;

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2b(ii): Date: __/__/____

Verilog Code to Realize 8:3 Encoder with priority

module encoder8_3(en, a_in, y_op);

input en;

input [7:0] a_in;

output [2:0] y_op;

reg [2:0] y_op;

always @ (a_in,en)

begin

if(en==1 )

y_op=3’bzzz;

else

case (a_in)

8'b00000001: y_op = 3'b000;

8'b0000001x: y_op= 3'b001;

8'b000001xx: y_op= 3'b010;

8'b00001xxx: y_op= 3'b011;

8'b0001xxxx: y_op= 3'b100;

8'b001xxxxx: y_op= 3'b101;

8'b01xxxxxx: y_op= 3'b110;

8'b1xxxxxxx: y_op= 3'b111;

default: y_op=3'bxxx;

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2c: Date: __/__/____

Verilog Code to Realize 8:1 Multiplexer

module mux8_1(i_in, sel, y_out);

input [7:0] i_in;

input [2:0] sel;

output y_out;

reg y_out;

always@ (i_in,sel )

begin

case (sel)

3'b000: y_out=i_in[0];

3'b001: y_out=i_in[1];

3'b010: y_out=i_in[2];

3'b011: y_out=i_in[3];

3'b100: y_out=i_in[4];

3'b101: y_out=i_in[5];

3'b110: y_out=i_in[6];

3'b111: y_out=i_in[7];

default: y_out =3'b000;

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2d: Date: __/__/____

Verilog Code to realize 4 bit Binary to Gray Convertor

module b2g(b_in, g_op);

input [3:0] b_in;

output [3:0] g_op;

assign g_op[3] = b_in[3];

assign g_op[2] = b_in[3] ^ b_in[2];



endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2e: Date: __/__/____

Verilog Code to realize 1:4 DEMUX

module demux1_4(a_in, sel, y_out);

input a_in;

input [1:0]sel;

output [3:0]y_out;

reg [3:0]y_out;

always @(a_in, sel)

begin

case (sel)

2'b00:begin y_out[0]=a_in;y_out[1]=1'b0;

y_out[2]=1'b0;y_out[3]=1'b0;end

2'b01:begin y_out[0]=1'b0;y_out[1]=a_in;

y_out[2]=1'b0;y_out[3]=1'b0;end

2'b10:begin y_out[0]=1'b0;y_out[1]=1'b0;

y_out[2]=a_in;y_out[3]=1'b0;end

2'b11:begin y_out[0]=1'b0;y_out[1]=1'b0;

y_out[2]=1'b0;y_out[3]=a_in;end

default: y_out=3'b000;

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 2f: Date: __/__/____ Verilog Code to realize 4-bit Comparator

module comparator(a_in, b_in, L_op,g_op,e_op);

input [3:0] a_in; input [3:0] b_in;

output L_op; output g_op;

output e_op; reg L_op,g_op,e_op;

always @ (a_in,b_in) begin if (a_in<b_in)

L_op=1'b1; else

L_op=1'b0; if (a_in>b_in)

g_op=1'b1; else

g_op=1'b0; if (a_in==b_in)

e_op=1'b1; else

e_op=1'b0; end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:(i) Dataflow Style

Expression:

sum = a_in b_in c_in;

carry= (a_in.b_in)+(b_in.c_in)+(a_in.b_in);

RTL Schematic(ii) Behavioral Style

Truth Table:

HDL Lab (17ECL58) 2019-20


Experiment No 3 : Date: __/__/____

Verilog Code to Describe Full Adder using Dataflow Style

module fulladder(a_in, b_in, c_in, sum, carry);

input a_in, b_in,c_in;

output sum, carry;

assign sum = a_in^b_in^c_in;

assign carry =(a_in & b_in)|(b_in & c_in)|(a_in & c_in);

endmodule

Verilog Code to Describe Full Adder using Behavioral Style

module fulladder(abc, sum, carry);

input [2:0] abc;

output sum,carry;

reg sum,carry;

always@(abc)

begin

case (abc)

3’b000:begin sum=1’b0; carry=1’b0;end








default: begin sum=1'bz;carry=1'bz;end

endcase

end

endmodule

HDL Lab (17ECL58) 2019-20


Gate level logic:

RTL Schematic: (iii) Gate Level Style


HDL Lab (17ECL58) 2019-20


Verilog Code to Describe Full Adder using Gate level Style

module fulladder(a_in, b_in, c_in, sum, carry);

input a_in,b_in, c_in;

output sum,carry;

wire s1, s2, s3;

xor x1(s1,a_in,b_in);

and a1(s2,a_in,b_in);

xor x2(sum,s1,c_in);

and a2(s3,s1,c_in);

or o1(carry,s3,s2);

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Opcode Table:

OPCODE ALU OPERATION

1 A + B

2 A – B

3 A Complement

4 A*B

5 A AND B

6 A OR B

7 A NAND B

8 A XOR B

HDL Lab (17ECL58) 2019-20



Verilog Code to realize 32-bit ALU

module alu(a, b, sel,en,y,y_mul);

input [31:0] a;

input [31:0] b;

input en;

input [3:0] sel;

output [31:0] y;

output[63:0]y_mul;

reg [31:0] y;

reg [63:0]y_mul;

always @(a, b , sel)

begin

if (en==1)

case (sel)

4'b0001:y=a+b;

4'b0010:y=a-b;

4'b0011:y=~a;

4'b0100:y_mul=a*b;

4'b0101: y=a&b;

4'b0110: y=a|b;

4'b0111: y=~(a&b);

4'b1000:y=a^b;

endcase

end

endmodule

HDL Lab (17ECL58) 2019-20



HDL Lab (17ECL58) 2019-20


Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:

UCF /Implementation Constraint File details

HDL Lab (17ECL58) 2019-20



Verilog Code to Describe SR Flipflop

module sr_ff(sr, clk, rst, q, qb);

input [1:0]sr;

input rst, clk;

output q,qb;

reg q,qb;

always @ (posedge clk)

begin

if (rst==1)

begin

q=0;

qb=1;

end

else

case (sr)

2'b00: begin q=q; qb=qb; end

2'b01: begin q=0; qb=1; end

2'b10: begin q=1; qb=0; end

2'b11: begin q=1'bx; qb=1'bx; end

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic

Truth Table:


HDL Lab (17ECL58) 2019-20


Experiment No 5b: Date: __/__/____

Verilog Code to Describe D Flipflop

module d_ff(d, rst, clk, q, qb);

input d;

input rst;

input clk;

output q;

output qb;

reg q,qb;

always@(posedge clk)

begin

if (rst==1)

begin

q=0;

qb=1;

end

else

begin

q=d;

qb=~d;

end

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20



Verilog Code to Describe JK Flipflop

module jk_ff(jk, clk, rst, q, qb); input [1:0]jk;

input clk,rst; output q, qb;

reg q, qb; reg [22:0] div;

reg clkdiv; always @ (posedge clk) begin

div= div+1'b1; clkdiv = div[22];

end always @ (posedge clkdiv)

begin if(rst==1)

begin q=1’b0; qb=1’b1;

end else

case (jk) 2'b00: begin q=q; qb=qb; end

2'b01: begin q=1’b0; qb=1’b1; end 2'b10: begin q=1’b1; qb=1’b0; end

2'b11: begin q=~(q); qb=~(qb); end endcase

end endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth Table:


HDL Lab (17ECL58) 2019-20



Verilog Code to Describe T Flipflop

module t_ff(t, clk, rst, q, qb);

input t, clk, rst; output q, qb;

reg q,qb; reg [22:0] div;

reg clkdiv;

always @ (posedge clk) begin

div = div+1'b1; clkdiv = div[22]; end

always @ (posedge clkdiv) begin

if (rst==1) begin

q=1’b0; qb=1’b1;

end else

case (t) 1’b0:begin q=q; qb=qb; end

1’b1:begin q=~(q); qb=~(qb); end endcase

end endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth table:

Clk Rst bin_out(3) bin_out(2) bin_out(1) bin_out(0)

1 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1


HDL Lab (17ECL58) 2019-20



Verilog Code to design 4 –bit Binary Synchronous reset counter

module bin_sync( clk, rst, bin_out);

input clk, rst;

output [3:0] bin_out;

reg [3:0] bin_out;

reg [22:0] div; reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv)

begin

if (rst)

bin_out=4’b0000;

else

bin_out=bin_out+4’b0001;

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth table:


X 1/ 0 0 0 0

X 0 0 0 0 1

X 0 0 0 1 0

X 0 0 0 1 1

X 0 0 1 0 0

X 0 0 1 0 1

X 0 0 1 1 0

X 0 0 1 1 1

X 0 1 0 0 0

X 0 1 0 0 1

X 0 1 0 1 0

X 0 1 0 1 1

X 0 1 1 0 0

X 0 1 1 0 1

X 0 1 1 1 0

X 0 1 1 1 1


HDL Lab (17ECL58) 2019-20



Verilog Code to design 4 –bit Binary Asynchronous reset counter

module bin_asyn( clk, rst, bin_out);

input clk, rst;

output [3:0] bin_out;

reg [3:0] bin_out;

reg [22:0] div;

reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv or posedge rst)

begin

if (rst)

bin_out=4'b0000;

else

bin_out=bin_out+4'b0001;

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth table:


1 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0


HDL Lab (17ECL58) 2019-20



Verilog Code to design 4 –bit BCD Synchronous reset counter

module bcd_syn( clk, rst, bcd_out);

input clk, rst;

output [3:0] bcd_out;

reg [3:0] bcd_out;

reg [22:0] div;

reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end


begin

if (rst)

bcd_out=4’d0;

else if(bcd_out<4’d9)

bcd_out=bcd_out+4’d1;

else

bcd_out=4’d0;

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic:

Truth table:


X 1/ 0 0 0 0

X 0 0 0 0 1

X 0 0 0 1 0

X 0 0 0 1 1

X 0 0 1 0 0

X 0 0 1 0 1

X 0 0 1 1 0

X 0 0 1 1 1

X 0 1 0 0 0

X 0 1 0 0 1

X 0 0 0 0 0

X 0 0 0 0 1

X 0 0 0 1 0


HDL Lab (17ECL58) 2019-20



Verilog Code to design 4 –bit BCD Asynchronous reset counter

module bcd_asyn( clk, rst, bcd_out); input clk, rst;

output [3:0] bcd_out; reg [3:0] bcd_out;

reg [22:0] div; reg clkdiv;

always @ (posedge clk) begin

div = div+1'b1; clkdiv = div[22];

end always @ (posedge clkdiv or posedge rst)

begin if (rst)

bcd_out=4'd0; else if(bcd_out<4'd9)

bcd_out=bcd_out+4'd1; else

bcd_out=4'd0; end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


RTL Schematic

State Diagram: S


HDL Lab (17ECL58) 2019-20


Experiment No 6e: Date: __/__/____ Verilog Code to design Any Sequence Counter

Sequence: 0 5 6 4

module any_seq( clk, s_out);

input clk;

output [2:0] s_out ;

reg [3:0] s_out;

reg [22:0] div;

reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end

initial

s_out=3'b0000;


begin

case(s_out)

3'b000:s_out=3'b101;

3'b101:s_out=3'b110;

3'b110:s_out=3'b100;

3'b100:s_out=3'b000;

default: begin end

endcase

end

endmodule

Simulation Result:

HDL Lab (17ECL58) 2019-20


Procedure: 1. Make the connection between FRC5 of the FPGA board and the LCD

display connector of the GPIOcard-1.

2. Assign appropriate pins to input and output.

4. Connect USB cable and power supply to the FPGA board.

4. Press the hex keys and analyze the data.

Pin no Name Function Description

1 Vss Power supply Ground

2 Vdd Power supply +5v

3 Vo Contrast adjust 0-5v

4 RS Command Register select

5 RW Command Read /Write

6 E Command Enable

7 D0 Input/Output Data(LSB)

8 D1 Input/Output Data






14 D7 Input/Output Data(MSB)

15 A LED BKL +5v

16 K LED BKL Ground

HDL Lab (17ECL58) 2019-20



VHDL Code to display messages on an alpha numeric LCD display.

entity lcd is port ( clk : in std_logic;

lcd_rw: out std_logic; lcd_e : out std_logic;

lcd_rs: out std_logic; data : out std_logic_vector(7 downto 0));

end lcd;

architecture behavioral of lcd is constant N: integer :=22;

type arr is array (1 to N) of std_logic_vector(7 downto 0); constant datas :

arr :=(X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"

43",x"48",x"20",x"53",x"4f",x"4c",x"55",x"54",x"49",x"4f",x"4e",X"53"); --command and data to display begin

lcd_rw<= '0'; process(clk)

variable i : integer := 0; variable j : integer := 1;

begin if clk'event and clk = '1' then

if i<= 1000000 then i:= i + 1;

lcd_e<= '1'; data<= datas(j)(7 downto 0);

elsif i> 1000000 and i< 2000000 then i := i + 1;

lcd_e<= '0'; elsif i = 2000000 then

j := j + 1; i := 0;

end if; if j <= 5 then lcd_rs<= '0'; --command signal

elsif j > 5 then

HDL Lab (17ECL58) 2019-20



HDL Lab (17ECL58) 2019-20


lcd_rs<= '1'; --data signal end if;

if j = 22 then --repeated display of data j := 5; end if;

end if; end process;

end Behavioral;

HDL Lab (17ECL58) 2019-20


Procedure: 1. Make the connection between FRC5 of the FPGA board and the seven-

segment connector of the GPIOcard-1.

2. Make the connection between FRC4 of the FPGA board and the keyboard

connector of the GPIOcard-1.

3. Assign appropriate pins to input and output .

4. Connect JTAG cable and power supply to the FPGA board.


HDL Lab (17ECL58) 2019-20



Verilog Code to display a character on the given seven segment display accepting HEX keypad input

module key(col,row,clk,disp_sel,ss); output [3:0] col=4'b0001;

input [3:0] row; input clk;

output [3:0] disp_sel; output [6:0] ss; reg [3:0]col;

reg[6:0] ss; reg[3:0] disp_sel;

always @( posedge clk)

begin col={col[2:0],col[3]};

disp_sel= 4'b1110; end

always @*

begin case (col)

4'b0001:case (row) 4'b0001:ss= 7'b1111110;

4'b0010:ss= 7'b0110011; 4'b0100:ss= 7'b1111111;

4'b1000:ss= 7'b1001110; default:ss= 7'b0000000; endcase

4'b0010: case (row)

4'b0001:ss = 7'b0110000;

4'b0010:ss = 7'b1011011;

4'b0100:ss = 7'b1111011;

4'b1000:ss = 7'b0111101;

default:ss = 7'b0000000;

endcase

HDL Lab (17ECL58) 2019-20



HDL Lab (17ECL58) 2019-20


4'b0100: case (row)

4'b0001:ss = 7'b1101101;

4'b0010:ss = 7'b1011111;

4'b0100:ss = 7'b1110111;

4'b1000:ss = 7'b1001111;


endcase

4'b1000: case (row)

4'b0001:ss = 7'b1111001;

4'b0010:ss = 7'b1110000;

4'b0100:ss = 7'b0011111;

4'b1000:ss = 7'b1000111;


endcase

default:ss=7'b0000000;

endcase

end

endmodule

HDL Lab (17ECL58) 2019-20


Hardware Details:

1. When rly=o, pwm(o)=1,pwm(1)=1

2. When rly=1, pwm(o)=1,pwm(1)=1

HDL Lab (17ECL58) 2019-20



Verilog Code to control speed and direction of DC Motor

module dc_mot(clk,reset, pwm, rly, keys);

input clk,reset;

output [1:0] pwm;

output rly;

input [3:0] keys;

reg [1:0] pwm;

reg [16:0] div;

reg tick;

reg [7:0] counter= 0;

reg [7:0] duty_cycle;


begin

div = div +1'b1;

tick= keys[3]& keys[2] & keys[1]& keys[0];

end

always @ (negedge tick)

begin

case(keys)

4'b1110: begin duty_cycle = 255;end




default: begin duty_cycle = 64;end

endcase

end

always @ (posedge div[12])

begin

if (reset==1'b1)

begin

counter = 8'b00000000;

pwm = 2'b01;

HDL Lab (17ECL58) 2019-20


3. When rly=0,pwm(o)=1,pwm(1)=0

4. When rly=1,pwm(o)=1,pwm(1)=0

Procedure:

1. Make the connection between FRC9 of the FPGA board and stepper

motor connector of interfacing card.

2. Make the connection between FRC1 of the FPGA board and DIP switch




HDL Lab (17ECL58) 2019-20


end

else

begin

counter = counter +1'b1;

if (counter <= duty_cycle)

pwm[1] = 1'b1;

else

pwm[1] = 1'b0;

end

end

assign rly = 1'b1;

endmodule


HDL Lab (17ECL58) 2019-20


Hardware Details:

Procedure:

1. Make the connection between FRC9 of the FPGA board and stepper

motor connector of interfacing card






HDL Lab (17ECL58) 2019-20



Verilog Code to control direction of Stepper Motor

module step_mot(clk,reset,dir, stepout);

input clk,reset,dir; output [3:0] stepout;

reg [25:0] div; reg [3:0] shift_reg;


begin div = div + 1'b1;

end

always @ (posedge div[15]) begin

if (reset==1'b1) shift_reg="0001";

else begin

if (dir==1'b0)

shift_reg= {shift_reg[2:0],shift_reg [3]}; else

shift_reg= {shift_reg[0],shift_reg [3:1]}; end

end

assign stepout = shift_reg;

endmodule

HDL Lab (17ECL58) 2019-20


Procedure:

1. Make the connection between frc5 of the FPGA board to the LCD display

connector of the vtu card1.

2. Make the connection between frc10 of the FPGA board to the ADC


3. Make the connection between frc6 of the FPGA board to the dip switch


4. Short the jumper j1 to the vin to get the analog signal.


HDL Lab (17ECL58) 2019-20



VHDL code to accept 8 channel analog signal, temperature

sensors and display the data on LCD panel or seven

segment display.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.lcd_grap.all;

library unisim;

use unisim.vcomponents.all;

entity adc_lcd is

port ( clk: in std_logic; -- 4 mhz clock

reset: in std_logic; -- master reset pin

intr: in std_logic;

adc_out: in std_logic_vector(7 downto 0);

cs,rd,wr:out std_logic;

lcd_rw : out std_logic;

lcd_select : out std_logic;

lcd_enable : out std_logic;

lcd_data: out std_logic_vector (7 downto 0)); -- gives registered

data output

end adc_lcd;

architecture adc_beh of adc_lcd is

type state_type is (initial,display,clear,location,putchar);

signal state,next_state: state_type;

-- clear screen.

constant clr: std_logic_vector(7 downto 0) := "00000001";

-- display on, without cursor.

constant don: std_logic_vector(7 downto 0) := "00001100";

-- function set for 8-bit data transfer and 2-line display

constant set: std_logic_vector(7 downto 0) := "00111000";

--frequency divider

signal counter : std_logic_vector(18 downto 0);

signal clk_div :std_logic;

constant big_delay: integer :=16;

HDL Lab (17ECL58) 2019-20


constant small_delay: integer :=2;

constant reg_setup: integer :=1;

signal digital_data1,data1,data2: std_logic_vector(7 downto 0);

signal digital_data : integer range 0 to 255;

signal ntr :std_logic;

begin

ibuf_inst : ibuf

-- edit the following generic to specify the i/o standard for this

port.

generic map (

iostandard => "lvcmos25")

port map (

o => ntr, -- buffer output

i => intr -- buffer input (connect directly to top-level port));

process(clk)

begin

if clk='1' and clk'event then

counter<=counter+'1';

end if;

end process;

clk_div<=counter(7);

cs <='0';

wr <=ntr;

digital_data1 <= adc_out ;

rd <='0';

digital_data<=conv_integer(digital_data1) ;

process(digital_data)

begin

case (digital_data) is

when 0 to 100 => data1 <= one ; data2 <= nine ;

when 101 to 110 => data1 <= two ; data2 <= zero ;

when 111 to 120 => data1 <= two ; data2 <= one ;

when 121 to 130 => data1 <= two ; data2 <= two ;

when 131 to 140 => data1 <= two ; data2 <= three ;

when 141 to 150 => data1 <= two ; data2 <= four ;

when 151 to 160 => data1 <= two ; data2 <= five ;

when 161 to 170 => data1 <= two ; data2 <= six ;

HDL Lab (17ECL58) 2019-20


when 171 to 180 => data1 <= two ; data2 <= seven ;

when 181 to 190 => data1 <= two ; data2 <= eight ;

when 191 to 200 => data1 <= two ; data2 <= nine ;

when 201 to 205 => data1 <= three ; data2 <= zero ;

when 206 to 210 => data1 <= three ; data2 <= one ;

when 211 to 215 => data1 <= three ; data2 <= two ;

when 216 to 220 => data1 <= three ; data2 <= three ;

when 221 to 225 => data1 <= three ; data2 <= four ;

when 226 to 230 => data1 <= three ; data2 <= five ;

when 231 to 235 => data1 <= three ; data2 <= six ;

when 236 to 240 => data1 <= three ; data2 <= seven ;

when 241 to 245 => data1 <= three ; data2 <= eight ;

when 246 to 250 => data1 <= three ; data2 <= nine ;

when others => data1 <= four ; data2 <= zero ;

end case;

end process;

lcd_rw<='0';

process (clk_div,reset)

variable count: integer range 0 to big_delay;

variable c1 : std_logic_vector(7 downto 0);

begin

if reset = '1' then

state<=initial;

count:=0;

lcd_enable<='0';

lcd_select<='0';

c1 := "01111111";

elsif clk_div'event and clk_div = '1' then

case state is

when initial => -- to set the function

if count=reg_setup then

lcd_enable<='1';

else

lcd_enable<='0';

end if;

lcd_data<=set;

lcd_select<='0';

HDL Lab (17ECL58) 2019-20


if count=small_delay then

state<=display;

count:=0;

else

count:=count+1;

end if;

when display => -- to set display on


lcd_enable<='1';

else

lcd_enable<='0';

end if;

lcd_data<=don;

lcd_select<='0';


state<=clear;

count:=0;

else

count:=count+1;

end if;

when clear => -- clear the screen


lcd_enable<='1';

else

lcd_enable<='0';

end if;

lcd_data<=clr;

lcd_select<='0';

if count=big_delay then

state<=location;

count:=0;

else

count:=count+1;

end if;

when location => -- clear the screen


lcd_enable<='1';

HDL Lab (17ECL58) 2019-20


else

lcd_enable<='0';

end if;

if count=0 then

if c1="10001111" then

c1:="10000000";

else

c1:=c1+'1';

end if;

end if;

lcd_data <= c1 ;

lcd_select<='0';

if count=big_delay then

state<=putchar;

count:=0; else

count:=count+1;

end if;

when putchar=> -- display the character on the lcd


lcd_enable<='1';

else lcd_enable<='0';

end if;

case c1 is

when "10000000" => lcd_data<= a ;

when "10000001" => lcd_data<= d ;

when "10000010" => lcd_data<= c ;

when "10000011" => lcd_data<= space ;

when "10000100" => lcd_data<= v ;

when "10000101" => lcd_data<= o ;

when "10000110" => lcd_data<= l ;

when "10000111" => lcd_data<= t ;

when "10001000" => lcd_data<= a ;

when "10001001" => lcd_data<= g ;

when "10001010" => lcd_data<= e ;


when "10001100" => lcd_data<= equal ;

when "10001101" => lcd_data<= data1 ;

HDL Lab (17ECL58) 2019-20


when "10001110" => lcd_data<= dot ;

when "10001111" => lcd_data<= data2;



when "11000010" => lcd_data<= space;














when others => null;

end case ;

lcd_select<='1';


state<=location;

count:=0;

else

count:=count+1;

end if;

end case;

end if;

end process;

end adc_beh;

HDL Lab (17ECL58) 2019-20



HDL Lab (17ECL58) 2019-20


Design:

Given frequency, [fm]=2KHz

System frequency, [fs]=4MHz

Time, [T] =1/fm=0.5ms

Duty cycle, [DC]=50%

Count*1/fc= T

256*1/fc=0.5ms

fc=512 KHz

2N =fs/fc

4 MHz/512 KHz =8

N=3

Counter value =DC*Count

0.50*256

128

Divide by N counter 8-bit Counter 4MHz fc 0 to 255

fc

f

0 255

0 127

HDL Lab (17ECL58) 2019-20


Experiment No 5a : Date: __/__/____

Verilog Code to generate Sine wave using DAC

module sine_wave_gen(Clk,data_out);

input Clk;

output [7:0] data_out;

//declare the sine ROM - 30 registers each 8 bit wide.

reg [7:0] sine [0:29];

integer i;

reg [7:0] data_out;

initial begin

i = 0;

sine[0] = 0;

sine[1] = 16;

sine[2] = 31;

sine[3] = 45;

sine[4] = 58;

sine[5] = 67;

sine[6] = 74;

sine[7] = 77;

sine[8] = 77;

sine[9] = 74;

sine[10] = 67;

sine[11] = 58;

sine[12] = 45;

sine[13] = 31;

sine[14] = 16;

HDL Lab (17ECL58) 2019-20


Procedure:

1. Make the connection between FRC5 of the FPGA board and DAC

connector of GPIOcard-2






HDL Lab (17ECL58) 2019-20


sine[15] = 0;

sine[16] = -16;

sine[17] = -31;

sine[18] = -45;

sine[19] = -58;

sine[20] = -67;

sine[21] = -74;

sine[22] = -77;

sine[23] = -77;

sine[24] = -74;

sine[25] = -67;

sine[26] = -58;

sine[27] = -45;

sine[28] = -31;

sine[29] = -16;

end

//At every positive edge of the clock, output a sine wave sample.

always@ (posedge(Clk))

begin

data_out = sine[i];

i = i+ 1;

if(i == 29)

i = 0;

end

endmodule

HDL Lab (17ECL58) 2019-20


Design:

Given frequency, [fm]=2 KHz

System frequency, [fs]=4 MHz

Time, [T] =1/fm=0.5ms

Duty Cycle, [DC]=50%

Count*1/fc= T

256*1/fc=0.5ms

fc=512 KHz

2N =fs/fc

4 MHz/512 KHz =8

N=3

Counter value =DC*Count

0.50*256

128

Divide by N counter 8-bit Counter 4MHz fc 0 to 255

fc

f

0 255

0 127

HDL Lab (17ECL58) 2019-20



Verilog Code to generate Square wave using DAC

module square_wave(clk,rst,dac_out);

input clk;

input rst;

output [0:7] dac_out;

reg [7:0] div;

reg [0:7] counter;

reg [0:7] dac_out;


begin

div= div + 1'b1;

end


begin

if (rst)

counter =8'b0000000;

else

counter<=counter + 1'b1;

end

always @(counter)

begin

if(counter<=127)

dac_out=8'd1;

else

dac_out=8'd0;

end

endmodule

HDL Lab (17ECL58) 2019-20


Procedure:








HDL Lab (17ECL58) 2019-20



Verilog Code to generate Triangular wave using DAC

module triangularwave(clk,rst, dac_out);

input clk,rst;

output [0:7] dac_out;

reg [3:0] div;

reg [0:8] counter;

reg [0:7] dac_out;


begin

div = div +1'b1;

end


begin

if (rst ==1'b1)

begin

counter = 9'b00000000;

end

else begin

counter = counter + 1'b1;

if (counter[0] == 1 ) begin

dac_out = counter[1:8];

end

else begin

dac_out = ~(counter[1:8]);

end

end

end

endmodule

HDL Lab (17ECL58) 2019-20


Procedure:








HDL Lab (17ECL58) 2019-20



Verilog Code to generate Ramp/Sawtooth wave using DAC

module rampwave(clk, rst, dac_out);

input clk;

input rst;

output [0:7]dac_out;

reg [7:0] div;

reg [0:7] counter;

reg [0:7] dac_out;

always@(posedge clk)

begin

div=div+1'b1;

end

always@(posedge div[3])

begin

if(rst==1'b1)

counter=8'b00000000;

else

begin

counter=counter+1;

dac_out=counter[0:7];

end

end

endmodule

HDL Lab (17ECL58) 2019-20


Procedure:

1. Make the connection between frc5 of the FPGA board to the LCD display


2. Make the connection between frc1 of the FPGA board to the keyboard


3. Make the connection between frc6 of the FPGA board to the dip switch


4. Connect the downloading cable and power supply to the FPGA board.



HDL Lab (17ECL58) 2019-20



Verilog code to simulate Elevator operations.

module floor (clk,rst,ra,rb,rc,floor);

input clk,rst;

input ra,rb,rc;

output reg [1:0] floor;

reg [1:0] floor_next;

reg dir_next;

reg dir;

parameter A=0,B=1,C=2;

parameter up=1,down=0;

always@ (posedge clk)

begin

if (rst) floor<=A;

else

floor<=floor_next;

end

//flowchart for floor

always@ (*)

begin

case (floor)

A:

case (1) //ra is condition

ra:floor_next=A;

rb:floor_next=B;

HDL Lab (17ECL58) 2019-20


rc:floor_next=C;

//rd:floor_next=D;

default:floor_next=A;

endcase

B:

if (rb) floor_next=B;

else

begin

if (dir)

begin

case (1)

rc:floor_next<=C;

//rd:floor_next<=D;

ra:floor_next<=A;

default:floor_next<=B;

endcase

end

else

begin

case (1)

ra:floor_next<=A;

rc:floor_next<=C;

//rd:floor_next<=D;

default:floor_next<=B;

endcase

end

HDL Lab (17ECL58) 2019-20


end

C:

case (1)

//rd:floor_next<=D;

rc:floor_next<=C;

rb:floor_next<=B;

ra:floor_next<=A;

default:floor_next<=C;

endcase

endcase

end

//flowchart for direction

always@ (posedge clk)

begin

if (rst) dir<=up;

else dir<=dir_next;

end

always@ (*)

begin

case (dir)

up:

case (floor)

HDL Lab (17ECL58) 2019-20


B:

case (1)

rb:dir_next=up;

rc:dir_next=down;

//rd:dir_next=down;

default:dir_next=up;

endcase

C:

case (1)

rc:dir_next=down;

//rd:dir_next=down;

rb:dir_next=down;

default:dir_next=up;

endcase

default :dir_next=up;

endcase

down:

case (floor)

B:

case (1)

//rc:dir_next=down;

rb:dir_next=down;

ra:dir_next=up;

default:dir_next=down;

endcase

HDL Lab (17ECL58) 2019-20


A:

case (1)

ra:dir_next=up;

rb:dir_next=up;

rc:dir_next=down;


endcase


endcase

endcase

end

endmodule

HDL Lab (17ECL58) 2019-20


Additional Experiments

1. VHDL Code to realize 4-bit Braun multiplier

entity braun_multiplier4 is

port ( a : in std_logic_vector (3 downto 0);

b : in std_logic_vector (3 downto 0);

p : out std_logic_vector (7 downto 0));

end braun_multiplier4;

architecture behavioral of braun_multiplier4 is

signal s1,s2,s3,s4 :std_logic_vector (3 downto 0);

signal f1,f2,f3,f4 :std_logic_vector (4 downto 0);

component and21

port( a : in std_logic;

b : in std_logic;

c : out std_logic);

end

componentcomponent f_adder

port ( a : in std_log ic;

b : in std_logic;

c : in std_logic;

sum : out std_logic;

carry : out std_logic);

end component;

begin

g1: for i in 0 to 3 generate

a1: and21 port map (b(0),a(i),s1(i));

p(0) <=s1(0);

end generate;

g2: for j in 0 to 3 generate

a2: and21 port map (b(1),a(j),s2(j));

end generate;

fa1: f_adder port map (s1(1),s2(0),'0',p(1),f1(0));

fa2: f_adder port map (s1(2),s2(1),'0',f1(1),f1(2));

fa3: f_adder port map (s1(3),s2(2),'0',f1(3),f1(4));

g3: for k in 0 to 3 generate

HDL Lab (17ECL58) 2019-20


a3: and21 port map (b(2),a(k),s3(k));

end generate;

fa4: f_adder port map (s3(0),f1(0),f1(1),p(2),f2(0));

fa5: f_adder port map (s3(1),f1(2),f1(3),f2(1),f2(2));

fa6: f_adder port map (s3(2),f1(4),s2(3),f2(3),f2(4));

g4: for l in 0 to 3 generate

a3: and21 port map (b(3),a(l),s4(l));

end generate;

fa7: f_adder port map (s4(0),f2(0),f2(1),p(3),f3(0));

fa8: f_adder port map (s4(1),f2(2),f2(3),f3(1),f3(2));

fa9: f_adder port map (s4(2),f2(4),s3(3),f3(3),f3(4));

fa10: f_adder port map ('0',f3(0),f3(1),p(4),f4(0));

fa11: f_adder port map (f4(0),f3(2),f3(3),p(5),f4(1));

fa12: f_adder port map (f4(1),f3(4),s4(3),p(6),p(7));

end behavioral;

HDL Lab (17ECL58) 2019-20


2. VHDL Code to control external lights using Relays.

Procedure:

1. Make the connection between frc9 of the FPGA board to the

external light connector of the vtu card2.

2. Make the connection between frc1 of the FPGA board to the

dipswitch connector of the vtu card2.

3. Connect the downloading cable and power supply to the FPGA

board.

4. Then open the xilinx impact software (refer ise flow) select the

slave serial mode and select the respective bit file and click

program.

5. Make the reset switch on (active low) and analyze the data.

entity extlight is

port ( cntrl1,cntrl2 : in std_logic;

light : out std_logic);

end extlight;

architecture behavioral of extlight is

begin

light<= cntrl1 or cntrl2 ;

end behavioral;

HDL Lab (17ECL58) 2019-20


3. Verilog Code to realize ripple carry adder

Figure:. Ripple Carry Counter

module ripple_carry_counter(q, clk, reset);

output [3:0] q;

input clk, reset

T_FF tff0(q[0],clk, reset);

T_FF tff1(q[1],q[0], reset);



endmodule

module T_FF(q, clk, reset);

output q;

input clk, reset;

wire d;

D_FF dff0(q, d, clk, reset);

not n1(d, q);

endmodule

module D_FF(q, d, clk, reset);

output q;

input d, clk, reset;

reg q;

always @(posedge reset or negedge clk)

if (reset)

q <= 1'b0;

else

q <= d;

endmodule

VIVA QUESTIONS

1. What is Verilog language?

2. Which block describes a design's interface?

3. Which block describes a design's behavior?

4. What is the difference between simulation and synthesis?

5. Which data type defines a single logic signal?

6. Which data type describes a bus?

7. What two ways can a vector's range be described?

8. What are the only two values for a Boolean type?

9. What are the numerical data types?

10. What type is use to create a user data type?

11. What reserved word is used to declare a user data type?

12. Which data type includes time units as values?

13. Create the module block for a three input XOR gate.

14. Which keyword is used to end Verilog program?

15. What part of a port declaration defines signals in or out direction?

16. Create the integer constant included in a module BUS_SIZE and assigns it a value of 32?

17. Which symbols are used as an assignment operator to assign a literal to an identifier name?

18. Which symbols are used to assign an expression's result to an output interface signal?

19. What are the rules used to define an identifier name?

20. What symbols define a comment line?

21. How does a transport delay differ from an inertial delay?

22. What is the purpose of a SIGNAL declaration?

23. Where are SIGNAL declarations placed in the design?

24. Write an assignment statement that assigns the contents of S(5) to t(2).

25. What is the purpose of a process' sensitivity list?

26. Under what conditions is a process run?

27. What is an EVENT? What is the difference between event and non-event driven process?

28. Which symbols are used to differentiate between logic 1 and an integer 1?

29. In an if..then..else construct, which statements are executed if the condition is TRUE and

which if it is FALSE?

30. What is the purpose of a for loop?

31. What are the requirements for a for loop?

32. What is meant by instantiating a component?

33. How do signal declarations differ from port interface declarations?

34. What is the prime use of signals?

35. How many parameters can be passed into a function?

36. Write a function that returns the sum of two 8-bit words.

37. How are functions called?

38. How do procedures differ from functions?

Question Bank

1. a) Write verilog code to realize all the logic gates.

b) Write verilog code to display a character on the given seven segment display by

accepting hex key pad input data.

2. a) Write verilog code to realize 2 to 4 decoder.

b) Write verilog code to display a character on the given seven segment display by

accepting hex key pad input data.

3. a) Write Verilog code to realize 8 to 3 encoder with priority.

b) Write Verilog code to control the direction of stepper motor.

4. a) Write Verilog code to realize 8 to 3 encoder without priority.

b) Write Verilog code to control the direction of stepper motor.

5. a) Write Verilog code to realize 8 to 1 multiplexer.

b) Write Verilog code to control the speed and direction of DC motor.

6. a) Write Verilog code to realize 1 to 4 De-multiplexer.

b) Write Verilog code to control the speed and direction of DC motor.

7. a) Write Verilog code to realize 4 –bit Binary to Gray converter.

b) Write Verilog code to generate square waveform using DAC for given duty cycle.

8. a) Write Verilog code to realize 4 –bit comparator.

b) Write Verilog code to generate triangular waveform using DAC.

9. a) Write Verilog code to model 32-bit ALU.

b) Write Verilog code to generate ramp waveform using DAC.

10. a) Write Verilog code to realize SR flip-flop.

b) Write Verilog code to generate ramp waveform using DAC.

11. a) Write Verilog code to realize JK flip-flop.

b) Write Verilog code to generate sine waveform using DAC.

12. a) Write Verilog code to realize D and T flip-flop.

b) Write Verilog code to display message on LCD display.

13. a) Write Verilog code to realize 4-bit asynchronous reset binary counter.

b) Write Verilog code to display message on LCD display.

14. a) Write Verilog code to realize 4-bit synchronous reset binary counter.

b) Write Verilog code to simulate elevator operation for three floors.

15. a) Write Verilog code to realize 3-bit any sequence counter.

b) Write Verilog code to simulate elevator operation for three floors.

16. a) Write Verilog code to realize 4-bit synchronous reset BCD counter.

b) Write Verilog code to generate sine waveform using DAC.

17. a) Write Verilog code to realize 4-bit asynchronous reset BCD counter.

b) Write Verilog code to generate square waveform using DAC.

hdl laboratory

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