hcpleed7840

8/10/2019 hcpleed7840

1/121-248

H

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component toprevent damage and/or degradation which may be induced by ESD.

HCPL-7840

Analog Isolation Amplifier

Technical Data

A 0.1 F bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8.

Features

High Common Mode

Rejection (CMR): 15 kV/sat VCM= 1000 V

5% Gain Tolerance

0.1% Nonlinearity

Low Offset Voltage and Off-

set Temperature Coefficient

100 kHz Bandwidth

Performance Specified Over

-40C to 85C TemperatureRange

Recognized Under UL 1577

and CSA Approved for

Dielectric Withstand Proof

Test Voltage of 2500 Vac, 1

Minute

Standard 8-Pin DIP Package

Applications

Motor Phase and Rail

Current Sensing

Inverter Current Sensing

Switched Mode Power

Supply Signal Isolation

General Purpose CurrentSensing and Monitoring

General Purpose Analog

Signal Isolation

Description

The HCPL-7840 isolation ampli-

fier provides accurate, electricallyisolated and amplified representa-tions of voltage and current.

When used with a shunt resistorin the current path, the HCPL-7840 offers superior reliability,cost effectiveness, size andautoinsertability compared withthe traditional solutions such ascurrent transformers and Hall-effect sensors.

The HCPL-7840 consists of asigma-delta analog-to-digitalconverter optically coupled to adigital-to-analog converter.Superior performance in designcritical specifications such ascommon-mode rejection, offset

voltage, nonlinearity, operatingtemperature range and regulatorycompliance make the HCPL-7840the clear choice for designingreliable, lower-cost, reduced-size

products such as motorcontrollers and inverters.

Common-mode rejection of15 kV/s makes the HCPL-7840suitable for noisy electrical

environments such as thosegenerated by the high switching

rates of power IGBTs.

Low offset voltage together witha low offset voltage temperaturecoefficient permits accurate useof auto-calibration techniques.

Gain tolerance of 5% with 0.1%nonlinearity further provide theperformance necessary foraccurate feedback and control.

A wide operating temperaturerange with specified performanceallows the HCPL-7840 to be usedin hostile industrial environments.

Functional Diagram

1

2

3

4

8

7

6

5

IDD1VDD1

VIN+

VIN

GND1

IDD2VDD2

VOUT+

VOUT

GND2

+

+

SHIELD

5965-4784E

8/10/2019 hcpleed7840

2/121-249

Package Outline Drawings

Standard DIP Package9.65 0.25

(0.380 0.010)

1.78 (0.070) MAX.1.19 (0.047) MAX.

HP 7840

YYWW

DATE CODE

1.080 0.320(0.043 0.013)

2.54 0.25(0.100 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

7.62 0.25

(0.300 0.010)

5TYP.

5678

4321

6.35 0.25(0.250 0.010)

0.20 (0.008)0.33 (0.013)

0.635 0.25(0.025 0.010)

12NOM.

0.20 (0.008)0.33 (0.013)

9.65 0.25(0.380 0.010)

0.635 0.130(0.025 0.005)

7.62 0.25(0.300 0.010)

5678

4321

9.65 0.25(0.380 0.010)

6.350 0.25(0.250 0.010)

1.016 (0.040)1.194 (0.047)

1.194 (0.047)1.778 (0.070)

9.398 (0.370)9.960 (0.390)

4.826(0.190)

TYP.

0.381 (0.015)0.635 (0.025)

PAD LOCATION (FOR REFERENCE ONLY)

1.080 0.320(0.043 0.013)

4.19(0.165)

MAX.

1.780(0.070)MAX.1.19

(0.047)MAX.

2.54(0.100)BSC

DIMENSIONS IN MILLIMETERS (INCHES).TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01

xx.xxx = 0.005

HP 7840

YYWW

LEAD COPLANARITYMAXIMUM: 0.102 (0.004)

Gull Wing Surface Mount Option 300

Ordering Information

HCPL-7840#xxx

No option = Standard DIP Package, 50 per tube

300 = Gull Wing Surface Mount Lead Option, 50 per tube

500 = Tape/Reel Package Option (1 K min.), 1000 per reel

Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor formore information.

8/10/2019 hcpleed7840

3/121-250

Maximum Solder Reflow Thermal Profile Regulatory Information

The HCPL-7840 has beenapproved by the following

organizations:

UL Recognized under UL 1577,Component RecognitionProgram, File E55361.

CSAApproved under CSAComponent Acceptance Notice#5, File CA 88324.

240

T = 115C, 0.3C/SEC

0

T = 100C, 1.5C/SEC

T = 145C, 1C/SEC

TIME MINUTES

TEMPERATUREC

220

200

180

160

140

120

100

80

60

40

20

0

260

1 2 3 4 5 6 7 8 9 10 11 12

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

Insulation and Safety Related Specifications

Parameter Symbol Value Units Conditions

Min. External Air Gap L(IO1) 7.1 mm Measured from input terminals to output(External Clearance) terminals, shortest distance through air.

Min. External Tracking Path L(IO2) 7.4 mm Measured from input terminals to output(External Creepage) terminals, shortest distance path along body.

Min. Internal Plastic Gap 0.08 mm Through insulation distance, conductor to(Internal Clearance) conductor, usually the direct distance

between the photoemitter and photodetectorinside the optocoupler cavity.

Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1(Comparative Tracking Index)

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Unit Note

Storage Temperature TS -55 125 C

Ambient Operating Temperature TA -40 85 CSupply Voltages V DD1, VDD2 0.0 5.5 V

Steady-State Input Voltage V IN+,VIN- -2.0 V DD1 +0.5 V 1

2 Second Transient Input Voltage -6.0

Output Voltages V OUT+,VOUT- -0.5 V DD2 +0.5 V

Lead Solder Temperature TLS 260 C(10 sec., 1.6 mm below seating plane)

Solder Reflow Temperature Profile See Maximum Solder Reflow Thermal Profile Section

8/10/2019 hcpleed7840

4/121-251

DC Electrical SpecificationsAll specifications, typicals and figures are at the nominal operating conditions of VIN+= 0 V, VIN-= 0 V,TA= 25C, VDD1= 5 V and VDD2= 5 V, unless otherwise noted.

Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note

Input Offset Voltage V OS -1.2 -0.2 1.0 mV 1 2

-3.0 -0.2 2.0 -40C TA 85C 1,2,34.5 (VDD1, VDD2) 5.5 V

Gain G 7.60 8.00 8.40 V/V -200 VIN+ 200 mV 57.44 8.00 8.56 -200 VIN+ 200 mV 5,6,7

-40C TA 85C4.5 (VDD1, VDD2) 5.5 V

200 mV Nonlinearity NL200 0.1 0.2 % -200 VIN+ 200 mV 5, 8 3

0.4 -200 VIN+ 200 mV 5,8,9-40C TA 85C 10,124.5 (VDD1, VDD2) 5.5 V

100 mV Nonlinearity NL100 0.05 0.1 -100 VIN+ 100 mV 5, 8

0.2 -100 VIN+ 100 mV 5,8,9-40C TA 85C 11,124.5 (VDD1, VDD2) 5.5 V

Maximum Input Voltage |VIN+| 320 mV 4

Before Output ClippingAverage Input Bias Current IIN -0.57 A 13 4

Average Input Resistance RIN 480 k

Input DC Common-Mode CMRRIN 69 dB 5Rejection Ratio

Output Resistance RO 1

Output Low Voltage V OL 1.28 V V IN+= 400 mV 4 6

Output High Voltage V OH 3.84 V V IN+= -400 mV

Output Common-Mode V OCM 2.20 2.56 2.80 V -400 < V IN+< 400 mVVoltage

Input Supply Current IDD1 8.7 15.5 mA 14

Output Supply Current IDD2 8.8 14.5 mA 15

Output Short-Circuit Current |IOSC| 11 mA V OUT= 0 V or VDD2 7

-40C TA 85C4.5 (VDD1, VDD2) 5.5 V

MAX

Recommended Operating Conditions

Parameter Symbol Min. Max. Unit Note

Ambient Operating Temperature TA -40 85 C

Supply Voltages V DD1, VDD2 4.5 5.5 V

Input Voltage V IN+,VIN- -200 200 mV 1

8/10/2019 hcpleed7840

5/121-252

AC Electrical SpecificationsAll specifications, typicals and figures are at the nominal operating conditions of VIN+= 0 V, VIN-= 0 V,TA= 25C, VDD1= 5 V and VDD2= 5 V, unless otherwise noted.


Common Mode CMR 10 15 kV/ s VCM= 1 kV 16 8Rejection 4.5 (VDD1, VDD2) 5.5 V

Common Mode CMRR >140 dB 9Rejection Ratioat 60 Hz

Propagation Delay tPD50 3.7 6.5 s VIN+= 0 to 100 mV step 17,18to 50% -40C TA 85C

4.5 (VDD1, VDD2) 5.5 V

Propagation Delay tPD90 5.7 9.9to 90%

Rise/Fall Time tR/F 3.4 6.6

(10-90%)Small-Signal f -3 dB 50 100 kHz -40C TA 85C 17, 19,Bandwidth 4.5 (VDD1, VDD2) 5.5 V 20(-3 dB)

Small-Signal f -45 33Bandwidth (-45)

RMS Input- V N 0.6 mV rms In recommended 21, 23 10Referred Noise application circuit

Power Supply PSR 570 mV P-P 11Rejection

Package CharacteristicsAll specifications, typicals and figures are at the nominal operating conditions of VIN+= 0 V, VIN-= 0 V,TA= 25C, VDD1= 5 V and VDD2= 5 V, unless otherwise noted.


Input-Output Momentary VISO 2500 V rms t = 1 min., RH 50% 12,13Withstand Voltage*

Input-Output Resistance RI-O 1012 VI-O= 500 Vdc 13

Input-Output Capacitance CI-O 0.6 pF f = 1 MHzVI-O= 0 Vdc

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating, refer to the VDE 0884 Insulation Characteristics Table (if applicable),your equipment level safety specification, or HP Application Note 1074, Optocoupler Input-Output Endurance Voltage.

8/10/2019 hcpleed7840

6/121-253

Figure 1. Input Offset Voltage Test Circuit.

Figure 2. Input Offset Change vs.Temperature.

Figure 3. Input Offset Change vs.VDD1and VDD2.

VOSINPUTOFFSETCHANG

EmV

VDD SUPPLY VOLTAGE V

0.2

0.1

4.6

0.3

4.8 5.0 5.2

TA= 25C

-0.1

vs. VDD1 (VDD2= 5 V)

4.4 5.65.4

vs. VDD2

(VDD1

= 5 V)

0

VOSINPUTOFFSETCHANG

EmV

TA TEMPERATURE C

0

-0.2

-0.6

-20

0.6

20 60

VDD1= 5 V

VDD2= 5 V

-0.8

0.2

0.4

-40 100

-0.4

0 40 80

Notes:

1. If VIN-is brought above VDD1- 2 V

with respect to GND1 an internal test

mode may be activated. This testmode is not intended for customer

use.

2. Exact offset value is dependent on

layout of external bypass capacitors.The offset value in the data sheet

corresponds to HPs recommendedlayout (see Figures 25 and 26).

3. Nonlinearity is defined as half of thepeak-to-peak output deviation fromthe best-fit gain line, expressed as a

percentage of the full-scale differen-tial output voltage.

4. Because of the switched capacitor

nature of the sigma-delta A/Dconverter, time-averaged values are

shown.

5. CMRRINis defined as the ratio of thegain for differential inputs applied

between pins 2 and 3 to the gain forcommon mode inputs applied to bothpins 2 and 3 with respect to pin 4.

6. When the differential input signal

exceeds approximately 320 mV, theoutputs will limit at the typical values

shown.

7. Short-circuit current is the amount of

output current generated when eitheroutput is shorted to VDD2or ground.

HP does not recommend operation

under these conditions.8. CMR (also known as IMR or Isolation

Mode Rejection) specifies the

minimum rate of rise of a common

mode noise signal applied across theisolation boundary at which small

output perturbations begin to appear.

These output perturbations can occurwith both the rising and falling edges

of the common mode waveform and

may be of either polarity. A CMRfailure is defined as a perturbation

exceeding 200 mV at the output of

the recommended application circuit(Figure 23). See applications section

for more information on CMR.

9. CMRR is defined as the ratio ofdifferential signal gain (signal applied

differentially between pins 2 and 3)to the common mode gain (input pinstied to pin 4 and the signal applied

between the input and the output ofthe isolation amplifier) at 60 Hz,expressed in dB.

10. Output noise comes from two primarysources: chopper noise and sigma-

delta quantization noise. Chopper

noise results from chopper stabiliza-tion of the output op-amps. It occurs

at a specific frequency (typically 500

kHz) and is not attenuated by the on-chip output filter. The on-chip filter

does eliminate most, but not all, of

the sigma-delta quantization noise.

An external filter circuit may beeasily added to the external post-

amplifier to reduce the total RMS

output noise. See applications sectionfor more information.

11. Data sheet value is the amplitude of

the transient at the differential outputof the HCPL-7840 when a 1 VP-P,

1 MHz square wave with 100 ns rise

and fall times (measured at pins 1and 8) is applied to both VDD1 and

VDD2.

12. In accordance with UL1577, eachisolation amplifer is proof tested by

applying an insulation test voltage 3000 VRMSfor 1 second (leakagecurrent detection limit II-O

5 A).

13. Device considered a two terminaldevice: Pins 1, 2, 3 and 4 connectedtogether; pins 5, 6, 7 and 8

connected together.

0.1 F

VDD2

VOUT

8

7

6

1

3

HCPL-7840

5

2

4

0.1 F

10 K

10 K

VDD1 +15 V

0.1 F

0.1 F

-15 V

+

AD624CDGAIN = 100

0.47F

0.47F

Figure 4. Output Voltages vs. InputVoltage.

VOOUTPUTVOLTAGEV

VIN INPUT VOLTAGE V

2.5

2.0

1.5

-0.4

4.0

-0.2 0 0.2

VDD1= 5 VVDD2= 5 VTA= 25C

1.0

3.0

3.5

-0.6 0.60.4

POSITIVEOUTPUT

NEGATIVEOUTPUT

8/10/2019 hcpleed7840

7/121-254

0.1 F

VDD2

8

7

6

1

3

HCPL-7840

5

2

4

0.01 F

10 K

10 K

+15 V

0.1 F

0.1 F

-15 V

+

AD624CDGAIN = 4

0.47F

0.47F

VDD1

13.2

404VIN

VOUT

+15 V

0.1 F

0.1 F

-15 V

+

AD624CDGAIN = 10

10 K

0.47F

0.1 F

Figure 6. Gain Change vs.Temperature.

Figure 5. Gain and Nonlinearity Test Circuit.

Figure 7. Gain Change vs. VDD1andVDD2.

Figure 8. Nonlinearity Error Plot vs.Input Voltage.

GGAINCHANGE%

TA TEMPERATURE C

0

-0.3

-20

0.1

20 60

VDD1= 5 V

VDD2= 5 V

-0.5

-40 100

-0.1

0 40 80

-0.2

-0.4 GGAINCHANGE%


0.04

0.02

4.6

0.10

4.8 5.0 5.2

TA= 25C

-0.06

0.06

vs. VDD1 (VDD2= 5 V)0.08

4.4 5.65.4


0

-0.02

-0.04NLERROR%OFFULLSCALE

VIN+ INPUT VOLTAGE V

-0.05

-0.1

0.15

0 0.1

-0.10

0.05

200 mV ERROR

0.10

-0.2 0.2

100 mV ERROR

VDD1= 5 VVDD2= 5 VVIN= 0 VTA= 25C

0

Figure 9. Nonlinearity vs.Temperature.

Fibure 10. 200 mV Nonlinearity vs.VDD1and VDD2.

Figure 11. 100 mV Nonlinearity vs.VDD1and VDD2.

NLNONLINEAR

ITY%

TA TEMPERATURE C

0.10

0.05

0

0.20

20 600

0.15

200 mV NL

-40 100

100 mV NL

VDD1= 5 VVDD2= 5 VVIN= 0 VTA= 25 C

-20 40 80

NLNONLINEAR

ITY%


0.10

0.09

4.6

0.12

4.8 5.0 5.2

TA= 25C

0.08


0.11

4.4 5.65.4


NLNONLINEAR

ITY%


0.050

0.045

4.6

0.060

4.8 5.0 5.2

TA= 25C

0.040


0.055

4.4 5.65.4


8/10/2019 hcpleed7840

8/121-255

Figure 16. Common Mode RejectionTest Circuit.

Figure 15. Output Supply Current vs.Input Voltage.

Figure 18. Propagation Delays andRise/Fall Time vs. Temperature.

Figure 17. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit.

IININPUTCURRENT

mA


-4

-6

-8

-4

2

-2 0 2

VDD1= 5 V

VDD2= 5 V

VIN= 0 V

TA= 25C

-10

-2

0

-6 64

NLNONLINEARITY

%

FS FULL-SCALE INPUT VOLTAGE V

0.50

5.00

0.10 0.20

VDD1= 5 VVDD2= 5 V

0.01

TA= 85C

0 0.40

TA= -40C

0.05

TA= 25C

0.30IDD1INPUTSUPPLYCURR

ENTmA


9

11

-0.2 0

VDD1= 5 VVDD2= 5 VVIN= 0 V

6

TA= 85C

-0.4 0.40.2

TA= -40C

TA= 25C10

8

7

Figure 12. Nonlinearity vs. Full-ScaleInput Voltage.

Figure 13. Input Current vs. InputVoltage.

Figure 14. Input Supply Current vs.Input Voltage.

IDD2

OUTPUTSUPPLYCURRENTmA


10.0

-0.2 0

VDD1= 5 VVDD2= 5 VVIN= 0 V

8.0

TA= 85C

-0.4 0.40.2

TA= -40C

9.0

TA= 25C

9.5

8.5

0.1 F

VDD2

VOUT

8

7

6

1

3

HCPL-7840

5

2

4

2 K

2 K

78L05+15 V

0.1 F

0.1 F

-15 V

+ MC34081

150

pF

IN OUT

0.1F

0.1F

9 V

PULSE GEN.

VCM

+

10 K

10 K

150 pF

tTIMEs

TA TEMPERATURE C

9

-20 02

DELAY TO 90%

-40 10020

RISE/FALL TIME

6

DELAY TO 50%

7

4

40 60 80

VIN= 0 VVIN+= 0 TO 100 mV STEP

VDD1= 5 VVDD2= 5 V

3

5

80.1 F

VDD2

VOUT

8

7

6

1

3

HCPL-7840

5

2

4

2 K

2 K

+15 V

0.1 F

0.1 F

-15 V

+ MC34081

0.1 F

10 K

10 K

0.01 F

VDD1

VIN

VINIMPEDANCE LESS THAN 10.

8/10/2019 hcpleed7840

9/121-256

Applications Information

Functional Description

Figure 22 shows the primaryfunctional blocks of the HCPL-7840. In operation, the sigma-delta modulator converts theanalog input signal into a high-speed serial bit stream. The timeaverage of this bit stream isdirectly proportional to the input

signal. This stream of digital datais encoded and optically trans-mitted to the detector circuit. Thedetected signal is decoded andconverted back into an analogsignal, which is filtered to obtainthe final output signal.

Application Circuit

The recommended applicationcircuit is shown in Figure 23. Afloating power supply (which inmany applications could be thesame supply that is used to drivethe high-side power transistor) isregulated to 5 V using a simplethree-terminal voltage regulator(U1). The voltage from the cur-rent sensing resistor, or shunt(Rsense), is applied to the inputof the HCPL-7840 through an RCanti-aliasing filter (R5, C3). And

finally, the differential output ofthe isolation amplifier isconverted to a ground-referencedsingle-ended output voltage witha simple differential amplifiercircuit (U3 and associated com-ponents). Although the applica-tion circuit is relatively simple, afew recommendations should befollowed to ensure optimal

performance.

Supplies and Bypassing

As mentioned above, an inexpen-sive 78L05 three-terminalregulator can be used to reducethe gate-drive power supply

voltage to 5 V. To help attenuatehigh frequency power supplynoise or ripple, a resistor orinductor can be used in series

with the input of the regulator toform a low-pass filter with the

regulators input bypasscapacitor.

As shown in Figure 23, 0.1 Fbypass capacitors (C2, C4)should be located as close aspossible to the input and outputpower supply pins of the HCPL-7840. The bypass capacitors are

required because of the high-speed digital nature of the signalsinside the isolation amplifier. A0.01 F bypass capacitor (C3) isalso recommended at the inputpin(s) due to the switched-capacitor nature of the inputcircuit. The input bypass capaci-tor should be at least 1000 pF tomaintain gain accuracy of the

isolation amplifier.

Inductive coupling between theinput power-supply bypasscapacitor and the input circuit,including the input bypasscapacitor and the input leads ofthe HCPL-7840, can introduceadditional DC offset in the circuit.Several steps can be taken tominimize the mutual couplingbetween the two parts of thecircuit, thereby improving the

offset performance of the design.Separate the two bypasscapacitors C2 and C3 as much aspossible (even putting them onopposite sides of the PC board),

while keeping the total leadlengths, including traces, of eachbypass capacitor less than 20mm. PC board traces should bemade as short as possible and

RELATIVEAMPLITUD

EdB

f FREQUENCY kHz

0

5-4

1 50010

-2

-1

-3

50 100

VDD1

= 5 VVDD2= 5 VTA= 25 C

Figure 19. Amplitude Response vs.Frequency.

Figure 20. 3 dB Bandwidth vs.Temperature

Figure 21. RMS Input-Referred Noisevs. Recommended Application CircuitBandwidth.

f(-3dB)3dBBANDWIDTHkHz

TA TEMPERATURE C

160

-20 040

-40 10020

100

140

80

40 60 80

120

60

VDD1= 5 VVDD2= 5 V

VNRMSINPUT-REFERREDNOISEmV

f FREQUENCY KHz

2.5

100

VIN+= 200 mV

5 50050

VIN+= 0 mV

VIN+= 100 mV

2.0

0.5

100

TA= 25CVDD1= 5 VVDD2= 5 V

1.5

1.0

8/10/2019 hcpleed7840

10/121-257

placed close together or overground plane to minimize looparea and pickup of stray magnetic

fields. Avoid using sockets, asthey will typically increase bothloop area and inductance. Andfinally, using capacitors withsmall body size and orientingthem perpendicular to each otheron the PC board can also help.For more information concerningthis effect, see Application Note1078,Designing with Hewlett-Packard Isolation Amplifiers.

Shunt Resistor Selection

The current-sensing shunt resis-tor should have low resistance (tominimize power dissipation), lowinductance (to minimize di/dtinduced voltage spikes whichcould adversely affect operation),and reasonable tolerance (tomaintain overall circuit accuracy).The value of the shunt should bechosen as a compromise betweenminimizing power dissipation bymaking the shunt resistancesmaller and improving circuitaccuracy by making it larger andutilizing the full input range ofthe HCPL-7840. Hewlett-Packardrecommends four different shunts

which can be used to senseaverage currents in motor drivesup to 35 A and 35 hp. Table 1shows the maximum current andhorsepower range for each of theLVR-series shunts from Dale.Even higher currents can besensed with lower value shunts

available from vendors such asDale, IRC, and Isotek (Isabellen-huette). When sensing currentslarge enough to cause significantheating of the shunt, the tempera-ture coefficient of the shunt canintroduce nonlinearity due to thesignal dependent temperaturerise of the shunt. Using a heatsink for the shunt or using a

shunt with a lower tempco canhelp minimize this effect. The

Application Note 1078,Design-

ing with Hewlett-PackardIsolation Amplifiers, containsadditional information ondesigning with current shunts.

The recommended method forconnecting the isolation amplifierto the shunt resistor is shown inFigure 23. Pin 2 (VIN+) is con-nected to the positive terminal ofthe shunt resistor, while pin 3(VIN-) is shorted to pin 4 (GND1),

with the power-supply return

path functioning as the sense lineto the negative terminal of thecurrent shunt. This allows asingle pair of wires or PC boardtraces to connect the isolationamplifier circuit to the shuntresistor. In some applications,however, supply currents flowingthrough the power-supply returnpath may cause offset or noiseproblems. In this case, betterperformance may be obtained byconnecting pin 3 to the negative

terminal of the shunt resistorseparate from the power supplyreturn path. When connected this

way, both input pins should bebypassed. Whether two or three

wires are used, it is recom-mended that twisted-pair wire or

very close PC board traces beused to connect the current shuntto the isolation amplifier circuitto minimize electromagneticinterference to the sense signal.

The 68 resistor in series withthe input lead forms a low-passanti-aliasing filter with the inputbypass capacitor with a 200 kHzbandwidth. The resistor performsanother important function as

well; it dampens any ringingwhich might be present in thecircuit formed by the shunt, the

input bypass capacitor, and thewires or traces connecting thetwo. Undamped ringing of the

input circuit near the inputsampling frequency can alias intothe baseband producing whatmight appear to be noise at theoutput of the device. To beeffective, the damping resistorshould be at least 39 .

PC Board Layout

In addition to affecting offset, thelayout of the PC board can alsoaffect the common mode rejec-tion (CMR) performance of the

isolation amplifier, due primarilyto stray capacitive couplingbetween the input and the outputcircuits. To obtain optimal CMRperformance, the layout of theprinted circuit board (PCB)should minimize any stray coup-ling by maintaining the maximumpossible distance between theinput and output sides of thecircuit and ensuring that anyground plane on the PCB doesnot pass directly below theHCPL-7840. Using surface mountcomponents can help achievemany of the PCB objectivesdiscussed in the preceding para-graphs. An example through-holePCB layout illustrating some ofthe more important layoutrecommendations is shown inFigures 25 and 26. See Applica-tion Note 1078,Designing withHewlett-Packard Isolation

Amplifiers, for more information

on PCB layout considerations.

Post-Amplifier Circuit

The recommended applicationcircuit (Figure 23) includes apost-amplifier circuit that servesthree functions: to reference theoutput signal to the desired level(usually ground), to amplify thesignal to appropriate levels, and

8/10/2019 hcpleed7840

11/121-258

to help filter output noise. Theparticular op-amp used in thepost-amp is not critical; however,

it should have low enough offsetand high enough bandwidth andslew rate so that it does notadversely affect circuit perfor-mance. The offset of the op-ampshould be low relative to the out-put offset of the HCPL-7840, orless than about 5 mV.

To maintain overall circuit band-width, the post-amplifier circuitshould have a bandwidth at leasttwice the minimum bandwidth of

the isolation amplifier, or about200 kHz. To obtain a bandwidthof 200 kHz with a gain of 5, theop-amp should have a gain-bandwidth greater than 1 MHz.The post-amplifier circuitincludes a pair of capacitors (C5and C6) that form a single-polelow-pass filter. These capacitorsallow the bandwidth of the post-amp to be adjusted independentlyof the gain and are useful forreducing the output noise from

the isolation amplifier (doublingthe capacitor values halves thecircuit bandwidth). The compo-nent values shown in Figure 23form a differential amplifier witha gain of 5 and a cutoff frequencyof approximately 100 kHz and

were chosen as a compromise

between low noise and fastresponse times. The overallrecommended application circuit

has a bandwidth of 66 kHz, a risetime of 5.2 s and delay to 90%of 8.5s.

The gain-setting resistors in thepost-amp should have a toleranceof 1% or better to ensure adequateCMRR and gain tolerance for theoverall circuit. Resistor networks

with even better ratio tolerancescan be used which offer betterperformance, as well as reducingthe total component count and

board space.

The post-amplifier circuit can beeasily modified to allow forsingle-supply operation. Figure24 shows a schematic for a postamplifier for use in 5 V singlesupply applications. One addi-tional resistor is needed and thegain is decreased to 1 to allowcircuit operation over the fullinput voltage range. See Applica-tion Note 1078,Designing with

Hewlett-Packard IsolationAmplifiers, for more informationon the post-amplifier circuit.

Other Information

As mentioned above, reducing thebandwidth of the post amplifiercircuit reduces the amount ofoutput noise. Figure 21 shows

how the output noise changes asa function of the post-amplifierbandwidth. The post-amplifier

circuit exhibits a first-order low-pass filter characteristic. For thesame filter bandwidth, a higher-order filter can achieve evenbetter attenuation of modulationnoise due to the second-ordernoise shaping of the sigma-deltamodulator. For more informationon the noise characteristics of theHCPL-7840, see Application Note1078,Designing with Hewlett-Packard Isolation Amplifiers.

The HCPL-7840 can also be usedto isolate signals with amplitudeslarger than its recommendedinput range through the use of aresistive voltage divider at itsinput. The only restrictions arethat the impedance of the dividerbe relatively small (less than1 Kso that the input resistance(480 K) and input bias current(0.6 A) do not affect the accuracyof the measurement. An inputbypass capacitor is still required,

although the 68series dampingresistor is not (the resistance ofthe voltage divider provides thesame function). The low passfilter formed by the dividerresistance and the input bypasscapacitor may limit theachievable bandwidth.

Table 1. Current Shunt SummaryMaximum Maximum Maximum

Shunt Power Average Horsepower

Shunt Resistor Part Number Resistance Dissipation Current Range

LVR-3.05-1% 50 m 3 W 3 A 0.8-3.0 hp

LVR-3.02-1% 20 m 3 W 8 A 2.2-8.0 hp

LVR-3.01-1% 10 m 3 W 15 A 4.1-15 hp

LVR-5.005-1% 5 m 5 W 35 A 9.6-35 hp

8/10/2019 hcpleed7840

12/12

VOLTAGEREGULATOR

CLOCKGENERATOR

MODULATOR

ENCODERLED DRIVE

CIRCUITDETECTOR

CIRCUITDECODERAND D/A

FILTER ISO-AMPOUTPUT

VOLTAGEREGULATOR

ISO-AMPINPUT

ISOLATIONBOUNDARY

Figure 22. HCPL-7840 Block Diagram.

0.1 F

+5 V

VOUT

8

7

6

1

3

U2

5

2

4

R1

2.00 K

+15 VC8

0.1 F

0.1 F

-15 V

+ MC34081

R3

10.0 K

HCPL-7840

C4

R410.0 K

C6150 pF

U3

U178L05

IN OUT

C1 C2

0.01F

R5

68

GATE DRIVECIRCUIT

POSITIVEFLOATINGSUPPLY

HV+

HV

+

RSENSE

MOTOR

C5150 pF

0.1F

0.1F

C3

C7

R2

2.00 K

Figure 26. Bottom Layer of PrintedCircuit Board Layout.

TO RSENSE+TO RSENSE

TO VDD1TO VDD2VOUT+VOUT

Figure 25. Top Layer of PrintedCircuit Board Layout.

C3

C2 C4R5

Figure 24. Single-Supply Post-Amplifier Circuit.

0.1 F

+5 V

VOUT

8

7

6

1

3

U2

5

2

4

R1

10.0 K

+5 VC8

0.1 F

+ MC34071

R3

10.0 K

HCPL-7840

C4

R4B20.0 K

C6150 pF

U3

R4A

20.0 K

+5 V

C5150 pF

R2

10.0 K

Figure 23. Recommended Application Circuit.

hcpleed7840

Documents