hc17.15.10.s1t3 super companion chip with audio … mihara 1, hiroki muroga 1, hiroshi doi 1,...

1Copyright c 2005 Toshiba Corporation. All right reserved.1

Super Companion Chip with Audio VisualSuper Companion Chip with Audio Visual

Interface for Cell ProcessorInterface for Cell Processor

Takayuki Mihara 1, Hiroki Muroga 1, Hiroshi Doi 1, Tadashi Yabuta 1,

Yoichiro Iwagami 1, Kenichi Ishii 1, Naohiko Okamoto 1, Kazuki Iwata 1,

Yoshimasa Aoyama 1, Takeshi Takamiya 1, Naoki Sugawa 2

1. Toshiba Corporation

2. Toshiba Microelectronics Corporation

Jun. 25, 2005 22Copyright c 2005 Toshiba Corporation. All right reserved.

OutlineOutline

BackgroundBackground

What is Super Companion Chip(SCC)?What is Super Companion Chip(SCC)?

Processing FlowProcessing Flow

SCC ArchitectureSCC Architecture

Technology and Chip ImplementationTechnology and Chip Implementation

ConclusionConclusion


MotivationMotivation

To provide software based digitalTo provide software based digital

consumer solution for Cell processorconsumer solution for Cell processor

such as Digital TV, Audio Visual Server,such as Digital TV, Audio Visual Server,

etc.etc.

To establish GHz high bandwidthTo establish GHz high bandwidth

connection between Cell and ultra highconnection between Cell and ultra high

speed peripherals speed peripherals onon Super Companion Super Companion

Chip (SCC).Chip (SCC).


Storage

Satellite

Internet

CATV

HDD

HDTV

SDTV

Web, Streaming

Streaming

PC Monitor

HD-DVD

･･･

･･･

･･･

･･･

･･･

Home

Network

DTV

Requirements from MarketRequirements from Market- Multi Tasks Processing Simultaneously -- Multi Tasks Processing Simultaneously -

Key Feature：

Real Time Audio

Video Processing

-Multi Recording

-Time Shift Play

-Multi Screen

Terrestrial


Cell Processor OverviewCell Processor Overview

Power Processor ElementPower Processor Element

(PPE)(PPE)

Synergistic ProcessorSynergistic Processor

Element (SPE)Element (SPE)

Dual XDR DRAM channelsDual XDR DRAM channels

Flexible I/O InterfaceFlexible I/O Interface

Element Interconnect BusElement Interconnect Bus

SPEs

PPE FlexIO

SXU

LS

SXU

LS

SXU

LS

SXU

LS

SXU

LS

SXU

LS

SXU

LS

SXU

LS

EIB

L2 L1 PXUMIC BEI

XIO

SCC

Dual

XDRTM

Cell Processor


Features of Cell ProcessorFeatures of Cell Processor

Resource Management CapabilityResource Management CapabilityReserve Memory & I/O Bandwidth for up to four

tasks.

Isolation FacilityIsolation FacilityEach SPE is isolatable from outside for flexible

secure programming.

Multi OS SupportMulti OS SupportRun multiple OSs simultaneously.

e.g. Linux + Real-time OS


Features of SCCFeatures of SCC

For Real Time ProcessingFor Real Time ProcessingSCC internal bus has the bandwidth reservation capability

for the each resources.

-TDM arbitration

For Tight SecurityFor Tight SecurityThe HW random number generator and several kinds of HW

Encryption/Decryption functions are implemented.

For Multi OS SupportFor Multi OS SupportEvery bus master module have the address space restriction

mechanism.

To prevent the IO resource conflict between OSs.


OutlineOutline








SCC I/O CategorySCC I/O Category

For versatile A/V system For versatile A/V system

-DDR2 DRAM I/F for Video RAM.

-Video output / Audio output.

-Video input / Audio input.

-Digital AV equipment connection I/F

(IEEE1394).

-Digital tuner I/F (TS I/F).

For computer system For computer system

-Standard PC I/F (PCI-Express,PCI,USB2.0).

-High-speed Network I/F (Giga Bit Ethernet).

-Storage device I/F (Parallel ATA).


A-Tuner

D-Tuner

D-Tuner

NTSC

A/D

S,CVBS+Audio

Modem TELA-Tuner

5GB/s

V-DAC/HDMI HD Output

A-DAC

V-DAC

(D4, S2,CVBS)

2ch

S/PDIF

FlexIO

IEEE1394

A/V functions in SCCA/V functions in SCC

DDRI2 DRAM 2.6GB/s

5MB/s

555MB/s

50MB/s

27MB/s

Cell ProcessorXDR-DRAM

25.6GB/s

XIO

FlexIO

♪ ♪ ♪♪♪♪

SD Output

A/V

SCC

PC

5GB/s


5GB/s 5GB/s

PCI expressx4 LinkGiga Bit Ether 1Port

FlexIO

Cell ProcessorXDR-DRAM

25.6GB/s

XIO

DDRI2 DRAM 2.6GB/s

2.0GB/s

133MB/s

60MB/s

250MB/s

PCI 4 slot133MB/s

AC’97 Audio/Codec133MB/s

ATA 133 2 Ports

USB2.0 4 Ports

FlexIO

PC

AV

FlexIO

SCC

Computer peripheral functions in SCCComputer peripheral functions in SCC


OutlineOutline








TS Input Multi2

Descramble

Audio Dec

Video Dec I/P Scaling α Correction

Scaling α Correction

Character

Audio

Output

Video

Output

VCR

Output

NTSC En

or HDMI

NTSC En

DAC

From BS Digital

Tuner

HDDScramble

Demux

Descramble

Audio/Visual Processing StepsAudio/Visual Processing Steps< Digital Broadcasting >< Digital Broadcasting >

1.

6.7.

4.

3.2.

5.


TS I/F

DMAC DDR2

ATA I/F

FlexIO Cell XDR FlexIO

Video Output

Audio Output

FlexIO Cell XDR FlexIO

Taking digital broadcasting and Outputting A/V data

with time shift function.

Audio/Visual data flowAudio/Visual data flow

:Data Transfer in SCC

:SCC from/to Cell

2.

5.

6.

6.

7.

3.

4.

1.


Data Processing FlowData Processing Flow

Digital Tuner

1. Transferring the data from TS I/F to

Cell Processor.

2. Processing the data with XDR.

3. Recording the data on HDD.

4. Reading the data on HDD.

5. Processing the data with XDR.

6. Transferring the data from XDR

to DDR2, Audio I/F.

7. Transferring the data fromDDR2

to Video out I/F.


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FlexIOFlexIOMBUSMBUS

TBUSTBUS

SBUSSBUSHBUSHBUS

VideoVideo

OutOutDDR2DDR2

PCIPCIPCI-PCI-

expressexpress

DMACDMAC

Internal Bus HierarchyInternal Bus Hierarchy

2.66GB/s2.66GB/s

5.0GB/s5.0GB/s

Real Time

ProcessingBest Effort

Processing

Cell Processor

DMADMAEBUSEBUS I2CI2CPIOPIOSIOSIO TimerTimer

USBUSB ATAATA GbEGbEVideoVideo

InInIEEEIEEE

13941394TS InTS InGBUSCGBUSC

Enc/Enc/

DecDecAudioAudio

OutOutAudioAudio

InIn

GBUS


Key Architecture (1/2)Key Architecture (1/2)

Internal Bus ArchitectureInternal Bus ArchitectureQuality of Service (QoS)

-Bandwidth allocation by bus arbitration

mechanism.(with priority in every cycle. TDM .)

Hierarchical Architecture

-Dividing the bus according to the required

features.

Real time bus and Best effort.

DDR2 memory interfaceDDR2 memory interfaceDedicated DMA controller

-For streaming data.


Key Architecture (2/2)Key Architecture (2/2)

Other FeaturesOther FeaturesVirtual Channel Mechanism

To avoid blocking for data flow.

Multiple thread mechanism

Multi/Single threads are alternative.

Pipelined data processing

Data ordering mechanism

VC0

VC1

Stuck or Long Latency

Legacy I/O traffic

Video Data traffic


FlexIOFlexIO controller controller

•Virtual Channel/Thread

correspond to Cell

functionality

Master Path : 8

Slave Path : 4

•Priority Control


Dedicated DMA controllerDedicated DMA controller< For DDR2 memory >< For DDR2 memory >

•High bandwidth

XDR DDR2

DDR2 XDR

•4 Virtual Channel(thread)

•Multi/Single threads


Requirement vs. BandwidthRequirement vs. Bandwidth< MBUS, SBUS, HBUS >< MBUS, SBUS, HBUS >

The each maximum bus bandwidth(2.66GByte/s) is sufficient

for the every required module bandwidth.


Bandwidth Allocation ResultsBandwidth Allocation Results< TBUS >< TBUS >

The bandwidth allocation mechanism can satisfy the BUS

requirement from each module/bus bridge.

2.66GByte/S

Adjusting to the

optimized bandwidth.


OutlineOutline








Chip PhotoChip Photo

ProcessProcess

90nm CMOS Process

7 Layer Cu

FrequencyFrequency

-333MHz

PackagePackage

PBGA[FC],1385pin,

40mm□,1mm pitch

Chip SizeChip Size

12.71mm x 12.71mm

VDD

Core: 1.2V

I/O: Multiple voltages for

various peripherals


OutlineOutline









Super Companion Chip for Super Companion Chip for ““CellCell””

processor system has been successfullyprocessor system has been successfully

developed.developed.

Both rich audio visual featuresBoth rich audio visual features

supporting HD and PC I/O features aresupporting HD and PC I/O features are

integrated on the chip.integrated on the chip.

Simultaneous 48 MPEG-2 SD streamSimultaneous 48 MPEG-2 SD stream

decoding has been demonstrated bydecoding has been demonstrated by

utilizing utilizing SCCSCC’’ss high bandwidth bus with high bandwidth bus with

QoSQoS capability. capability.

hc17.15.10.s1t3 super companion chip with audio … mihara 1, hiroki muroga 1, hiroshi doi 1,...

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