Hardware/Software Co-designHardware/Software Co-designDesign of Hardware/Software Design of Hardware/Software

SystemsSystemsA Class Presentation for VLSI Course by :A Class Presentation for VLSI Course by :

Akbar SharifiAkbar Sharifi

Based on the work presented in :Based on the work presented in :PROCEEDINGS OF THE IEEEPROCEEDINGS OF THE IEEE

19971997GIOVANNI DE MICHELI, FELLOW IEEEGIOVANNI DE MICHELI, FELLOW IEEE

RAJESH K.GUPTA, MEMBER, IEEERAJESH K.GUPTA, MEMBER, IEEE------------------------------------------------------------------------------------------------------------------------------------

Some Slides From :Some Slides From :RASSP Education & Facilitation Program RASSP Education & Facilitation Program

Module 14Module 14

OutlineOutline

Typical Co-Design ProcessTypical Co-Design Process Components of HS ProblemsComponents of HS Problems PartitioningPartitioning SchedulingScheduling Co-SimulationCo-Simulation

Typical Co-design ProcessTypical Co-design Process

System Description(Functional)

HW/SWPartitioning

Software Synthesis

Interface Synthesis

Hardware Synthesis

SystemIntegration

Concurrent processesProgramming languages

Unified representation(Data/control flow)

Instruction set levelHW/SW evaluation

SW HW

FSM-directed graphs

Another HW/SWpartition

Components of the Co-design Components of the Co-design ProblemProblem

Specification of the systemSpecification of the system Hardware/Software PartitioningHardware/Software Partitioning

– Architectural assumptions - type of processor, interface style Architectural assumptions - type of processor, interface style between hardware and software, etc.between hardware and software, etc.

– Partitioning objectives - maximize speedup, latency requirements, Partitioning objectives - maximize speedup, latency requirements, minimize size, cost, etc.minimize size, cost, etc.

– Partitioning strategies - high level partitioning by hand, automated Partitioning strategies - high level partitioning by hand, automated partitioning using various techniques, etc.partitioning using various techniques, etc.

SchedulingScheduling– operation scheduling in hardwareeration scheduling in hardware– Instruction scheduling in compilersInstruction scheduling in compilers– Process scheduling in operating systemsProcess scheduling in operating systems

Modeling the hardware/software system during the design Modeling the hardware/software system during the design processprocess

PartitioningPartitioning

A first order of impact on the cost/performance of A first order of impact on the cost/performance of the final designthe final design

In embedded systems :In embedded systems :– Partition of system functionality into application-specific Partition of system functionality into application-specific

hardware and software executing on processorshardware and software executing on processors

In general purpose computing systems :In general purpose computing systems :– Captured by instruction setCaptured by instruction set

In FPGAs :In FPGAs :– Performing technology mappingPerforming technology mapping

SchedulingScheduling Hardware and software scheduling differ in formulation and

overall goals Assign an execution start time to each task in a set Tasks linked by some relations (e.g. dependencies,

priorities….) Important when several modules in the partition share a

single hw unit Tasks execution requires the use of resources that can be

limited in number Serialization of some task execution

Operation Scheduling in HardwareOperation Scheduling in Hardware The techniques have been implemented in CAD toolsThe techniques have been implemented in CAD tools Operations are assumed to take a known, integer Operations are assumed to take a known, integer

number of cycles to executenumber of cycles to execute Integer linear programmingInteger linear programming The usual goal : minimize the overall execution The usual goal : minimize the overall execution

latencylatency Satisfying the precedence and resource constraintsSatisfying the precedence and resource constraints heuristic approaches:

– list scheduling,

– force directed scheduling

Scheduling

Instruction scheduling in hardware Instruction scheduling in hardware – define a linear order of instructions– instruction selection and register allocation– goal: minimize code size and spills to memory

Coupling between scheduling– Pipelined microprocessors– Pipeline hazard avoidance

Process scheduling in operating systems– SJF– Roundrobin– FIFO

Co-simulationCo-simulation

An HDL (VHDL or Verilog) simulation environment is used An HDL (VHDL or Verilog) simulation environment is used to perform behavioral simulation of the system hardware to perform behavioral simulation of the system hardware processesprocesses

A Software environment (C or C++) is used to develop the A Software environment (C or C++) is used to develop the codecode

SW and HW execute as separate processes linked through SW and HW execute as separate processes linked through UNIX IPC (interprocessor communications) mechanisms UNIX IPC (interprocessor communications) mechanisms (sockets) (sockets)

Verilog Co-simulation ExampleVerilog Co-simulation Example

Verilog HW Simulator

Module: Application specific hardware

HWproc 1

HWproc 2

Module: Bus Interface

Verilog PLI

SWproc 1

SW proc 2

Software processes communicate with hardware simulatorvia UNIX sockets

Verilog PLI (programminglanguage interface) serves astranslator, allowing hardware simulation models to communicate with softwareprocesses.

UNIXsockets

VHDL Co-simulation ExampleVHDL Co-simulation Example

VHDL Simulator

Hardware Model in VHDL:

VHDL Foreign LanguageInterface

Software processes communicate with hardware simulatorvia foreign language interface

Allowing hardware simulation models to “cosimulate” with softwareprocesses.

SWproc 1

SW proc 2

RS232module

VMEmodule

Hardware/Software co-design is the key design Hardware/Software co-design is the key design technology for digital systemstechnology for digital systems

ReferencesReferences

HardwareHardware//Software CoSoftware Co--Design, 1996Design, 1996. (. (CodesCodes//CASHE CASHE '96'96)), Proceedings, Proceedings.., Fourth International Workshop on, Fourth International Workshop on

HardwareHardware//Software Codesign of Embedded Systems, Software Codesign of Embedded Systems, Design Modeling and Design VerificationDesign Modeling and Design VerificationUCSD computer science professor Rajesh Gupta UCSD computer science professor Rajesh Gupta and and CalCal-(-(ITIT))² researcher Ingolf Krueger² researcher Ingolf Krueger