hardware support for acid transactions in...
TRANSCRIPT
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Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas
Hardware Support for ACID Transactions in Persistent Memory
NVMW 2019
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1
!2
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1• Persistent Memory
- Non-volatility over the memory bus- Load/Store interface to persistent data
!2
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1• Persistent Memory
- Non-volatility over the memory bus- Load/Store interface to persistent data
!2
System Crashes
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1• Persistent Memory
- Non-volatility over the memory bus- Load/Store interface to persistent data
• Crash Consistency- Is the persistent state consistent?- Programming Model: ACID Transactions
!2
System Crashes
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1• Persistent Memory
- Non-volatility over the memory bus- Load/Store interface to persistent data
• Crash Consistency- Is the persistent state consistent?- Programming Model: ACID Transactions
!2
System Crashes
“Ensuring failure atomicity for all this computation without failure-atomic transactions is practically infeasible, if not impossible.”
Marathe et al. [HotStorage’17]
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Persistent Memory SystemsL1
LLC
Persistent Memory
L1• Persistent Memory
- Non-volatility over the memory bus- Load/Store interface to persistent data
• Crash Consistency- Is the persistent state consistent?- Programming Model: ACID Transactions
!2
System Crashes
“Ensuring failure atomicity for all this computation without failure-atomic transactions is practically infeasible, if not impossible.”
Marathe et al. [HotStorage’17]
How fast can we support ACID?
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
Atomic Visibility
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
Atomic Visibility
Atomic Durability
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
Atomic Visibility
Atomic Durability
Locks HTMSTM
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
Atomic Visibility
Atomic Durability
Locks HTMSTM
Check-pointing
H/W Logging
S/WLogging
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ACID TransactionsL1
LLC
Persistent Memory
L1
!3
Atomic Visibility
Atomic Durability
Locks HTMSTM
Check-pointing
H/W Logging
S/WLogging
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Atomic Visibility: HTM
!4
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]
!4
L1 Cache
Cache Line
A = 15
R
B = 20
W
11
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]- Version Management: read/write sets in
L1 cache
!4
L1 Cache
Cache Line
A = 15
R
B = 20
W
11
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]- Version Management: read/write sets in
L1 cache- Conflict Detection: piggy back on the
coherence protocol
!4
L1 Cache
Cache Line
A = 15
R
B = 20
W
11
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]- Version Management: read/write sets in
L1 cache- Conflict Detection: piggy back on the
coherence protocol- Commit: make updates non-speculative
!4
L1 Cache
Cache Line
A = 15
R
B = 20
W
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]- Version Management: read/write sets in
L1 cache- Conflict Detection: piggy back on the
coherence protocol- Commit: make updates non-speculative- Abort: invalidate write set
!4
L1 Cache
Cache Line R
B = 20
W
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Atomic Visibility: HTM
• Commercial HTMs [Intel, IBM]- Version Management: read/write sets in
L1 cache- Conflict Detection: piggy back on the
coherence protocol- Commit: make updates non-speculative- Abort: invalidate write set
!4
L1 Cache
Cache Line R
B = 20
W
Write-sets in commercial HTMs limited by the size of the L1 cache.
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Atomic Durability: Logging
!5
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Atomic Durability: Logging
• Logging for durability [Doshi’16, Joshi’17, Shin’17, Ogleari’18]
!5
Persistent Memory
In-place Values
A = 10B = 20C = 30
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Atomic Durability: Logging
• Logging for durability [Doshi’16, Joshi’17, Shin’17, Ogleari’18]- Write a log entry for every update
!5
Persistent Memory
In-place Values
A = 10B = 20C = 30
Transaction Log
A = 15B = 25
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Atomic Durability: Logging
• Logging for durability [Doshi’16, Joshi’17, Shin’17, Ogleari’18]- Write a log entry for every update- Commit: Update the values in-place
!5
Persistent Memory
In-place Values
A = 15B = 25C = 30
Transaction Log
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Atomic Durability: Logging
• Logging for durability [Doshi’16, Joshi’17, Shin’17, Ogleari’18]- Write a log entry for every update- Commit: Update the values in-place- Abort: Undo any in-place updates
!5
Persistent Memory
In-place Values
A = 15B = 25C = 30
Transaction Log
A = 10B = 20
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Atomic Durability: Logging
• Logging for durability [Doshi’16, Joshi’17, Shin’17, Ogleari’18]- Write a log entry for every update- Commit: Update the values in-place- Abort: Undo any in-place updates
!5
Persistent Memory
In-place Values
A = 15B = 25C = 30
Transaction Log
A = 10B = 20
In-place updates in the critical path of commit High memory write bandwidth requirement
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ACID = HTM + Logging
Goals:- Support fast commits - Minimise memory bandwidth consumption- Extend the supported transaction size- Maintain the simplicity of commercial HTMs
!6
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DHTM: Durable Hardware Transactional Memory
L1
LLC
Persistent Memory
L1
!7
Log Writes
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Commercial HTM + Hardware Redo Log
DHTM: Durable Hardware Transactional Memory
L1
LLC
Persistent Memory
L1
!7
Log Writes
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Commercial HTM + Hardware Redo Log- H/W Redo Log + Log Buffer
Reduced memory bandwidth Fast commits
DHTM: Durable Hardware Transactional Memory
L1
LLC
Persistent Memory
L1
!7
Log Writes
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Commercial HTM + Hardware Redo Log- H/W Redo Log + Log Buffer
Reduced memory bandwidth Fast commits
- H/W Log + Sticky State Extended transaction size to the LLC Simplicity of commercial HTM
DHTM: Durable Hardware Transactional Memory
L1
LLC
Persistent Memory
L1
!7
Log Writes
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!8
L1
LLC
Persistent Memory
L1
Log Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
Log Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every storeLog Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every store- multiple stores create multiple log entriesLog Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every store- multiple stores create multiple log entries
• Solution: Log Buffer
Log Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every store- multiple stores create multiple log entries
• Solution: Log Buffer - track cache lines being modified
Log Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every store- multiple stores create multiple log entries
• Solution: Log Buffer - track cache lines being modified- multiple writes coalesced in a log entry
Log Writes
DHTM: Log Buffer
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!8
L1
LLC
Persistent Memory
L1• Redo Log Bandwidth Problem
- write a log entry for every store- multiple stores create multiple log entries
• Solution: Log Buffer - track cache lines being modified- multiple writes coalesced in a log entry - log entry written to persistent memory on eviction
from log buffer
Log Writes
DHTM: Log Buffer
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DHTM: Transaction States
!9
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DHTM: Transaction States
!9
Active
Begin Transaction
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DHTM: Transaction States
!9
Active Commit
Begin Transaction
End Transaction&
Log RecordsPersisted
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DHTM: Transaction States
!9
Active Commit CommitComplete
Begin Transaction
End Transaction&
Log RecordsPersisted
In-place DataPersisted
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DHTM: Transaction States
!9
Active Commit CommitComplete
Abort
Begin Transaction
End Transaction&
Log RecordsPersisted
In-place DataPersisted
Conflict
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DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
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Active
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
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ActiveActive
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
A = 15 1A
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ActiveActive
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
A = 15 1A
A = 15 1AB = 20 1
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ActiveActive
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
A = 15 1A
A = 15 1AB = 20B = 25 11 1
A = 15
B
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ActiveActiveCommit
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
A = 15 1A
A = 15 1AB = 20B = 25 11 1
A = 15
B
B = 25
B = 25
A = 15
Commit
1
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ActiveActiveCommit
DHTM: Commit ExampleL1 Cache
Cache Line R W
Persistent Memory
In-place Values
A = 15B = 25A = 10B = 20C = 30
Transaction Log
A = 10B = 20
State
Log Buffer Begin_Transaction
Write (A=15)
Read (B)
Write (B=25)
End_Transaction
!10
A = 15 1A
A = 15 1AB = 20B = 25 11 1
A = 15
B
B = 25
B = 25
A = 15
CommitA = 15B = 25
Complete
CommitComplete
CommitB = 25
1
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DHTM: Supporting Overflow
!11
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DHTM: Supporting Overflow
• Problems with Overflow:
!11
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DHTM: Supporting Overflow
• Problems with Overflow:- Version Management:
- global operation on write-set on a commit/abort- overhead infeasible in larger caches (beyond L1)
!11
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DHTM: Supporting Overflow
• Problems with Overflow:- Version Management:
- global operation on write-set on a commit/abort- overhead infeasible in larger caches (beyond L1)
- Conflict Detection: - additional metadata to detect conflicts- increased complexity due to NACK based protocols
!11
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DHTM: Supporting Overflow
!12
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DHTM: Supporting Overflow
!12
• Solution
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DHTM: Supporting Overflow
!12
LLC
Persistent Memory
• Solution- Version Management:
- Overflow List
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DHTM: Supporting Overflow
!12
LLC
Persistent Memory
Overflow List
C
AB
• Solution- Version Management:
- Overflow List
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DHTM: Supporting Overflow
!12
LLC
Persistent Memory
Overflow List
C
AB
• Solution- Version Management:
- Overflow List
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DHTM: Supporting Overflow
!12
LLC
Persistent Memory
Overflow List
C
AB
• Solution- Version Management:
- Overflow List- Conflict Detection:
- maintain sticky state on overflow (similar to LogTM)
- avoid NACK by restricting overflow to LLC
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Evaluation
• System Configuration- We evaluate an 8-core machine with a 2-level cache hierarchy- HTM’s implement (first) writer wins conflict resolution policy
!13
Atomic Visibility Atomic Durability
ATOM Locks Hardware Undo Log
LogTM+ATOM HTM (LogTM) Hardware Undo Log
DHTM HTM Hardware Redo Log (Log Buffer)
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Evaluation
!14
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Evaluation
!14
1
1.25
1.5
1.75
2
queue hash sdg sps btree rbtree gmean
ATOM LogTM+ATOM DHTM
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Evaluation
!14
1
1.25
1.5
1.75
2
queue hash sdg sps btree rbtree gmean
ATOM LogTM+ATOM DHTM
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Evaluation
!14
1
1.25
1.5
1.75
2
queue hash sdg sps btree rbtree gmean
ATOM LogTM+ATOM DHTM
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Evaluation
!14
1
1.25
1.5
1.75
2
queue hash sdg sps btree rbtree gmean
ATOM LogTM+ATOM DHTM
26%
![Page 68: Hardware Support for ACID Transactions in …nvmw.ucsd.edu/nvmw2019-program/unzip/current/nvmw2019...B = 20 W Write-sets in commercial HTMs limited by the size of the L1 cache. Atomic](https://reader030.vdocuments.us/reader030/viewer/2022040912/5e87c22347d25d04a24aae5d/html5/thumbnails/68.jpg)
Evaluation
!14
1
1.25
1.5
1.75
2
queue hash sdg sps btree rbtree gmean
ATOM LogTM+ATOM DHTM
17%
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Conclusion
• Persistent memory systems require crash consistency• ACID Transactions: widely understood crash consistency mechanism
• DHTM: ACID transactions in hardware- Atomic Visibility: commercial HTM- Atomic Durability: bandwidth optimized hardware redo log- Leverage hardware logging to extend transaction size unto LLC
!15
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Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas
Hardware Support for ACID Transactions in Persistent Memory
NVMW 2019