hardware software codesign of embedded...
TRANSCRIPT
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Hardware Software Codesign of Embedded System
CPSC689-602
Rabi Mahapatra
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Mahapatra - Texas A&M - Spring 04 2
Today’s topics
• Course Organization• Introduction to HS-CODES• Codesign Motivation• Some Issues on Codesign of Embedded
System
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Mahapatra - Texas A&M - Spring 04 3
Course Organization
Lectures: HRBB 104, TR 3:55 - 5:10 PM
Laboratory: HRBB 218, TBDInstructor’s office Hours: By appointmentContact: [email protected], 5-5787
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Mahapatra - Texas A&M - Spring 04 4
Course organization: Gradings
Projects: 70% Seminar/Term paper/Assignment: 30%Labs: Team work Seminar/Term papers/Project: Individual or Team of
two students
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Mahapatra - Texas A&M - Spring 04 5
Course policies
• Required to access the course web page for relevant info during the semester
• Class attendance is required • use emails for effective communication
with Instructor• all assigned papers are required materials• follow lab and univ rules
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Mahapatra - Texas A&M - Spring 04 6
Topics to be covered(order and details may change)
1. Codesign overview2. Models and methodologies of system design3. Hardware software partitioning and scheduling4. Cosimulation, synthesis and verifications5. Architecture mapping, HW-SW Interfaces and
Reconfigurable computing6. System on Chip (SoC) and IP cores7. Low-Power RT Embedded Systems8. On-chip Networking 9. Software for Embedded Systems10. Sensor Networks
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Mahapatra - Texas A&M - Spring 04 7
Laboratory Activites
• Synopsys’s Design Environment– Cocentric Tools for the class – use of SystemC
• FPGA based design – use of Xilinx’s design environment and devices (VHDL / Verilog)
• Can use Lab for project work• Embedded Systems: PowerPC, StrongARM and
Motorola’s ColdFire• Low-Power measurement setup using LabView tools • Use of tools and language based on choice of projects
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Mahapatra - Texas A&M - Spring 04 8
Texts & References
• G Micheli, R Ernst and W.Wolf, editors, “Readings in Hardware/Software Co-Design”, Morgan Kaufman Publisher, 2002
• Lecture notes: faculty.cs.tamu.edu/rabi/cpsc689/
• Staunstrup and Wolf Ed. “Hardware Software codesign: principles and practice”, Kluwer Publication, 1997 (Reference)
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Mahapatra - Texas A&M - Spring 04 9
Reading assignment
• Giovanni De Micheli and Rajesh Gupta, “Hardware/Software co-design”, IEEE Proceedings, vol. 85, no.3, March 1997, pp. 349-365.
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Mahapatra - Texas A&M - Spring 04 10
Introduction
Digital systems designs consists of hardware components and software programs that execute on the hardware platforms
Hardware-Software Codesign ?
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Mahapatra - Texas A&M - Spring 04 11
Microelectronics trends
• Better device technology– reduced in device sizes– more on chip devices > higher density– higher performances
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Mahapatra - Texas A&M - Spring 04 12
Microelectronics trends
• Higher degree of integration– increased device reliability– inclusion of complex designs
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Mahapatra - Texas A&M - Spring 04 13
Digital Systems
Judged by its objectives in application domain• Performance• Design and Manufacturing cost• Ease of Programmability
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Mahapatra - Texas A&M - Spring 04 14
Digital Systems
Judged by its objectives in application domain• Performance• Design and Manufacturing cost• Ease of Programmability
It depends on both the hardware and software components
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Mahapatra - Texas A&M - Spring 04 15
Hardware/Software Codesign
A definition:
Meeting System level objectives by exploiting the synergism of hardware and software
through their concurrent design
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Mahapatra - Texas A&M - Spring 04 16
Concurrent design
Traditional design flow Concurrent (codesign) flowstart
start
SWHW
HW SWDesigned by independentgroups of experts Designed by Same group of
experts with cooperation
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Mahapatra - Texas A&M - Spring 04 17
Codesign motivation
Trend toward smaller mask-level geometries leads to:• Higher integration and cost of fabrication.
• Amortize hardware design over large volume productions
Suggestion:Use software as a means of differentiating products based on the same hardware platform.
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Mahapatra - Texas A&M - Spring 04 18
Story of IP cores
What are these IP Cores?
Predesigned, preverified silicon circuit block, usually containing 5000 gates, that can be used in building larger application on a semiconductor chip.
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Mahapatra - Texas A&M - Spring 04 19
Story of IP cores
Complex macro cells implementing instruction set processors (ISP) are available as cores
• Hardware (core)• Software (micro kernels)
Are viewed as intellectual property
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Mahapatra - Texas A&M - Spring 04 20
IP core reuse
• Cores are standardized for reuse as system building blocksRationale: leveraging the existing software layers including OS and applications in ES
Results:1. Customized VLSI chip with better area/ performance/
power trade-offs2. Systems on Silicon
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Mahapatra - Texas A&M - Spring 04 21
Hardware Programmability
Traditionally • Hardware used to be configured at the time of
manufacturing • Software is variant at run time
The Field Programmable Gate Arrays (FPGA)has blurred this distinction.
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Mahapatra - Texas A&M - Spring 04 22
FPGAs
• FPGA circuits can be configured on-the-fly to implement a specific software function with better performance than on microprocessor.
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Mahapatra - Texas A&M - Spring 04 23
FPGAs
• FPGA circuits can be configured on-the-fly to implement a specific software function with better performance than on microprocessor.
• FPGA can be reprogrammed to perform another specific function without changing the underlying hardware.
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Mahapatra - Texas A&M - Spring 04 24
FPGAs
• FPGA circuits can be configured on-the-fly to implement a specific software function with better performance than on microprocessor.
• FPGA can be reprogrammed to perform another specific function without changing the underlying hardware.
This flexibility opens new applications of digital circuits.
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Mahapatra - Texas A&M - Spring 04 25
Why codesign?
• Reduce time to market
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Mahapatra - Texas A&M - Spring 04 26
Why codesign?
• Reduce time to market• Achieve better design
• Explore alternative designs• Good design can be found by balancing the HW/SW
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Mahapatra - Texas A&M - Spring 04 27
Why codesign?
• Reduce time to market• Achieve better design
• Explore alternative designs• Good design can be found by balancing the HW/SW
• To meet strict design constraint• power, size, timing, and performance trade-offs• safety and reliability• system on chip
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Mahapatra - Texas A&M - Spring 04 28
Distinguishing features of digital system
• Interrelated criteria for a system designHardwareTechnology
Level ofIntegration
Degree of Programmability
ApplicationDomain
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Mahapatra - Texas A&M - Spring 04 29
Application Domains
• General purpose computing system• usually self contained and with peripherals• Information processing systems
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Mahapatra - Texas A&M - Spring 04 30
Application Domains
• General purpose computing system• usually self contained and with peripherals• Information processing systems
• Dedicated control system• part of the whole system, Ex: digital controller in a
manufacturing plant• also, known as embedded systems
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Mahapatra - Texas A&M - Spring 04 31
Embedded System
• Uses a computer to perform certain functions • Conceived with specific application in mind
• examples: dash controller in automobiles, remote controller for robots, answering machines, etc.
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Mahapatra - Texas A&M - Spring 04 32
Embedded Systems
• Uses a computer to perform certain functions • Conceived with specific application in mind
• examples: dash controller in automobiles, remote controller for robots, answering machines, etc.
• User has limited access to system programming• system is provided with system software during
manufacturing• not used as a computer
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Mahapatra - Texas A&M - Spring 04 33
Degree of Programmability
Most digital systems are programmed by some software programs for functionality.
Two important issues related to programming:• who has the access to programming?• Level at which programming is performed.
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Mahapatra - Texas A&M - Spring 04 34
Degree of Programmability: Accessibility
Understand the role of:End users, application developers, system
integrator and component manufacturers.
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Mahapatra - Texas A&M - Spring 04 35
Degree of Programmability: Accessibility
Understand the role of:End users, application developers, system
integrator and component manufacturers.
Application Developer: System to be retargetable.
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Mahapatra - Texas A&M - Spring 04 36
Degree of Programmability: Accessibility
Understand the role of:End users, application developers, system
integrator and component manufacturers.
Application Developer: System to be retargetable.System Integrator: Ensure compatibility of system
components
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Mahapatra - Texas A&M - Spring 04 37
Degree of Programmability: Accessibility
Understand the role of:End users, application developers, system
integrator and component manufacturers.
Application Developer: System to be retargetable.System Integrator: Ensure compatibility of system
componentsComponent Manufactures: Concerned with maximizing
product reuse
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Mahapatra - Texas A&M - Spring 04 38
Degree of Programmability
Example 1: Personal computerEnd User: Limited to application levelApplication Dev.: Language tools, Operating System, high-
level programming environment (off the self components)Component Manf.: Drive by bus standards, protocols etc.
Observe that: coalescing the system components due to higher chip densityResult: Few but more versatile system hardware components
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Mahapatra - Texas A&M - Spring 04 39
Example 2.
Embedded Systems• End user: Limited access to programming• Most software is already provided
by system integrator who could be application developer too!
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Mahapatra - Texas A&M - Spring 04 40
Level of Programmability
• Systems can be programmed at application, instruction and hardware levels
• Application Level: Allows users to specify “option of functionality” using special language.
• Example: Programming VCR or automated steering control of a ship
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Mahapatra - Texas A&M - Spring 04 41
Level of Programmability
• Instruction-level programmability– Most common ways with ISA processors or
DSP • compilers are used in case of computers• In case of embedded systems, ISA is NOT
visible
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Mahapatra - Texas A&M - Spring 04 42
Level of programmability
• Hardware level programmability⇓
Example: Microprogramming (determine the behavior of control unit by microprogram)
• Emulating another architecture by alternation of µp• Some DSP implementations too• Never in RISC or ISA processors
configuring the hardware (after manufacturing) in the desired way.
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Mahapatra - Texas A&M - Spring 04 43
Programmability
Microprogramming Vs.. Reconfigurability
Microprogram allows to reconfigure the control unitwhereas Reconfigurable system can modify both
datapath and controller.
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Mahapatra - Texas A&M - Spring 04 44
Programmability
Microprogramming Vs.. Reconfigurability
Microprogram allows reconfigure the control unitversus Reconfigurable system can modify both
datapath and controller.
Reconfigurability increases usabilitybut not the performance of a system.
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Mahapatra - Texas A&M - Spring 04 45
Performance and Programmability
• General computing applications: use of superscalar RISC architecture to improve the performance (instruction level programming)
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Mahapatra - Texas A&M - Spring 04 46
Performance and Programmability
• General computing applications: use of superscalar RISC architecture to improve the performance (instruction level programming)
• Dedicated Applications: Use of application specific designs (ASICs) for power and performance
• Neither reusable nor cheap!
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Performance and Programmability
• General computing applications: use of superscalar RISC architecture to improve the performance (instruction level programming)
• Dedicated Applications: Use of application specific designs (ASICs) for power and performance
• Neither reusable nor cheap!
What if ASICs with embedded cores?
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Performance and Programmability
• Any other solutions?How about replacing the standard processors by application specific processors that can be programmed at instruction level (ASIPs).
• Better power-performance than standard processor ?• Worse than ASICs
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Programmability and Cost:ASIPs
• Cost can typically be amortized over larger volume than on ASICs (with multiple applications using ASIPs).
• Ease to update the products and engineering changes through programming the HW,
• However, includes compiler as additional cost
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Hardware Technology
• Choice of hardware to implement the design affects the performance and cost
• VLSI technology (CMOS or bipolar, scale of integration and feature size etc.) can affect the performance and cost.
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Hardware Technology: FPGAs
• Performance is an order of magnitude less than corresponding non-programmable technology with comparable mask size
• For high volume production, these are more expensive than ASICs
• Power Issues?
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Level of Integration
• Integration leads to reducing number of parts, which means, increased reliability, reduced power and higher performances
• But it increases the chip size (cost) and makes debugging more challenging.
• Standard components for SoC are cores, memory, sensors and actuators.
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Embedded System Design Objective
• Embedded systems:control systems: reactive, real-time♦function & size: micro controller to high
throughput data-processor• requires leveraging the components and cores of
microprocessors
• reliability, availability and safety are vital• use of formal verification to check the correctness• may use redundancy
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Codesign of ISA
• ISA is fundamental to digital system design• An instruction set permits concurrent design of HW
and compiler developments• Good ISA design is critical in achieving system
usability across applications• Goal of codesign in ISP development is to optimize
HW utilization by application & OS
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Codesign of ISA
• For high performance in ES, selection of instruction set that matches the application is very important
• replace the standard core by ASIP
• ASIPs are more flexible than ASICs but less than ISP
• ASIP performs better than ISP
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Challenges with ASIP
• Compatibility requirement is less important • Goal: support specific instruction mixes
• CAD of compiler is partly solved problem
Price of the flexibility in choosing mixed instructionset is to develop the application specific compiler.
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Typical codesign process
SystemDescription
HW/SWPartitioning
Softwaresynthesis
Interfacesynthesis
Hardwaresynthesis
Systemintegration
Modeling
Unified representation
Instruction set levelHW/SW evaluation
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Steps in Codesign
HW-SW system involves• specification• modeling• design space exploration and partitioning• synthesis and optimization• validation• implementation
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Steps in codesign
Specification• List the functions of a system that describe the
behavior of an abstraction clearly without ambiguity.
Modeling:• Process of conceptualizing and refining the
specifications, and producing a hardware and software model.
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Modeling style
• Homogeneous: a modeling language or a graphical formalism for presentation
• partitioning problem used by the designer
• Heterogeneous: multiple presentations• partitioning is specified by the models
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Steps in codesign
Validation:Process of achieving a reasonable level of confidence that the system will work as designed.
• Takes different flavors per application domain: cosimulation for performance and correctness
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Steps in codesign
Implementation:Physical realization of the hardware (through synthesis) and of executable software (through compilation).
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Partitioning and Scheduling (where and when)
• A hardware/software partitioning represents a physical partition of system functionality into application-specific hardware and software.
• Scheduling is to assign an execution start time to each task in a set, where tasks are linked by some relations.
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Summary:Research areas in codesign
• Languages• Architectural exploration tools• Algorithms for partitioning• Scheduling• SW, HW and interface Synthesis• Verification and Testing