hardware-in-the-loop testbed

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Hardware-in-the- Loop Testbed Team 186

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Hardware-in-the-Loop Testbed. Team 186. Project Collaborators. Team Members: Aaron Eaddy – EE Ken Gobin – EE/COMPE Douglas Pence – ENGR PHYS/EE Team Advisor/Sponsor: Sung Yeul Park – Assistant Professor. Outline. Background Components: Microcontroller Interface circuit - PowerPoint PPT Presentation

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Page 1: Hardware-in-the-Loop Testbed

Hardware-in-the-Loop Testbed

Team 186

Page 2: Hardware-in-the-Loop Testbed

Project Collaborators• Team Members:

o Aaron Eaddy – EEo Ken Gobin – EE/COMPEo Douglas Pence – ENGR PHYS/EE

• Team Advisor/Sponsor:o Sung Yeul Park – Assistant Professor

Page 3: Hardware-in-the-Loop Testbed

Outline• Background• Components:

o Microcontrollero Interface circuito Sensor circuits

• Design Updates• Circuitry• Timeline• Budget

Page 4: Hardware-in-the-Loop Testbed

Background• Hardware-in-the-Loop:

o A simulation technique that is used in the development and testing of complex real-time embedded system designs.

o Benefits:• Function tests are able to be done at an early stage of development.• Laboratory tests are cheaper, more flexible and highly controllable.• No potential major risk of physically damaging test failures.• Tests are easy to reproduce and provide highly consistent results.

• Improve battery operation and monitoring• State of Health• State of Charge• Remaining useful life• Voltage, current, and temperature

Page 5: Hardware-in-the-Loop Testbed

Components

Page 6: Hardware-in-the-Loop Testbed

Design UpdatesInitial Design:• TI ezDSP® F28335

o 6 data/address lines, 59 GPIO, ADCo MATLAB® Simulink, Code Composer Studio®

Updated Design – Rev 1:• dSPACE® RTI-1104

o ADC ports, PWM CP-18 connector, embedded microcontrollero MATLAB® Simulink software for digital signal processing and ease-of-use displayo Removed CCS as an “extra” middle software process. Less complicated and more robust.

Updated Design – Rev 2:o Changed from ‘8’-channel design to hybrid ‘4+2’-channel designo Changed from 1 to 2 PCB design – isolate analog from digital and provide safety barriero Simplified GPIO requirements with PWM MUX selecto Added scaling, filtering and digital isolator

Page 7: Hardware-in-the-Loop Testbed

dSPACE® Microcontroller

dSPACE® RTI-1104 dSPACE® ControlDesk

Page 8: Hardware-in-the-Loop Testbed

dSPACE® Limitations• Maximum 8 ADC channels• Maximum of 10-Volt ADC processing signal limit• Maximum of 5-Volt system hardware limit

• Main reason for switching from ‘8’-channel design to ‘4+2’-channel design was related to these limitations, specifically the 8 ADC channel hardware limitation.

Page 9: Hardware-in-the-Loop Testbed

Sensors and Circuits• Voltage Sensor• Current Sensor

o Internal Impedance of each Cell.

• Temperature Sensoro Ambiento Battery Surface

• Amplificationo Integration with ADC

• Scaling for Multiple Cells• Requirements

o 30Vo 4 Cells

• Integration

Page 10: Hardware-in-the-Loop Testbed

Voltage Sensing Circuit

Page 11: Hardware-in-the-Loop Testbed

Current Sensor

Page 12: Hardware-in-the-Loop Testbed

Current Sensing Circuit

Page 13: Hardware-in-the-Loop Testbed

Temperature Sensing Circuit

Page 14: Hardware-in-the-Loop Testbed

Interface Circuit

Page 15: Hardware-in-the-Loop Testbed

Printed Circuit Board Design

Page 16: Hardware-in-the-Loop Testbed

TimelineResearch Item

Jan Feb MarApr

3 4 1 2 3 4 1 2 3 4

Design

Schematics + Part List x x x

PCB Layout x x x x x x x x

Parts Order x x x

PCB Order x x

Board Assembly x x

Board Testing

Hardware x x

DSP x x

Power Test x x

Page 17: Hardware-in-the-Loop Testbed

Budget• Total Budget $1,000• Current Expenditure Estimate:

o Temperature Sensors and Initial Parts - $156o PCB Order - $198o Additional Parts and Expandable Testing Components - $492

• Budget Surplus Estimate $154

Page 18: Hardware-in-the-Loop Testbed

Questions

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