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UNU/IISTInternational Institute forSoftware Technology

UNU/IIST Report No. 244

Hardware/Software Interface Design

Chen Chang and He Jifeng

October 2001


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UNU/IIST and UNU/IIST Reports

UNU/IIST (United Nations University International Institute for Software Technology) is a Research and TrainingCentre of the United Nations University (UNU). It is based in Macau, and was founded in 1991. It started oper-

ations in July 1992. UNU/IIST is jointly funded by the Governor of Macau and the governments of the Peoples

Republic of China and Portugal through a contribution to the UNU Endownment Fund. As well as providing two-

thirds of the endownment fund, the Macau authorities also supply UNU/IIST with its office premises and furnitureand subsidise fellow accommodation.

The mission ofUNU/IIST is to assist developing countries in the application and development of software tech-nology.

UNU/IIST contributes through its programmatic activities:

1. Advanced development projects, in which software techniques supported by tools are applied,

2. Research projects, in which new techniques for software development are investigated,

3. Curriculum development projects, in which courses of software technology for universities in developing

countries are developed,

4. University development projects, which complement the curriculum development projects by aiming tostrengthen all aspects of computer science teaching in universities in developing countries,

5. Courses, which typically teach advanced software development techniques,

6. Events, in which conferences and workshops are organised or supported by UNU/IIST, and

7. Dissemination, in which UNU/IIST regularly distributes to developing countries information on interna-tional progress of software technology.

Fellows, who are young scientists and engineers from developing countries, are invited to actively participate in

all these projects. By doing the projects they are trained.

At present, the technical focus of UNU/IIST is on formal methods for software development. UNU/IIST is aninternationally recognised center in the area of formal methods. However, no software technique is universally

applicable. We are prepared to choose complementary techniques for our projects, if necessary.

UNU/IIST produces a report series. Reports are either Research R , Technical T , Compendia C or Adminis-

trative A . They are records ofUNU/IIST activities and research and development achievements. Many of thereports are also published in conference proceedings and journals.

Please write to UNU/IIST at P.O. Box 3058, Macau or visit UNU/IIST home page: http://www.iist.unu.edu , ifyou would like to know more about UNU/IIST and its report series.

Zhou Chaochen, Director 01.8.1997 31.7.2003


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UNU/IISTInternational Institute forSoftware Technology

P.O. Box 3058

Macau

Hardware/Software Interface Design

Chen Chang and He Jifeng

Abstract

Hardware/Software Interface plays an important role in co-design of the embedded computer system. It

links the software part and the hardware part of the system. The design process supports software inter-

face implementation and hardware interface synthesis. This report shows how the hardware and software

interfaces can be implemented by using bus extended technology in embedded computer system, which

includes the primitive interface, the synchronous interface and the data communication protocol between

the hardware and the software.


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Chen Chang is a Fellow of UNU/IIST, on leave form the Department of Computer Science and Technol-

ogy, East China Normal University, Shanghai, where he is a senior engineer. E-mail: [email protected]

He Jifeng is a Senior Research Fellow of UNU/IIST, on leave of absence from East China Normal Uni-versity, Shanghai, where he is a professor. His research interest lies in the sound methods of specification

of computer system, communications, application and standards, and the techniques for designing and

implementing those specifications in software and/or hardware, with high reliability and at low cost.

E-mail: [email protected]

Copyright c

2002 by UNU/IIST, Chen Chang and He Jifeng


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Contents i

Contents

1 Introduction 1

2 Bus Extended Technology 2

3 Primitive Interface Design 23.1 Input Interface for Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.2 Output Interface for Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.3 Inout Interface for Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Synchronous Interface design 8

4.1 Input Interface for Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Output Interface for Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Hand Shaking Protocol for Embedded Computer System 12

5.1 Hand Shaking Protocol for Hardware and Software Components . . . . . . . . . . . . . 12

5.2 The Synchronous Protocol between Processor and Co-processor . . . . . . . . . . . . . 13

6 Conclusion 14

Report No. 244, October 2001 UNU/IIST, P.O. Box 3058, Macau


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Introduction 1

1 Introduction

Hardware/Software Co-design technique supports the simultaneous design of both hardware and soft-

ware to implement a desired function. It has widely been used in design of Embedded Computer Sys-

tem(ECS). With hardware and software co-design methodology, a system specification is partitioned intohardware and software parts according to the system architecture.

software

implementation Interface

SW/HW

systhesis

specification

HW/SW patation

hardware

Intergration and test

Figure 1: Hardware/Software Co-design Partition

In this vertical partition processing, the formal method [1] can be used for ensuring the system de-

sign correct. Hardware/Software Interface links the software part and the hardware part in the system.

Hardware/Software Interface design includes software interface implementation and hardware interface

synthesis.

Embedded Computer System usually requires high performance at low cost. To meet such requirements

in application, powerful chips, such as Micro-Processors (MP), Micro-controllers (MC) and Digital Sig-

nal Processors (DSP), and high level programming languages are used to facilitate the software design.

Meanwhile, Hardware Description Languages (HDL) are adopted to improve the efficiency in hardware

design,

Bus is used for dispatching information in computers, through which address, data and control messages

all can be transmitted. The relationship of these signals is based on the architecture of the processor in

system. Use of bus technology in design of the hardware/software interface of embedded systems can

reduce the link number of wires and devices, and make the system easy to be extended.

This paper shows how the hardware and software interfaces can be implemented using bus extendedtechnology, and discusses in detail the primitive interface, the synchronous interface and the data com-

munication protocol between the hardware and the software. The reminder of this paper is organized as

follows. Section 2 briefly describes the Bus extended technology used in the communication interface

design. Section 3 presents the primitive hardware/software interfaces. Section 4 deals with the design of

the synchronous interface. Section 5 gives the examples of the data communication interface design.



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2 Bus Extended Technology

2 Bus Extended Technology

A standard Bus is composed of the data Bus, the address Bus and the control Bus. The Bus width is

determined by the processor architecture. The data Bus transmits data messages and normally its width

is 8Bit, 16Bit or 32Bit. The address Bus transmits address messages and its width determines the access

space of processor. The control Bus transmits system control signals.

Reading and writing are two primitive functions in the Bus. The reading protocol sees figure 2 and the

writing protocol sees figure 3.

WR

RD

dataBus

addrBus

Figure 2: The reading protocol

WR

RD

dataBus

addrBus

Figure 3: The writing protocol

In the reading and writing protocol, a specific address is first sent through the address Bus to identify the

location where the data is fetched from or is stored to. Then the data is present in the data Bus and the

control signal or in the control Bus. When the signal is in place, the processor reads the

data from the data Bus. When the signal

is valid, the data is output from the processor to the data

Bus. However,

and

can not be valid at the same time. When

and

both are absent, the

Bus is in the

state.

We use the following notations to represent the reading and writing functions in the later discussion.

reads a data into a variable form the channel .

writes the value of to the channel .

where the channel is selected by the Bus address, and the number of the channels available for commu-

nication is determined by the width of the address Bus.

3 Primitive Interface Design

The primitive interface implements input and output, where the input interface supports the reading

function, and the output interface the writing function.



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Primitive Interface Design 3

3.1 Input Interface for Processor

The input interface for processor is composed of the hardware interface and the software interface.

The behaviour of the hardware interface can be described by a Verilog module

1 define BUSwidth 8 // Width of BUS

2 module Data_input( x, y, g );

3 input [BUSwidth-1:0] x;

4 output [BUSwidth-1:0] y;

5 input g;

6 assign y = (g) ? x : {BUSwidth{1bz}} ;

7 endmodule

In this program, line 1 defines the Bus width. Line 2 introduces the module # % # ' ( 0 % as an input

hardware interface, where the parameter

stands for input,3

for output and4

for control. A digitaldevice % 5 7 - @ % # % 4 # % has the same behaviour as the hardware interface

g

yx

Figure 4: three-state gate

which performs a signal assignment

3 C E

G

4 I Q

The gate has its input wire directly connected to the input source, whose selection is determined by

the address value sent by the software input interface shown below. Its output wire3

and control wire

4are linked to the data Bus and the control Bus respectively. If

4is valid,

3is assigned the value of ,

otherwise3

is equal toQ

(which denotes high impedance).

The software interface reads the data from the hardware interface. It is implemented as a procedure

# % # # U V X

X `, where its value parameters and

identify the selected address and the control

signal, and the result parameterV

is the holder of the incoming message.

# % # # U V X

X ` cE # 7 d 0 @ C E

f

% 7 d 0 @ C E

f

q r

f

V C E # % # d 0 @

f

% 7 d 0 @ C E

f



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To perform a primitive reading function , the application program can invoke the software interface

procedure.

In the multi-input hardware interface, the selection of the input can be implemented in two ways. One is

based on the control signal, see figure 5. The other one is based on the input source, see figure 6.

g1

g2

gn

......

dataBus

y

x1

x2

xn

......

Figure 5: control based input

Busdata

RD

addrBus

selector

xn

x2

x1

xy

g

......

Figure 6: source based input

In figure 5, the multi-input hardware interface is a collection of the three-state gates connected to the

Bus in parallel. As in the case of single three-state gate, the inputs v X w w w X are connected to their input

sources. The control wire4

becomes valid only when both

signal and the corresponding address

are available. The behaviour of this multi-input hardware interface can be modelled by

cE

4

v

3 C E

v f

4

3 C E

f

w w w w w w

4

3 C E

f

4

v

4

w w w

4

3 C E Q

f

where the input message passed to the data Bus is selected by the control signals4

. To avoid interference

between multiple inputs, we must ensure that only one of control signals can be active at any time.

In figure 6, the multi-input hardware interface is built by a three-state gate together with a selector. The

input wires v X w w w X are connected to their corresponding input resource. One of them is selected by

the address and linked to the input wire of the three-state gate. The control wire4

is solely controlled

by the

signal. This multi-input hardware interface can be modelled by the program

cE 3 C E

U # 7 d 0 @ E # 7

v

`

v f

U # 7 d 0 @ E # 7 `

f

w w w w w w

U # 7 d 0 @ E # 7

`

f

U # 7 d 0 @

# 7

v

w w

`

Q

f

G

I Q

where the input message assigned to3

is selected by the address. To avoid interference between multiple

inputs, users must ensure that only one of addresses can be active and must be active at any time.



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The procedure # % # # U V X

X `can also be used to implement the multi-input software interface.

These input interfaces for processor are the typical asynchronous interfaces. They require that the input

data should be ready before the processor executes the reading function.

3.2 Output Interface for Processor

The output interface for processor is composed of the hardware interface and the software interface. The

hardware interface can be described by the Verilog program

1 define BUSwidth 8; // Width of BUS

2 module Data_output( x, y, k );

3 input [BUSwidth-1:0] x;

4 output [BUSwidth-1:0] y;

5 input k ;

6 reg [BUSwidth-1:0] y;

7 always @( k or x or y )

8 begin

9 if (k) y=x; else y=y;

10 end

11 endmodule

A digital device # %

5 has the same behaviour as the hardware interface

k

x

y

Figure 7: Latch

where the output wire3

is directly connected to output destination. The input wire and the control wirel

are linked to the data Bus and the control Bus respectively. Whenl

is valid, the value of propagates

to the output wire 3 , otherwise 3 remains unchanged.

The software interface writes data to the hardware interface, and is implemented by the procedure

# % # 7 % U X X `

# % # 7 % U X X ` cE # 7 d 0 @ C E

f

# % # d 0 @ C E

f

% 7 d 0 @ C E

f

# 3 U

r

`

f

% 7 d 0 @ C E

f



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where the parameter

gives the output message,

delivers the selected address and

outputs a control

signal for writing. The procedure is invoked when an application program wants to perform the writing

function .

For the multi-output interface, the selection of the output in the hardware interface can be implemented

in two ways. One is based on the control signal, see figure 8. The other one is based on the output

destination, see figure 9. In figure 8, the multi-output hardware interface is composed of a collection of

dataBus

k1

k2

kn

...... ......

y1

y2

yn

x

Figure 8: control-based output

dataBus

kWR s

elector

addrBus

......

y1

y2

yn

yx

Figure 9: destination based output

the latches connected to the Bus. As in the case of single latch, each output wire3

is linked to its own

output destination. The control wirel

is valid after both signal and the address become available.

The behaviour of this multi-output hardware interface can be modelled by the multiple assignment

cE 3

v

X 3 X w w w X 3

C E

G

l

v

I 3

v

X

G

l

I 3 X w w w X

G

l

I 3

In figure 9, the multi-output hardware interface is composed of a single latch connected to the Bus. This

kind of the multi-output hardware interface can be modelled by,

cE

U # 7 d 0 @ E # 7

v

`

3

v

U # 7 d 0 @ E # 7 `

3

w w w w w w

U # 7 d 0 @ E # 7

`

3

C E

G

I 3

f

where the output control signal is

. The output message from the data Bus is determined by theaddress. In this interface, at least one of the address must be active at any time.

The multi-output software interface can invoke the procedure # % # 7 % U X X `

to write the data

to the multi-output hardware interface. All these output interfaces for processor are the typical asyn-

chronous output interfaces. As the simplest case, the constraint of using these interfaces is that the

receiver should be ready when the data is output by the processor.



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3.3 Inout Interface for Processor

The primitive inout interface is composed of the hardware interface and the software interface. The

hardware component of the inout interface is made up of the modules # % #

' ( 0 %

and # % # 0 % ( 0 %

defined in the previous sections.


2 wire [BUSwidth-1:0] x1, x2;

3 wire g, k ;

4 reg [BUSwidth-1:0] y2;

5 tri [BUSwidth-1:0] y1;

6 Data_input IO_input( x1, y1, g ); // Input

7 Data_output IO_output( x2, y2, k ); // Output

The structure of the inout interface is shown in figure 10, where the input interface and the output inter-face link to the same data Bus.

Busdata

w

x

y

g

k

Figure 10: inout interface

The software interface interacts with the hardware interface by invoking the procedures # % # # U V X X `

and # % # 7 % U X X `

to perform the reading and writing functions.

The inout interface can only sever as either input interface or output interface (but not both) at any time.

If the reading and the writing occur at the same time, the data Bus and the three-state gate will output to

the same wire. This may damage the circuit when one outputs 1 and the other outputs 0. To exclude

the interference between the input and the output, users are required to maintain the invariant

4

l

E } # @

The multi-inout interface can be built in a very similar way as the multi-input interface and the multi-

output interface. Its hardware component encompasses a number of primitive input and output devices,

all of which are linked to the same Bus. The figure 11 is an example of the multi-inout interface, where

the input source and the output destination is selected by the control signal4

and address.



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8 Synchronous Interface design

dataBus

addrBus

WR

xm

gm...... ..........

g1

x1

y1y2

yn

......y

k

w

Figure 11: an example of the multi-inout

The multi-inout software interface is the same as the primitive inout software interface. The inout in-

terface for processor is asynchronous. Its correct function assumes that the input data has been ready

before it is read by the processor, and that the receiver is willing to input when the data is output by the

processor.

yes


The synchronous interface is used in support of synchronous communication between the software com-

ponent and the hardware component of an embedded system.

In synchronous interface, a flag is introduced to synchronise the parallel execution of its hardware com-ponent and software component, i.e., a communication can occur only after the flag is set indicating both

sender and receiver are ready for it.

The behaviour of a flag

is described by the following Verilog module

1 module Flag( S, R, Q );

2 input S, R ;

3 output Q ;

4 reg Q ;

5 always @ (posedge S or posedge R)6 begin if (R) Q = 1b0; else Q = 1b1; end

7 endmodule

where the flag is set by the positive edge signal from

, and reset by the positive edge signal from

.



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Synchronous Interface design 9

4.1 Input Interface for Processor

The hardware component of the synchronous input interface is made up of the flag and the primitive

input interface.


2 wire [BUSwidth-1:0] x;

3 tri [BUSwidth-1:0] y;

4 wire g, set;

5 reg F;

6 Data_input syn_input( x, y, g ); // Data input

7 Flag synin_flag( set, g, F ); // flag

Its structure is shown below 12. The software component of the synchronous interface inputs data from

g

yBusdata

RD Flag

F

x

R S

Figure 12: synchronous input interface

the hardware component, and is devised as a procedure@ 3 '

7 # U V X

X `, where the parameter

Vis

the holder of the input message, is the selected address and is a control signal for reading. defined

as follows,

@ 3 '

7 # U V X

X ` cE # % }

f

# % # # U V X

X `

f

Here, the program waits for the flag } to be set to indicate availability of an input data on the data Bus.

The reset wire of the flag is linked to the control wire4

, which is driven by the control signal

. The

assignment % 7 d 0 @ C E in the procedure # % # 7 # U V X X ` has the effect of resetting the flag.

The synchronous multi-input interface is also composed of the hardware interface and the software inter-

face. Its hardware component is constructed using a multi-input interface and a flag indicator 13. wherethe input source is selected by the address value.

The software component of the synchronous multi-input interface invokes the procedure@ 3 '

7 # U V X

X `

to read the data from the multi-input hardware interface synchronously.



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Busdata

RD

......

x1

x2

xn

Flag

F

y

addrBus

g

SR

x

Figure 13: synchronous multi-input interface

4.2 Output Interface for Processor

The hardware of the synchronous output interface is made up of the primitive output interface and the

flag indicator.


2 wire [BUSwidth-1:0] x;

3 reg [BUSwidth-1:0 ] y;

4 wire k, reset;

5 reg F;

6 Data_output syn_output( x, y, k ); // Data output

7 Flag synout_flag( k, reset, F ); // flag

Its structure of the synchronous output interface is shown below



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Synchronous Interface design 11

Flag

x y

WR

F

dataBus

S R

k

Figure 14: synchronous output interface

The software component of the synchronous output interface is responsible for writing data to the hard-

ware component, and coded as a procedure@ 3 '

7 % U X X `, where the parameter

is the output

message,

is the selected address and

is a control signal for writing.

@ 3 '

7 % U X X ` cE # %

}

f

# % # 7 % U X X `

f

In this program, the data can only be written after the flag}

is reset. Notice that in the hardware

component the @ % wire of the flag indicator is linked to the control wirel

of the latch, which is driven

by the control signal

. The assignment % 7 d 0 @ C E

in the procedure # % # 7 % U X X `

,

has the effect of setting the flag } .

The architecture of the hardware component of the synchronous multi-output interface is similar to that

of the hardware component of the synchronous multi-input interface. 15.

FlagWR

F

dataBus

S R

k

yx......

y1

y2

yn

addrBus

Figure 15: synchronous multi-output interface

where the output destination is chosen using the address value.

The software component of the synchronous multi-output interface is the same as that of the synchronous

output interface.



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12 Hand Shaking Protocol for Embedded Computer System

5 Hand Shaking Protocol for Embedded Computer System

This section explores two communication protocols used for transmitting data between the components

of the hardware/software mixed systems, where

The sender is not allowed to transmit a new data before the previous one has been input by the

receiver.

The receiver can input a data once after it has been output by the sender.

5.1 Hand Shaking Protocol for Hardware and Software Components

We propose the following hand shaking protocol to synchronise the hardware and software components

in an embedded system.

1. The protocol for the software components

Trigger the hardware component by sending a data to the output channel.

Never dispatch a new data to the hardware component before receipt of the acknowledgement

of the previous output.

The software component continues its execution after activating the hardware component.

2. The protocol for hardware component

The hardware component remains idle before the flag

is rising, where it is assumed that

the flag will be reset after one clock cycle.

The flag}

is set after the operation is completed.

As a result, the hardware component of an embedded system will be in the following form

% 7 0 U # %

f f

} C E `

where the function will be fired after

is set, and the flag}

is rising on its completion. In this

protocol, all flags is reset initially. Firstly the data is sent by the software component and processed by

the hardware component, then the result will be read by the software component. As one of the imple-

mentations, the structure of the protocol sees figure 16, where the wires # % #

- 0 %

from the software

component connects to the input port of the hardware component. The wires # % # - ' of the software

component links to the output port 3 of the hardware component. The address bus links to the hardware

directly.



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Hand Shaking Protocol for Embedded Computer System 13

k

H

W

WR

data

Bus

RD

addrBus

FN

Frdy

FrdyS

Data-in

Data-out

g

Fout

RS

R

STS

rst

ST-flag

x

y

Figure 16: The Protocol for Hardware and Software Components

In figure 16, the protocol for the software component is composed of the primitive output interface, the

synchronous input interface, the data output flag } 0 % which is set by the control signal and reset

by the signal 7 @ % , and the start flag which is set by the output of } 0 % in the rising edge of the clock

and reset after one clock cycle. The behaviour of can be described using the Verilog module

1 module ST_flag( S, rst, ST, clk );

2 input S, clk;

3 output ST, rst;

4 reg ST, rst;

5 always @( posedge clk )

6 begin

7 if (S) begin ST = 1b1; rst = 1b1; end

8 else begin ST = 1b0; rst = 1b0; end

9 end10 endmodule

5.2 The Synchronous Protocol between Processor and Co-processor

To support synchronous communication in a multiple processor system we adopt the following protocol

The data can be sent when the flag is reset.

The data can be received when the flag is set.

Using this protocol, all flags is reset initially. where the wires # % #

- 0 %

from the software component

connects to the input port of the hardware component. The wires # % #

- '

of the software component

links to the output port3

of the hardware component. The address bus links to the hardware directly.

The structure of the protocol sees figure 17. where the component in the upper dashed box, composed



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14 Conclusion

Flag

dataBus

RD

Busdata

WR

P1 P2

WR RD

F21

Flag

g1

k1

y1

y2

k2

w1

w2

g2

F12

RS

SR

x1

x2

Figure 17: The protocol between processor and co-processor

of the synchronous output interface and the synchronous input interface, is used for transmitting datafrom the processor to the co-processor, The component in the lower dashed box, used for transmitting

data from the co-processor back to the processor, is composed of the synchronous input interface and the

synchronous output interface.

As an example of using this protocol, we assume that the application system is made up of two pro-

cessors. The one is the main processor running the main program. The other one is the co-processor

managing the input and output devices, such as the keyboard and the LCD screen. In the system, the

co-processor can input and process the information from the keyboard, and then transmit it to the proces-

sor synchronously using the component in the lower dashed box. On the other hand, the processor can

display some outcomes of the main program in the LCD screen by transmitting them to the co-processor

synchronously using the component in the upper dashed box.

6 Conclusion

This paper shows how to apply the Bus extended technology in design of the communication interface for

the embedded systems. Firstly, we build the primitive input and output interfaces for processor, and thenimplement the synchronous input and output interface. Finally as their applications, we devise a hand-

shaking protocol for the hardware and software components of the embedded systems, and a synchronous

communication protocol between the processor and the co-processor. The technique discussed in the

report can also be used in design of various links between the components of the hardware/software

mixed systems.



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References 15

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[5] Bob Moore. SOC Should Mean Software-on-a-Chip . CoWare Inc., Electronic News, Oct

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[6] M. Chiodo et al. Hardware-Software Codesign of Embedded Systems. IEEE micro, Vol.14, No.4,

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[7] J.Van den Hurk and J.Jess. System-Level Hardware-Software Codesign. Kluwer Academic,1998.

[8] Intel Inc. MCS 51 Microcontroller Family Users Manual. Feb.,1994.

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[9] Xilinx,Inc., Development system reference guide. 2000.

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[12] Xilinx,Inc., Xilinx Netlist Format(XNF) Specification. June 1,1995.

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