1 5/15/2017

“Braking” through Barriers with Materials

Hans StorkSenior VP and CTO

2 5/15/2017

Four Perspectives

• A Company View

• A Technologist View

• A Supply Chain View

• An Industry Outlook

3 Public Information

• Headquarters: Phoenix, AZ• Employees: ~30,000 globally• Revenue: ~$5Bn(1)

• Market Capitalization: ~$6.1Bn(2)

• Ticker: ON• Founded: Spun-off from Motorola 1999, IPO 2000

ON Semiconductor Today

(1) Estimated Fiscal 2017 Revenue per Factset 11/8/2016; (2) As of May 9, 2017; Sector % based on 1Q17

4 5/15/2017

ON SemiconductorSustainable Competitive Advantage

Industry leading cost structureLarge scale and efficient operations

Global sales and distribution presenceStrong relationships with market leaders

Leadership in packaging technologiesControl over cost, technology & supply

One stop shop for discretes and ICs>80,000 SKUs

®

Cost Structure

Logistics and Sales Network

Integrated Manufacturing

Broad Product Portfolio

5 Public Information

*Amounts may not total due to rounding of individual amounts; Sector % based on 1Q17

Diverse Segment and Regional ProfileEnd Market Split Regional Split

Channel Split

Automotive32%

Computing10%Consumer

14%

Industrial, Mil, Aero, Medical

25%

Communications…

Distribution

58%

EMSI6%

OEM36%

North America

14%

Asia Pacific

(excludes Japan)63%

Europe16%

Japan7%

6 Public Information

ON + Fairchild: Industry Leader in Power Solutions

Medium voltageLow voltage High voltage

Serving similar customers with highly complementary product sets

Full spectrum of high, medium and low voltage products

Public Information7 5/15/2017

Wide Bandgap:Opportunity

andChallenges

8

Revolutionary Opportunity?

Needed:Cost of substrateReliability of interfaces Optimization of system

9 05/01/2017 CICC

Wide Bandgap Figure of Merit

Theoretical versus experimental performances and reported data of SiC and GaN power devices.

10 5/15/2017

Functions of buffer

• Providing smooth surface/interfaces– No pits, sub-nm roughness

• Wafer bow reduction, crack-free epi– Compensation of tensile stress from

thermal expansion mismatch• Crystal quality improvement

– Filtering of threading dislocations• VBD enhancement

– >3 µm buffer for VBD>650V• No negative impact on electrical properties

– Current collapse due to buffer traps

MOCVD of GaN HEMT epi stack on Si

Si (111)AlN nucleation layer

BUFFER

GaN channelAlGaN barrier

PassivationBasic concept:

Transition AlGaN

Graded AlGaNs

AlGaN layers + AlN interlayers

Superlattice(AlN/AlGaN)

• Heteroepitaxy lattice mismatch, CTE mismatch DEFECTS, STRESS

Separating layer

Buffer types:

11

0 1000 2000 3000 40000,01

0,1

1

Ga Al

Ga, A

l con

tent (%

)

Depth (nm)

1E15

1E16

1E17

1E18

1E19

1E20

1E21

1E22

O before O after

O co

ncen

tratio

n (at/

cm3 )

Rougheninglimit

Before oxygen reduction

After oxygen reduction

Roughening limit

• Defect formation due to oxygen contamination:– Formation of inversion domains on the oxidized Si surface.– Low AlN quality and coalescence due to oxidation of the

material during growth.– Localized Ga-Si melt-back etching due to Ga diffusion through

the defects in the AlN layer.

Smooth surfaces (Graded buffer / AlN)

12

Com

pres

sive

st

ress

Tens

ile

stre

ss

Coefficient of Thermal Expansion:

GaN > AlGaN > AlN > Si

Lattice constants:

Si > GaN > AlGaN > AlN

Compensation of tensile stress created during cooling by compressive stress build-up during growth

Wafer bow reduction, crack-free epi

13

Crystal quality improvement

AlN

AFM 1x1 µmImprovement of the Superlattice buffer

Filtering of the dislocations

SLS

GaNTerminations of the dislocations:

– mixed type– edge type

• Epi layers are smooth throughout the buffer• State-of-the-art surface roughness• Dislocation density ~1e8 in the top layers – Incredibly bad for Si, but quite good for GaN!

SuperLattice buffer technology was successfully developed in IMEC / ON Semiconductor cooperation

AlNRMS roughness = 0.33nm

V-trenches, Inversion domains suppressed

15

Materials Device Module System

ON Semi’s GaN R&D Ecosystem

• MOCVD epi internal • Transfer of recipe and

knowledge from imec

• Device fabrication, testing, intrinsic reliability internal

• E-mode in imec• Assembly and apps

testing internal

• Dr GaN (integrated half-bridge)

• PIM, IPM

• Partnering with OEM R&D teams

16

Power ModulesConverters and Motor Drives favor modules• Delivering electrical power requires efficient voltage conversion in ever smaller

(AND faster AND cheaper) and more reliable ways• The switching devices are built in unique ways, favoring package level integration

instead of monolithic integration• Driver circuitry to translate controller intelligence to precise signals for the

switches are typically integrated enabling higher value for the product

Modules can embed 2, 4 or 6 switches

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Issues in Power Management / Control

Reduce power losses - dissipation– Low Rds(on)– Low inductance: Critical for higher frequencies greater than multi-MHz range

Higher power densities drive requirement for improved thermal dissipation– Layout details are significant factor in thermal management– Details of power density distribution within active devices affect ability to

correlate measurement with simulation

System/package/module/materials optimization– Improved electrical and thermal management– Better knowledge of materials

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Common Trends: Efficiency vs. FrequencyEfficiency vs. Frequency:• Difficult to maintain high efficiency with an increase in frequency• Motivation to migrate to high frequency is often driven by product miniaturization• Smaller system sizes increase power density requirements which drives the need for

improved thermal solutions

20

Power Module Thermal PredictionQ0BOOST Gen III

(Si IGBT)

T1 off-state

T2 off-state

Spice model of the dies

.

The current distribution in a PIM affects hotspots and limits resistance

21

Power Substrate Technologies

Rectifier

IGBT

eDPC

• Cu Plating• Middle to high power

IMS

• Lamination/etching• Low to middle power

DBC

• Sintering/etching• Middle to high power

• Sintering, etching and Cu Plating

• Middle to high power

CeramicCu

Cu

CeramicCuCu

Cu

Anodized Al

IMSCu

CeramicCu

Cu

DBC+

IMS

22

Principles of Si/SiC/GaN Power Devices technologies

b [µ

m]

b [µ

m]

b [µ

m]

b [µm]

Si

Buffer

GaN f [nm]AlGaN

Material Properties Device structure

GaN HEMTSiC xFETSi MOSFETSi IGBT

+ Diode (Si or SiC)

• Current flows vertical in Si & SiC based power devices Ploss_on ≈ f(1/A; b)

• GaN performance is based on 2DEG in a horizontal interface Ploss_on ≈ f(1/l; b)

• Voltage capability in the current path is defined by distance b BVCES ≈ f(b)

• Switching losses are influenced by charges in the volume Ploss_switch ≈ f(A; b)

• Ability to dissipate losses is proportional to die size Pdissipate ≈ 1/Rth ≈ f(A)

In all technologies die size is affecting losses but also dissipation ability!

23

SiC Epitaxy and other Processing

• Epitaxy reactors available for mass production, growth temperatures ∼ 1600 C Obtaining low defect concentrations and smooth surfaces is critical for SiC devices

• Most other process steps are Si-compatible,runs in Si wafer fab at higher temperature

• Dopants don’t diffuse (ion implantation used)

• Thermal SiO2 layer can be grown like for Sibut with more defects in SiC/SiO2 interface

Top view of epitaxy reactor

SiC wafers

24

Extended defects in SiC material

• Even best SiC wafers contain significant number of extended defects• Many can be seen using optical techniques, dislocations seen by KOH etching• Most defects are quite harmless to devices, defect understanding still developing

Optically detected defects in a SiC wafer

SiC surface after etching in molten KOH(destructive testing)

dislocations

26

Diode Avalanche Robustness

0

0.5

1

1.5

0 2 4 6 8 10

1200V die, L=20µH

Eaval

aval

anch

e en

ergy

(J)

active chip area (mm2)

Scaling with chip area Scaling with avalanche time

0

5

10

15

20

25

0 5 10 15 20 25

650V SBD, this worklinear fit, Tcr=440C650V, Basler et al (Infineon) 2016650V, Nakamura et al (Rohm) 2012

spec

ific

aval

anch

e en

ergy

(J/c

m2 )

square root of time in avalanche (µs0.5)

28

Doping in 4H-SiC

29

4H-SiC Surface Construction

30

Development Crystal GrowthDislocation free/low stress Boule:- Recipe development for growth of

high quality boule in dedicated PVT tool and simulation tools

- Wafering- Metrology assessment feed

forward for improvement

Seed expansion:

• Dedicated PVT tool for crucible hardware optimization based on simulation and seed analysis

• Improved seed will be used for optimized crystal growth

Original seed

Crucible design Optimization based on outer crystal quality

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• Both n- and p-type control across a wide doping range is relatively easy in SiC.• Ability to form silicon dioxide (SiO2) as a native oxide is another favorable point.

Status of SiC Devices

Leading Rsp ~ 4.2mO achieved by understanding and optimizing the key Rdsoncontributors:

- Channel: increase surface mobility- JFET: trade-off Ecrit vs JFET pinch-off- control Epi process (minimize overhead)- control design pitch

Public Information32 5/15/2017

Economy and Supply Chain

33 05/01/2017 CICC

Global Semiconductor Outlook

34

Global Semiconductor Outlook

35 05/01/2017 CICC

Semiconductor material supply impact

• Silicon wafer fab utilization expected to be > 95%. • Installed base of depreciated 8-inch capacity at the major pure play

foundry suppliers is filled with overflow from 300mm fabs• High volume, key products such as fingerprint sensors, MCUs for

consumer and automotive, PMICs, and display drivers are more cost effective if run on 8-inch wafers rather than being redesigned for nodes running on 12-inch wafers

• Demand for 8-inch wafers remains strong driven by the increase in IoT and wearables. Both of these products require inexpensive silicon solutions and an array of technologies that are manufactured more efficiently using 8-inch wafers

36

Precious Metals - Au, Pt, Pd & Ag

Source: Statista

Source: ABN Amro

37 05/01/2017 CICC

IPA pricing trend

Source: Mintec

• Propylene is the feedstock for IPA production• Disruptions impact pricing dramatically

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Supply Chain Summary

• Strong Semiconductor activity overall• Upwards price pressure both in semiconductors as in the upstream supply chain• Capacity will be tight, both in Foundries (fabs are full) and in Silicon wafer supply• China continues investment in fab capacity (2018 and beyond)• Major raw material costs remain stable but trending up for the next several years• Future outlook (2018 and beyond) will strongly depend on political/fiscal stimulus

policies in the different economic zones

Public Information39 5/15/2017

Industry Technology

Future

40 05/01/2017 CICC

Smaller dimensionsDevice and circuit cleverness

1/.84xΧ 1/.85xΧ Χ1/ 1/

2.7x=

Logic Scaling is Continuing…

41 05/01/2017 CICC

Power Discrete Scaling is also Continuing…

SuperJunction 600V SuperFET1 600V SupreMOS(trench based)

600V SuperFET2 650V SuperFET3

cell pitch 20um 13um 14um 7.5um

# of epi layers 6 layers 2 layers, 1 in trench 6 layers 13 layers

Rsp 35 mΩ x cm2 19 mΩ x cm2 23 mΩ x cm2 13.5 mΩ x cm2

The first super-junction MOSFET had a multiple epi/implant design. This architecture still dominates the market today because of its superior charge control. The technology roadmap follows a simple scaling of cell pitch and number of epi layers. Trench-based architectures have not been able to displace multiple epi/implant designs.

Public Information42 5/15/2017

communication

With Heterogeneous Integration• Logic density improvements limited to low voltage• Power and sensor applications need higher voltages for energy and dynamic range• Functional unity and cost/performance require module packaging

Source N.C.C. Lu, Nov 2016

43

• Scaling is continuing; as with logic, power scaling benefits from smaller dimensions and new materials

• New materials offer superior breakthroughs, but require development patience and system level optimization

• Partnerships across the supply chain accelerate progress and improve investment for participants

• Market dynamics can put the brakes on:– Economics is rather unpredictable – logistics are hard – Customers demand extreme quality, safety and security

Summary Comments

CICC | May 1, 2017

QUESTIONS & ANSWERS

45 5/15/2017

• Industry consolidation to continue– Still too many sub-scale players– Significant fragmentation in Analog/Power segment

• Scale is relative– Larger players will continue to consolidate– Maintaining competitive cost structure is critical

• ON will participate, but as always, in a disciplined manner– Investments will be required to generate returns significantly above cost of

capital– Focus on adding key technologies and capabilities

• Collateral benefits– Potential for share gains driven by customer consternation, especially if a

foreign entity is involved

THOUGHTS ON INDUSTRY CONSOLIDATION