hands-on training – june 18-19, 2012 1 netfpga hands-on training day 2 presented by: adam...
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Hands-on Training – June 18-19, 2012 1
NetFPGA Hands-on TrainingDay 2
Presented by: Adam Covington (Stanford University)
Indiana University, BloomingtonJune 18 - 19, 2012
http://NetFPGA.org
Hands-on Training – June 18-19, 2012 2
Previously Covered
•Infrastructure– Tree– Build System– Scripts
•The Life of a Packet Through the NetFPGA– Hardware Datapath – Interface to software: Exceptions and Host I/O
•Implementation– Module Template– User Data Path– Write Crypto NIC using a static key
•Simulation and Debug– Write and Run Simulations for Crypto NIC
Hands-on Training – June 18-19, 2012 3
Tutorial Outline
•Registers
– Explain Register System– Add XML to define Crypto NIC encryption key– Use Generic Register Module to implement register– Update Simulations
•Build and Test Hardware– Build– Explanation of Hardware Tests– Write and run Hardware Tests
• Verify value: 0xFFFFFFFF• Verify value: 0xFF00FF00• Verify value: 0x55555555
•Group Discussion
Hands-on Training – June 18-19, 2012 5
Specifying the Key via a Register
• Can set the key via a register instead
• Need to understand the register system
• Register system:– Specify registers provided by module in the
module XML file– Implement registers in module
• Can usually use generic_regs
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Register bus
reg_addr_out
reg_data_out
Modulereg_addr_in
reg_data_in
reg_req_in
reg_ack_in
reg_rd_wr_L_in
reg_src_in
reg_req_out
reg_ack_out
reg_rd_wr_L_out
reg_src_out
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Module XML file (1)
• Each module (with registers) has an XML file
<?xml version="1.0" encoding="UTF-8"?><nf:module ...> <nf:name>crypto</nf:name> <nf:description>Registers for Crypto Module</nf:description>
<nf:prefix>crypto</nf:prefix>
<nf:location>udp</nf:location>
<nf:blocksize>64</nf:blocksize>
Name/description
Prefix appears before register names in source code
Location: where in the design should this module be instantiated? udp = user data path
Amount of memory to allocate to the block (in bytes, use k/m to indicate kilo/megabytes)
Hands-on Training – June 18-19, 2012 8
Module XML file (2) <nf:registers>
<nf:register> <nf:name>key</nf:name> <nf:description>The Key value used by the Crypto
Module</nf:description> <nf:type>generic_software32</nf:type> </nf:register>
</nf:registers>
<nf:constants> </nf:constants>
<nf:types> </nf:types></nf:module>
Can also declare constants and data types
Register declaration: need name, description, and width or type
Hands-on Training – June 18-19, 2012 9
Generic Registers Modulegeneric_regs # ( .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH), .TAG (`CRYPTO_BLOCK_ADDR), .REG_ADDR_WIDTH (`CRYPTO_REG_ADDR_WIDTH),
.NUM_COUNTERS (0), .NUM_SOFTWARE_REGS (1), .NUM_HARDWARE_REGS (0)) crypto_regs ( .reg_req_in (reg_req_in), … .reg_src_out (reg_src_out), … .software_regs (key), .hardware_regs (), …
Make sure you declare key as a 32-bit wire
Hands-on Training – June 18-19, 2012 10
Replacing Static Key
• Replace the static key with the key from the registers
• Update your simulations to set the key
Hands-on Training – June 18-19, 2012 12
Synthesis
• To synthesize your project– Run make in the synth directory
(netfpga/projects/crypto_nic/synth)
Hands-on Training – June 18-19, 2012 13
Hardware Tests
• Test compiled hardware
• Test infrastructure provided to – Read/Write registers– Read/Write tables– Send Packets– Check Counters
Hands-on Training – June 18-19, 2012 14
Example Hardware Tests
• Reference Router – Send Packets from CPU– Longest Prefix Matching– Longest Prefix Matching Misses– Packets dropped when queues overflow– Receiving Packets with IP TTL <= 1– Receiving Packets with IP options or non IPv4– Packet Forwarding– Dropping packets with bad IP Checksum
Hands-on Training – June 18-19, 2012 15
Python Libraries
• Start packet capture on interfaces
• Clear all tables in hardware
• Create packets– MAC header– IP header– PDU
• Read/Write registers
• Read/Write reference router tables– Longest Prefix Match– ARP– Destination IP Filter
Hands-on Training – June 18-19, 2012 16
Hardware Test Examples
• Reference Router– Packet Forwarding
• test/both_packet_forwarding
– Longest Prefix Match• test/both_lpm_generic
– Send and Receive • test/hw_send_rec
Hands-on Training – June 18-19, 2012 17
Creating a Hardware Test
Useful functions:Register access:
nftest_regwrite(addr, value)nftest_regread_expect(addr, expect)
Packet generation:make_IP_pkt(…) – see documentationencrypt_pkt(key, pkt)decrypt_pkt(key, pkt)
Packet transmission/reception:nftest_send_phy(interface, pkt)nftest_expect_phy(interface, pkt)nftest_send_dma(interface, pkt)nftest_expect_dma(interface, pkt)
Hands-on Training – June 18-19, 2012 18
Creating a Hardware Test (2)
• Your task:
1. Template files netfpga/projects/crypto_nic/test/both_crypto_encrypt/run.py
2. Implement your hardware tests
Hands-on Training – June 18-19, 2012 19
Running Hardware Tests
• Use command nf_test.py– Required Parameter
• sim or hw (right now only use hw)– Optional parameters
• --major <major_name>• --minor <minor_name>
both_crypto_encrypt
• Run the commandnf_test.py hw --major crypto --minor encrypt
majormajor minorminor
Hands-on Training – June 18-19, 2012 21
Interface with software
• Write two simple utilities:– getkey – get the current key and print it– setkey – set the key to a value specified on the
command line
– skeleton C files in the sw directory– build with ‘make’
• Two functions:readReg(nf2device *dev, int address, unsigned *rd_data);writeReg(nf2device *dev, int address, unsigned *wr_data);
Hands-on Training – June 18-19, 2012 22
Recap
Build a complete NetFPGA design
Learn:• Module creation (Verilog)• Reference pipeline integration• Verification via simulation• Verification via hardware tests• Interaction with software
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Project Ideas for the NetFPGA• IPv6 Router (in high demand)• TCP Traffic Generator• Valiant Load Balancing • Graphical User Interface (like CLACK)• MAC-in-MAC Encapsulation• Encryption / Decryption modules• RCP Transport Protocol • Packet Filtering ( Firewall, IDS, IDP )• TCP Offload Engine• DRAM Packet Queues• 8-Port Switch using SATA Bridge• Build our own MAC (from source, rather than core) • Use XML for Register Definitions
http://www.netfpga.org/foswiki/NetFPGA/OneGig/ModuleWishlist
Hands-on Training – June 18-19, 2012 26
NetFPGA DesignsProject (Title & Summary) Base Status Organization Docs.
IPv4 Reference Router 2.0 Functional Stanford University Guide Quad-Port Gigabit NIC 2.0 Functional Stanford University Guide Ethernet Switch 2.0 Functional Stanford University Guide Hardware-Accelerated Linux Router 2.0 Functional Stanford University Guide Packet Generator 2.0 Functional Stanford University Wiki OpenFlow Switch 2.0 Functional Stanford University Wiki DRAM-Router 2.0 Functional Stanford University Wiki NetFlow Probe 1.2 Functional Brno University Wiki AirFPGA 2.0 Functional Stanford University Wiki Fast Reroute & Multipath Router 2.0 Functional Stanford University Wiki NetThreads 1.2.5 Functional University of Toronto Wiki
URL Extraction 2.0 Functional Univ. of New South Wales Wiki
zFilter Sprouter (Pub/Sub) 1.2 Functional Ericsson Wiki Windows Driver 2.0 Functional Microsoft Research Wiki IP Lookup w/Blooming Tree 1.2.5 In Progress University of Pisa Wiki DFA 2.0 In Progress UMass Lowell Wiki G/PaX ?.? In Progress Xilinx Wiki Precise Traffic Generator 1.2.5 In Progress University of Toronto Wiki Open Network Lab 2.0 In Progress Washington University Wiki KOREN Testbed ?.? In Progress Chungnam-Korea Wiki RED 2.0 In Progress Stanford University Wiki Virtual Data Plane 1.2 In Progress Georgia Tech Wiki Precise Time Protocol (PTP) 2.0 In Progress Stanford University Wiki Deficit Round Robin (DRR) 1.2 Repackage Stanford University Wiki
.. And more on http://netfpga.org/foswiki/NetFPGA/OneGig/ProjectTable
Hands-on Training – June 18-19, 2012 27
Thoughts for Developers
• Build Modular components– Describe shared registers (as per 2.0 release)– Consider how modules would be used in larger systems
• Define functionality clearly – Through regression tests– With repeatable results
• Disseminate projects– Post open-source code– Document projects on Web, Wiki
• Expand the community of developers– Answer questions in the Discussion Forum – Collaborate with your peers to build new applications
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Join the NetFPGA.org Community
• Log into the Wiki
• Access the Beta code
• Join the netfpga-beta mailing list
• Join the discussion forum
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Contribute to the Project
• Search for related work
• List your project on the Wiki
• Link your project homepage
Hands-on Training – June 18-19, 2012 31
Nick McKeown, Glen Gibb, Jad Naous, David Erickson, G. Adam Covington, John W. Lockwood, Jianying Luo, Brandon Heller,
Paul Hartke, Neda Beheshti, Sara Bolouki, James Zeng, Jonathan Ellithorpe, Sachidanandan Sambandan, Eric Lo,
Sam D’Amico
Acknowledgments
NetFPGA Team at Stanford University (Past and Present):
NetFPGA Team at University of Cambridge (Past and Present):
Andrew Moore, David Miller, Martin Zadnik, Muhammad Shahbaz
All Community members (including but not limited to):
Paul Rodman, Kumar Sanghvi, Wojciech A. Koszek, Yahsar Ganjali, Martin Labrecque, Jeff Shafer,
Eric Keller , Tatsuya Yabe, Bilal Anwer,Yashar Ganjali, Martin Labrecque
Ram Subramanian, Kees Vissers, Michaela Blott, Shep Siegel
Hands-on Training – June 18-19, 2012 32
Special thanks to our Partners:
Other NetFPGA Tutorial Presented At:
SIGMETRICS
Ram Subramanian, Patrick Lysaght, Veena Kumar, Paul Hartke, Anna Acevedo
Xilinx University Program (XUP)
See: http://NetFPGA.org/tutorials/
Hands-on Training – June 18-19, 2012 33
Thanks to our Sponsors:
• Support for the NetFPGA project has been provided by the following companies and institutions
Disclaimer: Any opinions, findings, conclusions, or recommendations expressed in these materials do not necessarily reflect the views of the National Science Foundation or of any other sponsors supporting this project.