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VLSI DESIGN1999, Vol. 9, No. 1, pp. i-iiReprints available directly from the publisherPhotocopying permitted by license only

(C) 1999 OPA (Overseas Publishers Association) N.V.Published by license under

the Gordon and Breach SciencePublishers imprint.

Printed in Malaysia.

Guest Editorial

STEPHAN OLARIU and RONG LIN

This special issue of VLSI Design presents acollection of seven papers selected out of morethan 35 submissions received following the Call forPapers. Each submission was sent to three referees,all of them experts in the area of bus-basedarchitectures. The result is impressive. The papersfeatured in this Special Issue cover a wide range oftopics from sorting to string matching, to loadbalancing, to simulation, matrix operations, torobotics, to the design of high-performance scal-able architectures.

Before we summarize the papers of this issue wewould like to thank all the referees for theirthorough reviewing job and all the authors forsubmitting their manuscripts to the Special Issue.Last but certainly not least, our thanks go toProfessor Zobrist for all the help and adviceprovided during the various stages of this under-taking.We now turn to the task of introducing briefly

the papers of this issue.In the work "Sorting on Reconfigurable

Meshes: An Irregular Decomposition Approach",Lai and Sheng demonstrate that dividing aproblem evenly is not necessarily a good way topartition. There are occasions where an irregularpartitioning is preferable. They go on to apply thisapproach to sorting on the reconfigurable mesh,obtaining a sorting algorithm that is simple,scalable, and as broadcast-efficient as the bestknown result.

In the paper "Single Step Undirected Reconfi-gurable Networks", Ben-Asher and Schuster showthat for the reconfigurable mesh the constantinvolved in a number of O(1) time algorithms canalways be reduced to 1, still using a polynomialnumber of processors. Given a reconfigurablemesh that computes a set of values in O(1) time,they show that it can be simulated by a ingle-stepreconfigurable mesh whose size is polynomial inthe size of the original mesh.

In the paper "Investigation of various meshArchitectures with Broadcast Buses for High-Performance Computing" Ziavras carries out anextensive comparative analysis between variousmesh-connected architectures that contain sparsebroadcast buses for low-cost high-performanceparallel computing. Shared memory and Reconfi-gurable Mesh", Matias and Schuster look atrelations between the PRAM model and thereconfigurable mesh providing mutual simulationsbetween these models.

In the paper "Partitionable Bus-Based StringMatching Algorithm for Run-Length CodedStrings with VLDCs, Chen and Chung presentan efficient parallel string matching algorithm. Forrun-length coded strings with variable length don’tcares. Given a run-length coded text of length 2naver E and a run-length coded pattern of length2m, their algorithm runs in O(1) time on areconfigurable mesh of O(mn) processors. In orderto be suitable for VLSI modular implementation a

ii GUEST EDITORIAL

partitionable parallel algorithm on the reconfigur-able mesh is further presented.

In the paper "Multiplication of Matrices withDifferent Sparseness Properties on DynamicallyReconfigurable Meshes", Middendorf et al., pre-sent algorithm for multiplying several types ofsparse matrices of size n xn on dynamicallyreconfigurable arrays of the same size. Amongother results, they obtain O(kn/2) algorithms forthe case that one matrix is a general sparse matrixwith at most kn nonzero elements and the othermatrix has at most k nonzero elements in everyrow or every column.

In the paper "Reconfigurable Shift SwitchingParallel Comparators", Lin and Olariu presentnovel asynchronous YLSI comparator schemesbased on the recently proposed reconfigurableshift switching logic and the traditional prechargedCMOS domino logic. The proposed schemesalways produce a semaphore as a byproduct ofthe process to indicate the end of the dominoprocess, which requires no additional delay and aminimal number of additional devices.

Finally, in the work "Finding Combined L andLink Metric Shortest paths in the Presence ofOrthogonal Obstacles: A Heuristic Approach",Lim et al., present new heuristics search algorithmsfor searching combined rectilinear and link metricshortest paths in the presence of rectilinearobstacles. Their algorithms combine the best

features of maze-running algorithms and line-search algorithms.We trust you will be as stimulated as we are by

the enclosed contributions.

Guest Editors’ Biographies

Stephan Olariu received the M.Sc. and Ph.D.degrees in computer science from McGill Uni-versity, Montreal in 1983 and 1986, respectively.In 1986 he joined the Computer Science Depart-ment at Old Dominion University where he is nowa professor.

Dr. Olariu has published extensively in variousjournals and conference proceedings. His researchinterests include parallel algorithms, parallel algo-rithms, image processing and machine vision,computational graph theory, computational geo-metry, and mobile computing.Rong Lin received the B.S. in mathematics from

Peking university (China), M.S. in ComputerScience from Beijing Polytechnical University(China) and Ph.D. in computer science from OldDominion University in 1989. He is currently anassociate professor with the Department of Com-puter Science of SUNY at Geneseo. His currentresearch interests include VLSI arithmetic, parallelarchitectures and algorithms, digital signal proces-sing, and reconfigurable architectures.

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