gtu phd core course termpaper

8/11/2019 GTU PhD Core Course Termpaper

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Term Paper

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Contents

1 MOS Switch 4

2 MOS Diode 5

3 Current Sink and Source 5

4 Current Mirror 6

5 Current and Voltage References 7

6 CMOS Inverters 8

7 Differential Amplifier 10

8 Cascode Amplifier 11

9 Current Amplifier 11

10 Two Stage Op-Amp 13

11 Cascode Op-Amp 16

12 Comparators 16

13 Digital-Analog Converter 18

14 Analog-Digital Converter 20

15 References 23

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1 MOS Switch

A B

C

(a) MOSFET as a switch (b) I-V characteristic of MOSFET operating as aswitch

Figure 1: MOSFET as a switch

The MOS technology provides a very good switch. In figure 1a, MOS transistor that may be usedas a switch is illustrated. Terminals A and B can be considered as the two terminals of the switch,while terminal C is the control terminal to turn on and off the switch. The MOS switch is a voltagecontrolled switch. The voltage at terminal C controls the switch. Here, MOS device is assumed to be innon-saturation, thus in on stage, the voltage across the switch VDS is smaller than VGS VTH. The onstate resistance of switch consists of series combination ofrd and rs. The drain current in non-saturationis given by,

Id = K

WL

(VGS VT)VDS V2

DS2

(1)

rON = 1

id/VDS|Q= L

KW[VGS VT VDS] (2)

Where, Q is quiescent point of the transistor. In figure 1b the channel current as a function of the VDSvoltage is plotted. When theVGS is less than VT, the switch is OFF. The OFF state resistance of theswitch is very high. The performance of the OFF stage is limited by the leakage currents. The leakagecurrents are source-drain leakage current, source to bulk and drain to bulk leakage current. The applicationof the MOS switch can be found in many circuits such as modulator, multiplexers, filtering circuits andto simulate the resistor.

BA

Figure 2: CMOS switch

The dynamic range limitations of the MOS device switch can be overcome by CMOS switch illustratedin figure 2. When is high, both transistors are ON providing low impedance path.

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Vds

I

+

+

(a) MOSFET asa diode

-5e-05

0

5e-05

0.0001

0.00015

0.0002

0.00025

0.0003

0.00035

0 0.5 1 1.5 2 2.5 3 3.5

Id

Vds

(b) I-V characteristic of MOSFET operating as adiode

Figure 3: MOSFET as a diode

2 MOS Diode

When the gate of the MOS device is tied together with the drain, the device operates in saturation regionand VDSbecomes same as the VGS. The drain current is given by,

Id= KW

L (VGS VT)2 =

2(VGS VT)2 (3)

V =VGS=VDS=

2Id+ VT (4)

The IV characteristic of this configuration is plotted in figure 3b, which is similar to that of diode. FromEqu. 4, if V and I is known then device size() can be adjusted. The output resistance of MOS diodeexcluding parasitic capacitors can be given by,

rout= 1

gm+ gmbs+ gds 1

gm(5)

3 Current Sink and Source

VGG

Iout

Vout

Iout

VoutVGGVTH

+

(a) Current sink

VGG

Vout

Iout

VDD

VoutVGG +|V |TH

Iout

+

(b) Current source

Figure 4: Current Sink and Source

The current sink and sources are two terminal devices whose current at any instance of time is in-dependent of the voltage across their terminals. In figure 4a current sink is illustrated along with itscharacteristic. When the gate voltage is greater than threshold voltage and the device is in saturation itacts like a current sink. Thus when Vout VGG VT >0, transistor draws almost constant current. Thewith constant gate voltage output resistance is given by,

rout= 1 + VDS

Id 1

Id(6)

In figure 4b current source implemented with the PMOS transistor is illustrated. The condition for theproper operation region is Vout VGG+ |VT0| The advantage of current source and sink shown in figure4a, 4b is their simplicity. However, there are two areas in which improvements may be needed for certain

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VGG

Iout

Vout

+

r

(a)

Iout

Vout

VGG

VGC

+

M2

M1

(b)

Figure 5: Current Sink with improved output resistance

applications. One is to increase the output resistance resulting in more constant current over range of theVout. The second improvement is to decrease the value ofVMIN. In figure 5a, technique is illustrated toincrease the value of the output resistance. The output resistance in this case is given by, rout= gm2rds2r.The similar technique using MOS transistor instead of the resistor is illustrated in figure 5b. The output

resistance is given by, rout = gm2rds2rds1. Here, we get improvement in the output resistance, howeverthe value of the VMIN is also increased which is unwanted and worse effect.

2VON T+2V

+VON

VT

+VON

VT

IOUT

IREF

M2

M1M3

M4

+

_

+

_

+

_

VOUT

(a) Cascode Current sink

IOUT

IREFIREF

VOUT

VON

VON

M3

_

+

_

M4

+

_

+

_

M2

M1

(b) Improved Cascode current sink

Figure 6: Cascode Current sink

In Figure 6a standard cascode is illustrated. TheVMIN voltage is in this case is the voltage to keeptransistors M1 and M2 in saturation that is equal to VT + 2VON. In figure 6b improved version of thestandard cascode current source with its characteristic is shown. Here, VMIN is reduced further to thevalue 2VON

4 Current Mirror

Current mirror is extension of the current sink and source which can be used to mirror the current and as acurrent amplifier. In figure 7a simple current mirror is illustrated. As the gates of the both transistors aretied together, as long as both transistors are in saturation, current of M1 is mirrored in M2, assuming thatboth transistors are identical and effect of channel length modulation is absent. The output resistance ofthis current mirror isrout 1/Id. The first non-linear effect that ditoriates the performance of illustratedcurrent mirror is channel length modulation. The second non-linear effect is offset in threshold voltageof transistors because of process variations. The third non-linear effect is error in the aspect ratio of twotransistors that arises due to error in manufacturing process.

In figure 7b, standard cascode current mirror is illustrated that reduces ratio errors due to the differencein input and output voltage and improves the output resistance. The output resistance is given by,rout= rds2+ rds4+ gm4rds2rds4(1 + 4)

Another current mirror named Wilson current mirror is illustrated in figure 7c that increases the

output resistance through the negative feedback. IfI0 increases, mirror action causes current through M1to increase. IfIIis constant and if we assume that there is some resistance form drain of M1 (gate of M3)

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iI

iO

M1 M2

(a) Simple current mirror

iI

iO

M1 M2

M3 M4

(b) Cascode current mirror

iI

iO

M1 M2

M2

(c) Wilson current mirror

Figure 7: Current mirrors

to ground, then gate voltage of M3 decreases. The output resistance for Wilson current source is given by,

rout= rds3+ rds2

1 + rds3(1 + 3) + gm1rds1gm3rds33

1 + gm2rds2

(7)

5 Current and Voltage References

An ideal voltage or current reference is independent of the power supply and temperature variations.Such voltage or current references provides stable current and voltages to CMOS circuit building blocks.Simplest voltage reference can be built with the help of the voltage divider circuit, however the outputof such reference is directly proportional to the power supply variations. The performance of the voltagereference can be measured in terms of sensitivity S.

SVREFVDD = VREF/VREF

VDD/VDD=

VDDVREF

VREFVDD

(8)

Vref

+

VDD

RI

Figure 8: Simple voltage reference using MOSFET

A simple way of obtaining a better voltage reference is to use active device as shown in figure 8. Thereference voltage has less dependence on the supply voltage. If effect of the channel length modulation isignored then reference voltage and sensitivity are given by,

VREF =VT 1R

+

2(VDD VT)

R +

1

2R2 (9)

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SVREFVDD =

1

1 + (VREF VT)R

VREFVDD

(10)

Here, it can be noted that the sensitivity is less than unity.

Startup

M8

M7

M3 M4

M2

M5

M6

R

M1

I1 I2

I5

I6

VDD

Figure 9: Bootstrap reference circuit

If the voltage across the active device is used to create a current and this current is somehow usedto provide original current through the device, then the current or voltage is for all practical purposeindependent of supply voltage. This technique of generating reference is called bootstrap reference. Infigure 9, realization of such circuit is shown. M3 and M4 causes currents I1 and I2 to be equal. CurrentI2 flows through R creating voltage I2R and I1 flows through M1 causing Vgs1 voltage. Since these twovoltages are connected together equilibrium is established. If channel length modulation is neglected thenthe equilibrium point can be described by,

IQ= I2 = VT1

R +

1

2R2+

1

R

2VT11R

+ 1

21

R2 (11)

Here,I2 and IQ are independent ofVDD in first order analysis. We can getI5 andI6 throughI2 whichcan be used further. However to get desired equilibrium point, startup circuit as shown in figure 9 isrequired.

6 CMOS Inverters

Active load inverter

VDD

M2

M1

Out

In

(a) Active PMOS load in-

verter

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3

VOUT

VIN

(b) Voltage transfer characteristic curve

Figure 10: CMOS active PMOS load inverter circuit and VTC

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In figure 10, PMOS active load inverter is illustrated. The PMOS device is connected in diode fashionand thus it operates in the saturation region. The voltage transfer characteristic of this inverter is shownin figure 10. From this characteristic it can been observed that, this inverter has limited gain and limitedoutput voltage swing. The maximum output voltageVOUT(max) and minimum output voltageVOUT(min)can be given by,

Vout(max) =VDD | VTP| (12)Vout(min) =VDD VT VDD VT

1 + 2/1(13)

The minimum output voltage VOUT(min) is not at lower limit (ground) because M2 is in saturationand thus continuously current flows through it and that must flow through M1. For any MOSFET, thereis zero voltage across it only its drain-source current is zero that is not case here. Thus minimum voltageis corresponding to the minimum value of current that passes through M1. The small signal voltage gainand output resistance are given by,

VoutVin

= gm1gm2

=

KNW1L2KPW2L1

(14)

Rout= 1gds1+ gds2+ gm2

1gm2

(15)

Current source inverter

VDD = 3.3V

VGG

1.65V

M2

M1Vin

Vout

(a) Current source inverter

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3

VOUT

VIN


Figure 11: CMOS current source inverter circuit and VTC

In figure 11a current source inverter is illustrated that has higher gain than active load inverter. Insteadof connecting the PMOS in diode fashion as a load, current source is used. The current source implementedusing common gate PMOS configuration with gate is connected to fix bias voltage. The figure 11b showsthe voltage transfer characteristic of this inverter. The maximum output voltageVout(max) is VDD since

when M1 is off, the voltage across the M2 can go to zero, allowing output voltage to reach VDD. Thelower limit of the output voltage Vout(min) can be found assuming M1 in non-saturation region.

Vout(min) = (VDD VT1)1

1

21

VSG2 | VT2|

VDD VT1

2 12 (16)

The small signal gain and the output resistance is given by

VoutVin

= gm1gds1+ gds2

=

2KNW1

L1ID

12

11+ 2

1

ID(17)

rout= 1

gds1+ gds2=

1

ID(1+ 2)

(18)

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VDD

M2

M1

VoutVin

(a) Push Pull inverter

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3

VOUT

VIN


Figure 12: CMOS current source inverter circuit and VTC

iD3

iD1

iSS

iD2

iD4

VDD

M1 M2

M3 M4

Vout

VgM5

Vin

Figure 13: CMOS differential amplifier

Push pull inverter

In figure 12a, push pull CMOS inverter is illustrated. From the voltage transfer characteristic it can beinterpreted that this amplifier has higher gain and output voltage swing is rail to rail. The largest voltagegain can be achieved in region when both transistors M1 and M2 are in saturation. The voltage gain underthis condition is given by,

voutvin

= gm1+ gm2gds1+ gds2

=

2/ID

KNW1/L1+

KPW2/L2

1+ 2

(19)

7 Differential Amplifier

In figure 13, CMOS differential amplifier using a PMOS current mirror load is illustrated. Under quiescent

conditions two currents in M1 and M2 are equal and summed to ISS, the current in current sink M5. Thecurrent of M1 will determine the current in M3. Ideally this current is mirrored in M4. IfVGS1 = VGS2and M1 and M2 are matched, then currents in M1 and M2 are equal. Thus current that M4 sources to M2should equal to the current that M2 requires, causing iOUTto be zero provided that load is negligible. IfVGS1 > VGS2, then ID1 increases with respect to ID2. Since ISS=iD1+ iD2, this increase in iD1 impliesan increase in iD3 and iD4.However iD2 decreases as VGS1 is greater than VGS2. Therefore only way toestablish circuit current equilibrium is for ioutto become positive and voutincreases. IfVGS1 < VGS2, theniout becomes negative and vout decreases. If the currents in current mirror are assumed to be identical,theniOUT can be found by subtractingID2 fromID1. The unloaded differential voltage gain can be foundout by finding the small signal output resistance of the differential amplifier.

rout= 1

gds2+ gds4(20)

Av =vout

vid=

gmdgds2+ gds4

= gm2

gds2+ gds4(21)

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The slew rate performance of the differential amplifier depends upon the value ofISSand the capaci-tance connected from output node to ac ground. The slew rate is given by ISS/C

8 Cascode Amplifier

The cascode amplifier has two distinct advantages over inverting amplifier. First the output impedanceprovided by cascode amplifier is high and second it reduces the effect of the Miller capacitance on theinput of amplifier. In figure 14, simple cascode amplifier is illustrated. The primary function of M2 is to

M3

M2

M1Vin

Vout

1.52V

2.25V

VDD = 3.3V

(a) Simple cascode ampli-fier

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3

VOUT

VIN


Figure 14: CMOS cascode amplifier circuit and VTC

keep the small signal resistance at drain of M1 low. The small signal resistance into the drain of M2 isapproximatelyrds1rds2gm2 while resistance looking into drain of M3 is rds3. The output resistance is theparallel combination ofrds1rds2gm2 and rds3 that is approximately rds3. Compared to inverter amplifierthe output resistance is improved by factor of 2 and thus the gain of amplifier is also improved by factorof 2. From the voltage transfer characteristic of the amplifier it can be seen that the output voltage swingis not rail to rail. The maximum and minimum values of the output voltages are given by,

vout(max) =VDD VSD3(sat) (22)

vout(min) =VDS1(sat) + VDS2(sat) (23)

The small signal voltage gain of cascode amplifier is given by,

voutvin

= gm1gds3

(24)

When the CMOS inverter is driven by the high resistance source, the miller effect essentially places the

capacitanceC2, a capacitance between the input and output node, by the gain form effective input voltagepoint to output and put in parallel to input impedance resulting dominant pole. The miller capacitancecan have negative effects on the circuit in several viewpoints. It creates dominant pole and also provideslarge capacitive load to driver circuits. In case of cascode amplifier the effect of the Miller capacitanceis reduced by keeping the low frequency voltage gain across M1 low, so that the C2 is not multiplied bythe large factor. The effect of the dominant pole is removed in cascode amplifier and this is very useful incontrolling the frequency response of the amplifier.

The small signal gain of the cascode amplifier shown in figure 14 can be increased by increasing theDC current through M1 without changing current in M2 and M3. This can be done by connecting the DCcurrent source between VDD and drain of M1.

9 Current AmplifierThe current amplifiers find many applications in analog signal processing circuits at low supply voltageand in discrete time circuits. The input impedance of the current amplifier is very low while the output

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iout

iin

i1

i2

VDD

M1 M2

(a) Simple

iin i

out

i2

i1

M1 M2

VDD

M4M3

R

(b) Self-bias

ioutiin

i1 i2

i

VDD

M3

M2M1

3

(c) Negative shunt feedback

Figure 15: Current mirror implementation of current amplifier

resistance is very high. The current amplifiers are driven by source with very high impedance and loadedwith very low resistance. There are several advantages of current amplifiers over the voltage amplifiers.The first is that, the current is not restricted by the power supply voltages and thus wider signal dynamicrange may be possible at lower supply voltage. The second advantage is that, -3dB bandwidth of a currentamplifier using negative feedback amplifier is independent of the closed-loop gain.

In figure 15a, simple current mirror implementation of the current amplifier is illustrated that performsreasonably good. The input resistance, output resistance and current gain are given by,

Rin= 1

gm1, Rout=

1

1I2, Ai=

W2/L2W1/L1

(25)

In figure 15b, current amplifier implemented with the help of self biased cascode current mirror is shown.

The cascoding increases the output resistance. However in this case the input resistance is also increasedbecause of presence of the self-biased resistor and that is unwanted effect. Figure 15c shows the currentamplifier implemented using negative shunt feedback. This negative feedback reduces the input impedancebelow the value 1/gm. One of the disadvantages of using negative shunt feedback to achieve low inputimpedance is that at higher frequencies the loop gain will decrease and input impedance increases.

In figure 16a, the symbolic representation of the differential current amplifier is illustrated. Thedifferential input current amplifier input-output relationship is given by,

io= AID iID AICiIC=AID (i1 i2) AIC

i1+ i22

(26)

i1

i2

iic

i

i

i

+

id

ic

2

2

o

(a) Differential input Current Amplifier

i1

i2

io

i1

i2

i2

I 2I I

M1 M2 M3 M4

VDD

(b) Circuit of differential input current amplifier

Figure 16: Differential input current amplifier

were AID is differential current gain and AIC is common mode current gain. In figure 16b, theimplementation of differential input current amplifier is shown. The minimum value of the current source

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should be at least twice the maximum value of thei1 and i2 or higher. The size of the M3 and M4 decidesthe current current gain of the amplifier. If the higher current gain is required then output resistance hasto be modified accordingly.

10 Two Stage Op-Amp

Differential

Transconductance

stage

Compensation

Circuitry

High

Gain

Stage

Bias

Circuitry

Output

Stage

v1

v2

vout

vout

Figure 17: Block diagram of a general Two-stage op amp

In figure 17, block diagram of two stage op amp is illustrated. The first stage is differential transcon-ductance stage which is followed by the high gain stage and output buffer. The output buffer is essentialonly when op amp has to drive a very low impedance load. Ideally the op amp has infinite input resistance,infinite differential gain and zero output impedance. The practical op amp only approaches these values.In figure 18 model of the non-ideal op amp is illustrated. The finite differential input impedance is modeledby Rid and Cid. The output resistance is modeled by the Rout. The common mode input resistance ismodeled by Ricm that is connected from each input terminal to ground. Vos is the input offset voltagenecessary to make the output voltage zero. TheIos, input offset current, is defined as the difference of the

two bias currents IB1 andIB2. Since the CMOS op amp has very high input impedance the bias currentsare approaching zero and thus offset current is almost zero. The common mode rejection ratio (CMRR)is modeled by the voltage controlled voltage source indicated by V1/CMRR. This source approximatesthe effect of the common mode input signal on the op amp. Two sources designated as e2n andi

2n are used

to modeled op amp noise. These rms voltage and current noise sources with unit of mean square voltageand mean square ampere have no polarity and are always assumed to add. The output voltage of the opamp is given by,

*

Ideal

op amp

Ricm

Ricm

Vos

V1

V2 R out

Ricm

en

2

in

2

IB2

IB2

IB2

RidC

id

V1

CMRR

+

+

+

Vout

Figure 18: A model of non ideal op amp

Vout(s) =Av(s) [v1(s) v2(s)] Ac(s)

v1(s) + v2(s)2

(27)

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where, the first term on the right is the differential portion of the Voutand the second term is the commonmode portion of the output. The differential frequency response of the op amp is typically given by,

Av(s) = Av0

s

p1

1s

p2

1s

p3

1 (28)

1

2

3

|Av| dB

0dB

Figure 19: Frequency response of uncompensated op amp

wherep1, p2, p3 ect are the poles of the open loop transfer function. In general a pole designated aspi can be expressed as pi = wi, where wi is the break frequency of pole pi. Av0 is the gain of op ampwhen frequency approaches to zero. In figure 19, typical frequency response of the op amp is illustrated.The frequency 1 is much lower than the rest break away frequencies making 1 dominant influence inthe frequency response. Another characteristic of the non-ideal op amp is the power supply rejectionratio which is defined as the product of the ratio of the change in supply voltage to change in the outputvoltage of the op amp caused by the change in power supply and open loop gain of the op amp. Forthe ideal op amp PSRR is infinite. The input common mode range is the range over which the inputcommon mode signal can vary. The output of the op amp has several limitations. First limitation is

current sink and source. Another limitation is characterized by the slew rate that is rate of change of theoutput voltage with respect to time. The time taken by th output of the op amp to reach its final valueis called the settling time. There are two major architectures of op amp. One is classical two stage opamp and second is folded cascode op amp. Before doing the actual design of op amp, one should knowthe boundary conditions and requirements of op amp. The boundary conditions are process specification,supply voltage and range, supply current and its range, operating temperature and range. The designrequirements are gain, gain bandwidth, settling time, slew rate, phase margin, ICMR, CMRR, PSRR,output resistance, offset voltage, noise and layout area. For the frequency compensation of the op ampfeedback and feed-forward methods are developed.

VBias

CC

LCVin

VDD

M4M3

M5

M1 M2_

+

+

_

M6

M7

VSS

R

Figure 20: Classical Two stage opamp

Op amps are generally used in negative feedback configuration. In this way, the relatively high,

inaccurate forward gain can be used with feedback to achieve a very accurate transfer function that isfunction of only feedback elements only. In figure 21 the general negative feedback configuration of op ampis shown. A(s) is the open loop gain of op amp and F(s) is the feedback path gain. The loop gain of the

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F(s)

A(s)

_

+ V (s)in V (s)out

Figure 21: Negative feedback configuration of op amp

system is given by L(s) = -A(s)F(s). In order to system be stable following conditions must be satisfied.

|A(j0)F(j0)| 0 (30)

where, 0 is called the phase crossover frequency and it is a frequency when phase becomes 0 . 0dB iscalled the gain crossover frequency, the frequency at which the magnitude of the system becomes unity.Larger phase margin results in less ringing of the output signal. Too much ringing can be undesirable,so it is important to have adequeate phase margin that keeps the ringing of the output signal underdesired level. It is desired to have phase margin of at least 45 while 60 phase margin is preferred in manyapplications. In figure 22a equivalent small signal model of the uncompensated op amp is illustrated. The

gmIvin

CI IR gmIIv1 RII CIIvin vout

v1

+

+

(a) Small signal model of uncompensated op amp

gmIvin

CI IR gmIIv1 RII CIIvin vout

v1

R zCc

+

+

(b) Small signal model of compensated op amp

Figure 22: Differential input current amplifier

poles of this system are given by p1 = 1/RICI and p2 = 1/RIICII.The feedback compensation technique is also known as the miller compensation technique. In this tech-

nique the compensation capacitorCCis connected between the output and input of the second transcon-ductance stage. The resultant location of the poles are given by the

p1

= 1gmIIRIRIICC

(31)

p2

= gmIICCCICII+ CIICC+ CICC

gmIICII

(32)

Here, it is assumed that CII is much greater thanCI andCC is greater than CI. The location of the zerois given by,

z1 = gmII

CC(33)

This zero is located on the right hand side of s-plane. The task of the op amp compensation includesmoving poles and zeros other than dominant pole(p1) away from the origin of s-plane that results indesired effect of phase shift as shown in figure. The dominant pole is also called the Miller pole. The unitygain bandwidth of the compensated op amp is given by GB gm2/CC. It can be shown that if the zerois placed at least ten times higher than GB, then in order to achieve 60 phase margin, the second pole p2must be placed at least 2.22 times higher than GB. The right hand zero resulting from the feed-forwardpath through the compensation capacitor tends to limit the GB that might otherwise be achieved if thezero was not present. There are several ways to eliminate the effect of this zero. The simplest way is toinsert nulling resistor in series with CC. The small signal model of the resulting circuit is illustrated infigure 22b. The location of the new zero is given by,

z1 = 1

CC(1/gmIIRz) (34)

This shows that the value ofRZcan control the location of the zero. If the z1 is placed exactly on thep2, then the effect of the both z1 and p2 can be eliminated. The effect of the remaining poles remainspresent.This compensation concept is used widely in design of two sate op amp.

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11 Cascode Op-Amp

VBias

VBias

Vin

2

Vin

2

VO1

VDD

M3 M4

MC3 MC4

MC1 MC2

M1 M2

M5

R

+ _

_+

(a) Cascode in first stage

VBias

CC

LCVin

VDD

M4M3

M5

M1 M2_

+

+

_

M6

MC7

M7

VSS

VBN

VBP

R

MC6

(b) Cascode in second stage

Figure 23: Two stage cascode op amp

The two stage op amp mentioned in previous section is used widely. However its performance does notmeet the requirements of certain applications. The performance limitations of two stage op amp op ampincludes insufficient gain and bandwidth. The gain of the two stage op amp can be increased by (1) addingadditional gain stages, (2) increasing transconductance of first or second stage (3) increasing the outputresistance of first or second stage. Since the first stage suggests to increase the number of gain stage, itdoes not seem attractive. The third approach is more attractive because increasing output resistance ismore power efficient than increasing the transconductance. The cascode amplifiers utilize third approach

to increase gain. The increase in gain is possible by increasing output resistance of first or second stage.In figure 23a shows cascode op amp in which the gain is improved by improving the output resistance offirst stage. The transistors MC3 and MC4 increases the output resistance of the first stage. The outputresistance of the first stage is given by,

RI= (gmC2rdsC2rds2) || (gmC4rdsC4rds4) (35)As the output resistance is improved by the factor of two, the gain will also improve by the factor of

two. In figure 23b cascode amplifier with cacoding in second stage is illustrated. The output resistance ofthe second stage in this case is given by,

RII= (gmC6rdsC6rds6) || (gmC7rdsC7rds7) (36)With compared to standard two stage op amp, it is possible to improve the gain by up to factor of 100.

However the it decreases the stability of the system and increase the output resistance of the op amp.These both are undesired effects, thus trade off between the stability and gain has to be considered.

12 Comparators

A comparator is a circuit with binary output which depends upon the comparison of two analog inputsignals. In figure 24b, transfer curve of ideal comparator is illustrated. Mathematically, the comparatorcan be modeled as the voltage controlled voltage source. The output of the comparator is high (VOH) whenthe difference of the analog input signal is positive, otherwise the output is low(VOL). The ideal comparatorhas infinitely high gain. In figure 24c, the transfer curve of comparator with finite gain is illustrated. VIHand VIL represents the input voltage difference VP VNneeded to saturate the output comparator at itsupper and lower limit respectively. Another non-ideal effect in comparator is offset voltage. If the outputdid not change until the input difference reached a value VOSthen the difference would be defined as offsetvoltage. If the offset voltage is constant then it is not a problem, but it varies randomly from circuit tocircuit and thus difficult to predict exact value of the offset voltage. The delay is present between the input

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ov

pv

v n

(a) Comparator Symbol

VOH

VO

VP VN

VOL

(b) Transfer characteristic of Ideal com-parator

VOH

VO

VP VN

VOL

VIL

VIH

(c) Transfer characteristic of compara-tor with finite gain

VOL

VOH

Vout

VINVTRP

VTRP+

(d) Transfer characteristic of compara-tor with hysteresis

Figure 24

voltage excitation and output response. This delay is called the propagation delay. The ideal comparatorhas zero propagation delay. The propagation delay affect the speed of operation or response adversely.

VBias

Vin

Vin

Vout

+

+

VDD

VSS

M1 M2

M3 M4

M5 M6 M7

M8

M9

(a) Clamped Push-pull output comparator

Vin

Vin

1

2

2

1

1

Vos VoutCAZ+

+

(b) Offset auto zero technique

Figure 25

Simple two stage op amp operating in open loop configuration can be used as a comparator. Howeversuch simple comparator suffers from the problems of propagation delay due to transition of the output offirst stage and second stage. To overcome this problem clamped comparator as shown in figure 25a can beused instead of simple two stage op amp. In clamped comparator, diode connected transistor is used inplace of mirror connected load. This reduces the gain, but it makes push pull output stage and increasingcurrent sink and source capacity of the output. The lower gain of this comparator can be compensatedby providing cascoding in output.

For precision applications such as high resolution ADC, large input offset voltage cannot be toleratedand design of the comparator becomes very difficult task. In order to overcome the problem of input offsetvoltage, auto-zeroing technique as illustrated in figure 25b can be used. The task of the comparison isdone in two phases. During the first stage switch1 is close while switch 2 is opened. In second stage,switch2 is closed and 1 is opened. In first phase, the capacitorCAZ is charged to value same as theinput offset voltage with polarity as shown in figure 25b. In second phase the input voltages are appliedto the comparator. The polarity of the voltage across capacitorCAZ is in such a way that it cancels theinput offset voltage. The switches in CMOS technology can be implemented either with the help of single

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mos transistor or transmission gate.

inv

ov

1R

2R

(a) Hysteresis using external positivefeedback

Ibias

Vin1Vout

Vin2M1 M2

M3

M9

M11

M4M6 M7

M5

M8

M10

M12

(b) Hysteresis using internal positive feedback

Figure 26

If high speed comparator is placed in noisy environment to detect the signal around its threshold, thendue to large noise, the output becomes very. In such situation, the hysteresis is needed in the characteristicof the comparator. The transfer characteristic of comparator with the hysteresis is illustrated in figure24d. In figure 26a, the comparator with hysteresis is shown. In this circuit external positive feedback isused to implement the hysteresis. In figure 26b, the comparator with output stage is illustrated that usesinternal positive feedback.

13 Digital-Analog Converter

Voltage

Reference

Scaling

Network

Output

Amplifier

Binary Switches

b0 b2b1 bN1

VREF DV REFVOUT

(a) General Block Diagram of DAC

Serial Parallel

ChargeCurrent Voltage

Voltage and Charge

DigitalAnalog Converters

Charge

Slow Fast

(b) Classification of DAC

Figure 27

Digital-Analog converter converts the digital data into equivalent analog signal. In figure 27a, block

diagram of the DAC is illustrated. The output voltage of the DAC is given by,

VOUT =K VREF

b021 + b12

2 + + bN12N

(37)

The number of bits that can be applied at the input of the DAC is called resolution and it is expressedin terms of the bits. For each input word, there is an unique output. The output levels are separatedby LSB. Thus LSB can be given by as VREF/2

N. When the input word is increased by one, the outputof DAC is increased by LSB. The full scale value of DAC is defined as th difference between the analogoutput for the largest word and analog output for smallest digital word. The dynamic range of DAC isthe ratio of full scale range to LSB. In decibels dynamic range is given by 6.02N, where N is resolution ofDAC. Integral nonlinearity (INL) for DAC is the maximum difference between the actual finite resolutioncharacteristic and ideal finite resolution characteristic measured vertically. Integral Nonlinearity can beexpressed as a percentage of full scale range or in terms of the least significant bit. Differential non-linearityis the measure of separation between adjacent levels measured at each vertical jump.

In figure 27b, broad classification is illustrated. This classification is based on the mode of digital inputand the methods utilize for the conversion. In figure 28, general block diagram of the current scaling DAC

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I0

I1

I2

N1I

REFV Current

Scaling

Network OUTV

FR

Digital Input Word

Figure 28: Block diagram of current scaling DAC

is shown. Here, VREF is converted into the set of the binary weighed currents. These binary weighedcurrents are summed up to generate the output voltage. The general equation of output voltage for suchDAC is given by,

VOUT = RFiout= RF(I0+ I1+ I2+ + IN1) (38)

outV

Iout

REFV

I0 I1 I2 IN1

2N1

R

KR

R 2R 4R

Figure 29: Binary weighed resistor DAC implementation

The current scaling network can be implemented in different ways. The simplest way is to use network ofbinary weighed resistors as shown in figure 29.The advantage of binary weighed network is the insensitivityto parasitic capacitance and thus very fast. However the values of resistor required are spread over widespan. For N bit DAC the ratio of largest value resistor to smallest value resistor is 2N1. If the value ofMSB resistors are not accurate then the performance of DAC is very poor.

outV

REFV

0S 1S 2S N1S

I0I1 I2

Iout

KRR R R

2R 2R 2R 2R

Figure 30: R-2R resistor DAC implementation

The requirements of the large value resistors can be overcome by using R-2R ladder network as shownin figure 30. This network uses the resistor of only two values R and 2R. These resistor values can beimplemented easily with the help of three equal valued resistors. The value of currents shown in figure 30is given by,

I0 = VREF

2R , I1 =

VREF4R

, , IN1 = VREF2NR

(39)

The DAC implemented with R-2R ladder is also as fast as binary weighed DAC structure.The third way of implementing the current scaling structure is to use binary weighed current sinks.

The binary weighed current sinks can be implemented with the help of MOSFETs. If the width andlength of the MOSFETs are adjusted properly then proper ratio in the value of the current sinks canbe obtained. However the matching requirements of the transistors must be satisfied in order to have

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better performance. To increase conversion speed current sinks can be implemented with the help of BJTtransistors instead of MOSFETs.

V1

V2

V3

2NV

Scaling

Voltage

Network

Decoder

LogicVREF VOUT

Digital Input Word

Figure 31: Block diagram of Voltage Scaling DAC

In figure 31, general block diagram of the voltage scaling DAC is illustrated. The voltage scalingnetwork converts the VREF into binary weighed voltages and decoder connects one of these voltages to

output. Since structure of voltage scaling DAC is very regular, it is used widely in MOS technology. Thearea requirements of such DAC is more if the number of bits are 8 or more. This structure suffers fromthe parasitic capacitance present at each voltage tapping.

0S 1S 2S N1S

outV

REFV

2

2

2

2

1

c

2

c

2

c

2N1c

Figure 32: Charge Scaling DAC implementation

In figure 32, the implementation of the charge scaling DAC is shown. The conversion is done in twophases and non-overlapping clocks are used. During 1, the top and bottom pates of DAC are groundedand in phase 2, the capacitors are either connected to ground and VREFdepending upon the input bits.Since the capacitors are binary weighed, the output is given by,

VOUT =VREF

b021 + b12

2 + + bN12N

(40)

The performance of this DAC is limited by the accuracy of the capacitors and their values. In MOStechnology, since the capacitance ratio with accuracy of 0.1% can be provided, the DAC of 10-bits arepossible with this structure.

14 Analog-Digital Converter

Prefilter Sample/Hold Quantizer Encoder y(kT)x(t)

Figure 33: General block diagram of ADC

In figure 33, general block diagram of ADC is illustrated. The pre-filter is also known as the anti-aliasingfilter, which is a low pass filter and removes the higher frequency components from the input signal. Thepresence of this filter avoids aliasing of higher frequency components back to base band. The anti-aliasingfilter is followed by the sample and hold circuit. The sample-hold circuit samples and maintains the levelof the input analog signal for the certain period of time generally known as the conversion time. The

conversion is accomplished by quantizer. Generally quantizer has 2N subranges, where N is the numberof bits of output. The quantizer is followed is followed by the encoder, that encodes the output of thequantizer. Within conversion time analog input is converted in digital word.

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According to Nyquist rate, to avoid anti-aliasing, the sampling rate fSmust be twice the bandwidthfBof the signal. To increase the bandwidth of the ADC, 0.5fSshould be very close tofB. But this requires thepre-filter with very sharp response. The ADCs those work this principle are known as Nyquist ADC. TheADCs which sample the input signal at much higher rate than Nyquist rate are called over sampled ADCs.The resolution of ADC is the smallest analog range that can be distinguished by the ADC. Resolution may

be expressed with respect to full scale but it is typically given in the numbers of bits N, where convertedsignal has 2N possible output stages.

refV

inV intV

thV

Positive

Integrator

Digital

Control

Counteroutputcarry

Binary output

Figure 34: General block diagram of dual-slope adc

The serial ADC performs the operation until the conversion is completed. In figure 34, dual slope ADCis shown. First the input charges the integrator for fixed amount of time. So depending upon the valueof the input signal, integrator is charged. ThenVREF discharges the integrator. SinceVREF is constant,discharge rate of integrator is constant for all value of input, so discharge time depends upon the value ofthe input signal. The digital control block allows counter to run for the discharging time. So dependingupon the value of input, output of counter is set. Such ADCs are slow, but provides very high resolution.Typical values for such serial ADCs are conversion frequencies less than 100Hz and resolution greater than12bits.

Output

Register

SAR

LogicVRef

Vin

DAC Clock

Output

Figure 35: Block diagram of SAR adc

In figure 35, general block diagram of the successive approximation ADC is illustrated. In this ADC,the conversion is done in N discrete steps, where N is the resolution of the ADC. In each step one bit ischanged, the resultant digital word is converted to analog signal with help of the DAC for comparing itwith input signal. Depending upon the output of comparator, during next successive step, another bit ischanged. Such ADCs are medium speed and used very widely. As the resolution of such ADC increases,the conversion time also increases.

The flash or parallel ADCs are the fastest ADC. In flash ADC, input signal is directly compared withdifferent voltage level parallel. The different voltage levels are generated from the VREF voltage andresistive network. In such ADCs, for parallel comparison, 2N comparators are needed, where N is theresolution of the ADC. So as the resolution of ADC increases, design of flash ADC becomes challenging.Another challenge is to generate accurate set of different voltage using resistive network. With flash ADCof 8-bit sampling rate of 1G and even more can be achieved.

The problems encountered in designing flash ADC with higher resolutions can be overcome in foldingADC. The folding ADC is one type of pipelined ADC in which the input is split into two parallel path. Onepath consists of course quantizer which converts input into 2N1 values and generates N1 bits. In secondpath input is folded into single subrange and converted into 2N2 stages using fine quantizer that produces

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Analog

Input

Folding

Processor

Fine

Quantizer

Coarse

QuantizerEncoding

Logic

Digital

Output

Processor

Figure 36: Block diagram of folded ADC

DeltaSigma

Modulator

Decimation

FilterI/P O/P

Figure 37: Block diagram of delta-sigma ADC

N2 bits. The en-coder combines these two output into single digital word of N1+N2 bits. For 6 bit flashADC 63 comparators are needed but for folded ADC if N1=2 and N2=4, then only 18 comparators are

needed. The advantage of the folding ADC is that the power consumption and area requirements are lesscompared to flash ADC with almost same conversion speed.The Delta-Sigma ADC is example of oversampled ADC. In this case sampling rate is much higher than

the nyquist sampling rate. Such ADC is also known as the noise shaping ADC. Depending upon the oderof the delta-sigma modulator used in ADC, quantization noise is shifted toward higher frequencies whichis filtered latter by the low pass filter providing better conversion. In figure 38, first order delta-sigmamodulator is illustrated. Usually first and second order delta-sigma modulators are used in ADCs. Theoutput of Delta-sigma modulator is bit stream which is converted in to digital word with the help of thedecimation filter. The decimation filter has comb filter like response.

Integrator

1bit DAC

1bit ADCInput O/p+

Figure 38: Delta-Sigma Modulator

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15 References

1. Book : CMOS Analog Circuit Design, Second Edition, Philip Allen, Douglas Holberg, Oxford Uni-versity Press, ISBN-10: 0-19-806440-3

2. Book : Design of Analog CMOS Integrated Circuits, Behzad Razavi, Tata McGraw-Hill

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