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GSM MODEM (GL865 DUAL) INTEGRATION WITH

ARM LPC810 CORTEX FOR SURVEILLANCE

APPLICATION AND VALUE ENGINEERED POWER

MANAGEMENT

Produced by:

SALEEM, Muhammad Umair

Masters of Electrical Engineering

Matriculation Number 25279

HS-Weingarten

Supervising Professor:

Prof. Dr.-Ing. Andreas Siggelkow

Professor fr Elektrotechnik und Elektronik

Hochschule Ravensburg-Weingarten

Submission date: 2nd JUNE 2014

Faculty of Electrical Engineering Department

Masters of International Engineering Program

Scientific project for Summer Semester 2014

SS2014

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PREFACE AND ACKNOWLEDGMENT

The motivation for this project based on surveillance application for vehicles and private possessions

was provided by Prof. Dr.-Ing. Andreas Siggelkow. From the inception of this idea to the completion,

Prof. Dr.-Ing. Andreas Siggelkow has been really instrumental and helpful in certain ideas and

problem solving solutions for corroboration of system design. On the other hand, technical support

was provided by Dipl. Ing. (FH) Christoph Weber at different points in the entire life of this project.

And lastly, my appreciation goes to the Electrical department laboratories for providing instrumental

support, crucial to putting together the system in the first place.

To all the above mentioned personnel and department, I present my humble gratitude and I am

grateful to have you as my senior instructors.

SALEEM, Muhammad Umair

Masters Electrical Engineering

Matriculation number 25279

Engineering project for SS2014

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CONTENTS

1. Introduction ____________________________________ 4

2. Requirement analysis __________________________ 4

3. Specification ____________________________________ 4

3.1. LPC 810 ARM cortex ______________________ 4

3.2. GPS sensor MT3329 ______________________11

3.3. GSM modem GL865 telit dual _____________16

3.4. Telit software user guide _________________28

3.5. Power supply units ______________________31

3.6. Quad tri-state buffer ______________________34

4. Schematic diagram of the system _________________37

5. Hardware of the system __________________________38

6. Further improvements ___________________________39

7. Bibliography ____________________________________39

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1- INTRODUCTION

The requirement of the construction of an apparatus that tracks on basis of GPS specifications is a

well-established product of the current consumer lobby in high end policy insurance for security,

tracking for monitoring basis or etc. the acquisition of data performed requires a simple GPS satellite

receiver apparatus which relays data over to the controller unit for control of program logic, where its

decided upon further parameters as to how it should be dealt with and finally, the data is relayed over

the GSM modem via an asynchronous serial receiver and transmitter. The report presented here is to

further provide insight into the general method prescribed above is carried out.

2- REQUIREMENT ANALYSIS

The requirements of the project are outlined as to receive the coordinate specified data from the GPS

satellite receiver antenna and transmit it to the handy as a proper structured text message. However

a lot more goes into this work. Here a brief summarization of the very top level of design management

for the project will be provided so as to create a picture of data reception and transmission from GPS

modem to the handy.

The GPS coordinates are received via the MTK 3329 satellite receiver antenna. A lot more detail

about the specification of operations of the satellite receiver antenna are provided below. The data

acquisition done from this stage is of the GPRMC packet. For reasons defined in detailed in the

specification section of the receiver, it will be mentioned why the GPRMC provides a better standoff

alternative as compared to the 3D-fix technique. The hub of the tracking apparatus can be very well

the 74LS125 tri-state quad buffer. The functionality of the tri-state buffer is to get programmed with

the GPIO ports of the LPC810 controller and provide for a queue session for buffering data received

from the antenna and storing it in the LPC array, and finally relaying it over to the GPS modem on

timely delays, via the UART. It is at this point that the AT commands are engaged for the GPS

modem and data is relayed over to the handy via the telecommunication provider (SIM carrier)

resource.

3- SPECIFICATION

Specification details along with the functionality usage and the program coding chunks will be

provided in this section of the report. The order of specification is selected as to the novelty of the

model, followed by their functional description.

3.1- LPC 810 ARM CORTEX

The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU

frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM.

The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to

three USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up timer, and state-

configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input

pattern match engine, and up to 18 general-purpose I/O pins.

The features and benefits as described by this cortexs user manual are as followings:

System features include:

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ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and

fast single cycle I/O port. Built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug

(SWD) and JTAG boundary scan modes supported. And Micro Trace Buffer (MTB) supported.

Memory support of Up to 16 kB on-chip flash programming memory with 64 Byte page write and

erase. And Up to 4 kB SRAM.

ROM API support:

Boot loader.

USART drivers.

I2C drivers.

Power profiles.

Flash In-Application Programming (IAP)

In-System Programming (ISP).

Digital peripherals include:

High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter.

High-current source output driver (20 mA) on four pins.

High-current sink driver (20 mA) on two true open-drain pins.

GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

Switch matrix for flexible configuration of each I/O pin function.

State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix.

Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.

Self-Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.

CRC engine.

Windowed Watchdog timer (WWDT).

Serial interfaces:

Three USART interfaces with pin functions assigned through the switch matrix.

Two SPI controllers with pin functions assigned through the switch matrix.

One I2C-bus interface with pin functions assigned through the switch matrix.

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The LPC 810 cortex MCU comes in several packages, out of which the one employed here will be the

DIP08

A block diagram for the general cortex ARM MCU is given as follows:

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Pining of the DIP:

Pining information in line with the DIP08 packing module is as follows

One of the most important and novel features to the ARM LPC cortex MCU is the switch pin matrix

tool. This tool, as provided with in the IDE or SDK can help alter or change the functional aspects of

allowable GPIO pins in line with the functionality required.

Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible

way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin

that is not power or ground. These functions are called movable functions and are listed in detail in

the datasheet and are used according to application specifications. Functions that need specialized

pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch

matrix.

These functions are called fixed-pin functions and cannot move to other pins. If a fixed-pin function is

disabled, any other movable function can be assigned to this pin. The table describes in detail the

assignment to the various pins as opposed to the vector interrupt setting or the general purpose I/O

setting for configurations.

Alongside this table in the IDK, there exist corresponding hex files for the respective pin assignment

as well. Another feature of the LPC expresso IDK is the switch pin matrix tool. This tool is essentially

a GUI (graphic user interface) designed for ease of assignment for the pin declaration as described a

little earlier.

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The interface for the switch pin matrix tool in the expresso is given as under:

Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight external

interrupts connected to the NVIC. The pattern match engine can be used, in conjunction with

software, to create complex state machines based on pin inputs. Any digital pin, independently of the

function selected through the switch matrix, can be configured through the SYSCON block as input to

the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match

engine are located on the IO+ bus for fast single-cycle access.

A few features are provided as under:

Up to eight pins can be selected from all digital pins as edge- or level-sensitive

Interrupt requests. Each request creates a separate interrupt in the NVIC.

Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

Level-sensitive interrupt pins can be HIGH- or LOW-active.

Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and power-down mode.

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Up to 8 pins can be selected from all digital pins to contribute to a Boolean expression. The Boolean expression consists of specified levels and/or transitions on various combinations of these pins.

Each min-term (product term) comprising the specified Boolean expression can generate its own, dedicated interrupt request.

This is the point which naturally leads us to the discussion of the UART in the LPC cortex. The

LPC81X series makes use of the UARTs for serial transmission of data. The data is transmitted as a

serial 8 bit data. The use of UART in cortex ARM MCU is used for the propagation of GPRS -

$GPRMC data protocol along the usb over serial UART.

UART for ARM:

All UART functions are movable functions and are assigned to pins through the switch matrix.

Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except PIO0_10 and PIO0_11.

7, 8, or 9 data bits and 1 or 2 stop bits

Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option.

Multiprocessor/multi-drop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.)

Parity generation and checking: odd, even, or none.

One transmit and one receive data buffer.

RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output.

Received data and status can optionally be read from a single register

Break generation and detection.

Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

Built-in Baud Rate Generator.

A fractional rate divider is shared among all UARTs.

Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.

Separate data and flow control loopback modes for testing.

Supported by on-chip ROM API.

Some other fascinating and novel characteristics of the LPC 81X series is the SPI/O is also an

integral part of the LPC 81X cortex. All SPI functions are movable functions and are assigned to pins

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through the switch matrix. Comes with a Master and slave operation. Data can be transmitted to a

slave without the need to read incoming data. This can be useful while setting up an SPI memory.

This is feature is followed up by the I2C bus application. However this portion is not required and not

utilized in this prevailing project, but the extension of this project into GSM add-ons may possible

make use of such advantageous features. So for the lack of interest at this stage, they will not be

discussed here in detail. However it is assumed that the reader of this report knows the basic

ideology of the I2C application which is merely synchronization of system clock with data lines for

transmission.

The values given as under the limiting factors are the governing factors for the supply voltage as well

current.

Given below is the table from the data sheet, which includes these factors:

The operating stance of the FTDI and the LPC cortex are within the maximum limit range. So for the

application purpose described at length here, the current and voltage parameters do not necessarily

effect the overall performance of the system.

The interrupt handler for the UART is described as under for the serial receiving of data from the GPS

module and the serial transmission along the lines of the usb over serial protocol of the FTDI

breakout board.

The code for UART interrupt handler taken from the Expresso suit is as follows:

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void UART0_IRQHandler(void) { unsigned char temp=0; temp = LPC_USART0->RXDATA; if(mydevice_stat.GPS)//mydevice_stat.GPS==1 | mydevice_stat.GPS=0 { if(!myFlags.serial_data_recvd) { if(temp=='$') myFlags.start_filling=1; if(myFlags.start_filling) { myreg.buffer[myreg.counter]=temp; myreg.counter++; } if(temp==0x0A)//actual check WILL BE on 0x0A { myFlags.start_filling=0; myreg.counter=0; myFlags.serial_data_recvd=1; } } }

3.2- GPS SENSOR MT3329

The GlobalTop FGPMMOPA6C is an ultra-compact POT (Patch On Top) GPS Module, The module utilizes the MediaTek new generation GPS Chipset MT3339 that achieves the industrys highest level of sensitivity (-165dBm ) and instant Time-to-First Fix (TTFF) with lowest power consumption for precise GPS signal processing to give the ultra-precise positioning under low receptive, high velocity conditions.

Up to 12 multi-tone active interference canceller (ISSCC2011 award), customer can have more

flexibility in system design. Supports up to 210 PRN channels with 66 search channels and 22

simultaneous tracking channels, FGPMMOPA6C supports various location and navigation

applications, including autonomous GPS, SBAS(note) ranging (WAAS, EGNO, GAGAN, MSAS),

AGPS.

FGPMMOPA6C is excellent low power consumption characteristic (acquisition 82mW, tracking 66mW), power sensitive devices, especially portable applications, need not worry about operating time anymore and user can get more fun.

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GPS SoC MT3329

The FGPMMOPA6 is a POT (Patch On Top) GPS Module. This GPS receiver provides a solution that

has high position and speed accuracy as well as high sensitivity and tracking capabilities in urban

conditions. It supports NMEA 0183 and PMTK protocol.

Features

Sensitivity : Acquisition -148 dBm , Tracking -165 dBm

Position Accuracy : Without aid: 3.0 m (50% CEP) DGPS (SBAS(WAAS,EGNOS,MSAS)): 2.5 m (50% CEP)

TIFF(Time to First Fix) : Cold Start:

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Consider deriving the following data frame from the GPS sensor module:

$GPRMC,064951.000,A,2307.1256,N,12016.4438,E,0.03,165.48,260406,3.05,W,A*2C

This format consists of many frames and one such frame is RMC (GPS Fix Data, fixed data for the Global Positioning System). The RMC data set contains information on time, longitude and, void and active locking field.

This sensor captures the GPS signal from the satellite and converts it to a special data format. This format is standardized by the National Marine Electronics Association (NMEA) to ensure that data exchange takes place without any problems.

Data retrieval is done via the LPC with the following check parameter:

unsigned char acq_gps() { unsigned char valid_result=0; while(!myFlags.serial_data_recvd); if(myreg.buffer[1]=='G' && myreg.buffer[2]=='P' && myreg.buffer[3]=='R' && myreg.buffer[4]=='M' && myreg.buffer[5]=='C') {

..

System Block Diagram

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For simplicity of design and keeping the footprint as less minimalistic as

possible the only useful outputs derived from the GPS sensor on chip is

the TX

Pin Assignment

Pin Name I/O Description

1 VCC PI Main DC power input

2 NC Not connected

3 GND P Ground

4 VBACKU

P

PI Backup power input

5 3D-FIX O 3D-fix indicator

6 1PPS O 1PPS Time Mark Output 2.8V CMOS Level

7 NC Not connected

8 GND P Ground

9 TX O Serial data output of NMEA

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10 RX I Serial data input for firmware update

11 GND P Ground

12 GND P Ground

13 GND P Ground

Although the FGPMMOPA6C comes in a SoC form already as it is

dispatched by the manufacturers. But it is crucial at this point to examine the various pin assignments

that could very well expand upon the possibility of the same module being used as something more

elaborate when it comes to describing the user functionality as a complete marketable product in

design and production phase.

As mentioned before, the only output taken from the aforementioned module is the TX. This decision

although has no pre-conceived notion other than to reduce the bare effective footprint used and

streamlined functionality of the desired output. However the VCC back up , 1PPS and the built in

EASY control i.e. the 3D-FIX output can also be used as an extension for a complete and robust

solution to all the possible application notes as provided by the manufacturer.

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3.3- GSM MODEM GL865 TELIT DUAL

Product Overview The new GL865-DUAL/QUAD product introduces the smallest GSM/GPRS Leadless-Chip-Carrier (LCC) module in the market. The GL865-DUAL/QUAD incorporating a single-chip solution built on SMD technology into a 24,4 x 24,4 x 2,7 mm block. The low profile and small size of the unique LCC package for the GL865-DUAL/QUAD enable the design of extremely compact applications. Since connectors are eliminated, the solution cost is significantly reduced compared to conventional mounting. With its ultra-compact design and extended temperature range, the Telit GL865-DUAL/QUAD product is the perfect platform for high-volume m2m applications and mobile data devices. Additional features such as integrated TCP/IP protocol stack and serial multiplexer extend functionality of the application at no additional cost. The Telit GL865-DUAL is dual band GSM/GPRS module in 900 and 1800 MHz. The Telit GL865-QUAD is Quad band GSM/GPRS module in 850/900/1800/1900 MHz. Moreover, the Telit GL865-QUAD is compliance with e-Call European directive. The GL865-DUAL/QUAD makes it possible to run the customer's application inside the module using Python Script Interpreter, thus making it the smallest, complete platform for m2m solutions. The GL865-DUAL/QUAD module, support Over-the-Air firmware update by means Premium FOTA

Management. By embedding the RedBends vCurrent Mobile agent, a proven and battle-tested

technology powering hundreds of millions of cellular handsets world-wide, Telit is able to update its

products by transmitting only a delta file, which represents the difference between one firmware

version and another.

Product Features

GL865-DUAL: Dual-band EGSM 900 / 1800 MHz

GL865-QUAD: Quad-band EGSM 850 / 900 / 1800 / 1900 MHz

GSM/GPRS protocol stack 3GPP Release 4 compliant

Output power

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o Class 4 (2W) @ 850/900 MHz o Class 1 (1W) @ 1800/1900 MHz o Control via AT commands according to 3GPP 27.005, 27.007 and Telit custom AT

commands

Control via Remote AT commands

Power consumption (typical values)

o Power off: 62 uA o Idle (registered, power saving): 1.6 mA @ DRX=9

Serial port multiplexer 3GPP 27.010

SIM Application Toolkit 3GPP TS 51.014

SIM Access Profile

eCall Compliant (only GL865-QUAD)

Extended Supply voltage range: 3.22 4.5 V DC (3.8 V DC nominal)

TCP/IP stack access via AT commands

Interfaces

Analog audio (balanced)

Digital Voice Interface

2 A/D plus 1 D/A converters

Buzzer output

ITU-T V.24 serial link through CMOS UART: o Baud rate from 300 to 115.200 bps o Auto-baud up to 115.200 bps

SMS

Point-to-point mobile originated and mobile terminated SMS

Concatenated SMS supported

SMS cell broadcast

Text and PDU mode

SMS over GPRS

GSM Supplementary Services

Call forwarding

Call barring

Call waiting & call hold

Advice of charge

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Calling line identification presentation (CLIP)

Calling line identification restriction (CLIR)

Unstructured supplementary services mobile originated data (USSD)

Closed user group

The user interface

The user interface is managed by AT commands according to ITU-T V.250, 3GPP 27.007 and 27.005

specifications. Moreover, custom AT commands are also available. Please refer to the AT Command

User Guide for details.

SIM Reader The GL865-DUAL/QUAD supports phase 2 SIM at 1.8V and 3V ONLY with an external SIM

connector. For 5V SIM, an external level translator can be added.

The GL865-DUAL/QUAD supports the following SMS types:

Mobile Terminated (MT) class 0 3 with signaling of new incoming SMS, SIM full, SMS read

Mobile Originated class 0 3 with writing, saving in SIM and sending

Cell broadcast compatible with CB DRX with signaling of new incoming SMS. The GL865-DUAL/QUAD also supports SMS over GPRS

AT Commands The Telit GL865-DUAL/QUAD module can be driven via the serial interface using the standard AT commands. The Telit GL865-DUAL/QUAD module is compliant with:

Hayes standard AT command set, in order to maintain the compatibility with existing SW programs.

3GPP 27.007 specific AT command and GPRS specific commands.

3GPP 27.005 specific AT commands for SMS (Short Message Service) and CBS (Cell Broadcast Service)

Moreover the GL865-DUAL/QUAD module supports also Telit proprietary AT commands for special

purposes.

Interface boards and evaluation kits.

The telit GSM modems are poised to work with the factory and manufacturer provided interface

boards. A complete series of collections available for choosing is available in the criterion for the

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respective telit chip utilized for this purpose. More information on this topic can be acquired via the

telit product specification website. Where the complete catalogue of interface boards in present.

For our project we will be utilizing the GL865 interface board, without the EKV2 evaluation board. This

was chosen to be a valid solution because of no usage of I2C and I2S busses for voice and digital

voice interfacing. This will result in providing a main supply and utilizing only the serial outputs

provided by the interface board as its specifications writing in the data sheet.

Antenna

The antenna connection and board layout design are the most important aspect in the full product

design as they strongly affect the product overall performances,

Frequency range 880-960 MHz GSM900 band 1710-1885MHz MHz DCS1800 band

Gain 1.4dBi @ GSM900 and 3dBi @ DCS1800

Impedance 50 Ohm

Input power > 2 W

VSWR absolute max 10:1 (limit to avoid permanent damage) VSWR recommended 2:1 (limit to fulfil all regulatory requirements)

The other feature of antenna as taken from the telit hardware guide is the matching over the smith

chart to provide a 50 ohm antenna with matching resistance for no loss in transmission.

A smith chart stating the matching is provided below from the user guide of telit:

Reset signal

RESET* is used to reset the GL865. Whenever this signal is pulled low, the GL865 is reset. When the device is reset it stops any operation. After the release of the reset GL865 is unconditionally shut down, without doing any detach operation from the network where it is registered. This behavior is not a proper shut down because any GSM device is requested to issue a detach request on turn off. For this reason the Reset signal must not be used to normally shutting down the device, but only as an emergency exit in the rare case the device remains stuck waiting for some network response.

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The Reset is internally controlled on start-up to achieve always a proper power-on reset sequence, so

there's no need to control this pin on start-up. It may only be used to reset a device already on that is

not responding to any command.

Hardware Specifications

Although it goes without saying that the GL865 telit module for GSM/GPS is capable for functionality

on basis of many a parameters. Considering the fact that this chip is marketed as a complete solution

to the real world manufacturing line mobile telephony solution which brings as no surprise the

inclusion of on chip SPI, I2C and I2S busses for there respective utilization. Along with the inclusion

of battery management for standby mode and respective AT command responsive hardware aspects.

However the utilization for this project is made to use the simple serial output rails, bypassing the I2C

buss and the standby mode for battery management which will be replaced by a different finite state

machine logic for controlling power management aspect of the project.

Mechanical Dimensions: the mechanical dimensions of the telit GL865 can be read from the

hardware specs of the user guide. Since the in hose fabrication of the interfacing board is not carried

out, the interface board and mechanical dimension regarding to allowable distances between pins

and multi-layered pcbs is given further below in detail with the description of the layout of the

interface board EVK2 along with factory restored dimension settings for the GSM module.

Pin layout

A pin layout design for the telit GL865DUAL is given as under. For further detailed description of the

pin activity and its design features refer to the hardware specification manuals provided by telit.

Schematic for the interface board and details for serial port usage are given as under:

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Operation sequence for turning on GPS modem - Auto-Turning ON the GL865-

DUAL/QUAD V3

To Auto-turn on the GL865-DUAL/QUAD V3, the power supply must be applied on the power pins VBATT and VBATT_PA, after 1000 m-seconds, the V_AUX / PWRMON pin will be at the high logic level and the module can be considered fully operating. When the power supply voltage is between 3.22V and 3.4V, after 5000 m-seconds, the V_AUX /

PWRMON pin will be at the high logic level and the module can be considered fully operating.

A flow chart showing the AT commands managing procedure is displayed below

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The power off sequences are further provided in the hardware description however, bypassing the

protocol will knit result in any kind of significant problems to the module. Plus in addition to this, the

overall time lapse of sending and receiving time #AT commands and responding with appropriate

designated resulting procedure will also result in saving a substantial amount of time which will be

made up for in cold booting.

Power supply requirements

The power supply circuitry and board layout are a very important part in the full product design and

they strongly reflect on the product overall performances, hence read carefully the requirements and

the guidelines that will follow for a proper design.

The GSM system is made in a way that the RF transmission is not continuous, else it is packed into bursts at a base frequency of about 216 Hz, and the relative current peaks can be as high as about 2A. Therefore the power supply has to be designed in order to withstand with these current peaks without big voltage drops; this means that both the electrical design and the board layout must be designed for this current flow. If the layout of the PCB is not well designed a strong noise floor is generated on the ground and the

supply; this will reflect on all the audio paths producing an audible annoying noise at 216 Hz; if the

voltage drop during the peak current absorption is too much, then the device may even shutdown as

a consequence of the supply voltage drop.

General Design Rules The principal guidelines for the Power Supply Design embrace three different design steps:

The electrical design

The thermal design

The PCB layout.

Electrical Design Guidelines The electrical design of the power supply depends strongly from the power source where this power is drained. We will distinguish them into three categories:

+5V input (typically PC internal regulator output)

+12V input (typically automotive)

Battery

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+ 5V input Source Power Supply Design Guidelines The desired output for the power supply is 3.8V, hence there's not a big difference between the input source and the desired output and a linear regulator can be used. A switching power supply will not be suited because of the low drop out requirements. When using a linear regulator, a proper heat sink shall be provided in order to dissipate the power generated. A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks close to the GL865, a 100F tantalum capacitor is usually suited. Make sure the low ESR capacitor on the power supply output (usually a tantalum one) is rated at least 10V. A protection diode should be inserted close to the power input, in order to save the GL865 from power polarity inversion. An example of linear regulator with 5V input is:

+ 12V input Source Power Supply Design Guidelines The desired output for the power supply is 3.8V, hence due to the big difference between the input source and the desired output, a linear regulator is not suited and shall not be used. A switching power supply will be preferable because of its better efficiency especially with the 2A peak current load represented by the GL865. When using a switching regulator, a 500 kHz or more switching frequency regulator is preferable because of its smaller inductor size and its faster transient response. This allows the regulator to respond quickly to the current peaks absorption. In any case the frequency and Switching design selection is related to the application to be developed due to the fact the switching frequency could also generate EMC interferences. For car PB battery the input voltage can rise up to 15,8V and this should be kept in mind when choosing components: all components in the power supply must withstand this voltage. A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100F tantalum capacitor is usually suited. Make sure the low ESR capacitor on the power supply output (usually a tantalum one) is rated at least 10V. For Car applications a spike protection diode should be inserted close to the power input, in order to clean the supply from spikes. A protection diode should be inserted close to the power input, in order to save the GL865 from power polarity inversion. This can be the same diode as for spike protection.

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Battery Source Power Supply Design Guidelines The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V,

hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit GL865

module.

A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100F tantalum capacitor is usually suited. Make sure the low ESR capacitor (usually a tantalum one) is rated at least 10V. A protection diode should be inserted close to the power input, in order to save the GL865 from power polarity inversion. Otherwise the battery connector should be done in a way to avoid polarity inversions when connecting the battery. The battery capacity must be at least 500mAh in order to withstand the current peaks of 2A; the suggested capacity is from 500mAh to 1000mAh. For our design specifications, a 9 volt battery will be used which will ultimately result in a combined

middle ground of selecting a switch mode power supply with a non-varying input source as we would

have encountered in case of a car outlet usage. However the main theme of designing such a power

supply is to prevent the direct use of battery to the telit module and hence protecting it from un

conditional damages occurring due to maximum absolute voltage peaks and drops accompanied with

current levels at the output for module sink, which are far greater than the rated or allowed value to

make sure the device operates smoothly and without any problems of electrical damages or heating.

Thermal Design Guidelines

Considering the very low current during idle, especially if Power Saving function is enabled, it is possible to consider from the thermal point of view that the device absorbs current significantly only during calls. For the heat generated by the GL865, you can consider it to be during transmission 1W max during CSD/VOICE calls and 2W max during class10 GPRS upload. This generated heat will be mostly conducted to the ground plane under the GL865; you must ensure that your application can dissipate it.

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Power Supply PCB layout Guidelines

As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks and a protection diode on the input to protect the supply from spikes and polarity inversion. The placement of these components is crucial for the correct working of the circuitry. A misplaced component can be useless or can even decrease the power supply performances. The Bypass low ESR capacitor must be placed close to the Telit GL865 power input pads or in the case the power supply is a switching type it can be placed close to the inductor to cut the ripple provided the PCB trace from the capacitor to the GL865 is wide enough to ensure a drop less connection even during the 2A current peaks.The PCB traces from the input connector to the power regulator IC must be wide enough to ensure no voltage drops occur when the 2A current peaks are absorbed. Note that this is not made in order to save power loss but especially to avoid the voltage drops on the power line.

For this reason while a voltage drop of 300-400 mV may be acceptable from the power loss point of

view, the same voltage drop may not be acceptable from the noise point of view. If your application

doesn't have audio interface but only uses the data feature of the Telit GL865, then this noise is not

so disturbing and power supply layout design can be more forgiving.

The placement of the power supply on the board should be done in such a way to guarantee that the

high current return paths in the ground plane are not overlapped to any noise sensitive circuitry as the

microphone amplifier/buffer or earphone amplifier.

Serial Ports

The serial port on the GL865 is the core of the interface between the module and OEM hardware. 2 serial ports are available on the module

MODEM SERIAL PORT 1 (MAIN) for AT commands and Data

MODEM SERIAL PORT 2 (AUX) for AT commands or Debug

Modem Serial Port Several configurations can be designed for the serial port on the OEM hardware, but the most common are:

RS232 PC com port

microcontroller UART @ 2.8V - 3V (Universal Asynchronous Receive Transmit)

microcontroller UART @ 5V or other voltages different from 2.8V Depending from the type of serial port on the OEM hardware a level translator circuit may be needed to make the system work. The only configuration that doesn't need a level translation is the 2.8V UART.

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The serial port on the GL865 is a +2.8V UART with all the 7 RS232 signals. It differs from the PC-

RS232 in the signal polarity (RS232 is reversed) and levels.

According to V.24, RX/TX signal names are referred to the application side, therefore on the GL865

side these signal are on the opposite direction: TXD on the application side will be connected to the

receive line (here named TXD/ RX_uart) of the GL865 serial port and vice-versa for RX.

General Purpose I/O The general purpose I/O pads can be configured to act in three different ways: Input Output Alternate function (internally controlled) Input pads can be read; they report the digital value (high or low) present on the pad at the read time. Output pads can only be written or queried and set the value of the pad output. An alternate function pad is internally controlled by the GL865-DUAL/QUAD V3 firmware and acts depending on the function implemented.

Also the UARTs control flow pins can be usable as GPI/O.

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RS232 level translation In order to interface the GL865 with a PC com port or a RS232 (EIA/TIA-232) application a level translator is required. This level translator must:

Invert the electrical signal in both directions

Change the level from 0/2.8V to +15/-15V Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with lower levels on the RS232 side (EIA/TIA-562), allowing a lower voltage-multiplying ratio on the level translator. Note that the negative signal voltage must be less than 0V and hence some sort of level translation is always required. The simplest way to translate the levels and invert the signal is by using a single chip level translator. There are a multitude of them, differing in the number of drivers and receivers and in the levels (be sure to get a true RS232 level translator not a RS485 or other standards). By convention the driver is the level translator from the 0-2.8V UART to the RS232 level. The receiver is the translator from the RS232 level to 0-2.8V UART. In order to translate the whole set of control lines of the UART you will need:

5 drivers

3 receivers

3.4- TELIT SOFTWARE USER GUIDE

RTS/CTS handshaking

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After power on, the Telit Module is ready to receive AT commands on its Main Serial Port. In general,

its second serial port, called Auxiliary, is used for factory test. To have more hardware information

refer to [3] in accordance with the module under test. The figures below show the RTS/CTS

handshaking of the Main Serial Port:

RTS control line

The RTS control line indicates permission to the DCE (module) to send data to the DTE (user

equipment). The RTS (output) of DTE is checked by the module every GSM TDMA frame (4.61 ms).

As soon as the RTS of the DTE is detected as not asserted, the module immediately stops the

transmission of the bytes toward the DTE.

The maximum number of characters that Telit Module can send to the DTE after the transition RTS

asserted to RTS NOT asserted depends upon the used serial port speed.

CTS control line The CTS control line indicates permission to the DTE (user equipment) to send data to the DCE

(module). The CTS (output) of the DCE is not asserted when the data in its receiver buffer is grater

than 75% of its capacity, the DTE transmission is stopped. The CTS is asserted when data in the

receiver buffer of the module is lower than 25% of its capacity, the DTE transmission starts again.

Module Identification Use the following AT command (as example) to verify if the DTE/DCE connection is working.

AT OK Use the following AT commands to verify the Software Versions and Telit Module Identification:

AT+CGMR: Returns the Software Versions information

AT+CGMM: Returns the Telit Module identification

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A detailed overview of AT commands is provided as under

AT commands are used to control MODEMs. AT is the abbreviation for Attention. These commands come from Hayes commands that were used by the Hayes smart modems. The Hayes commands started with AT to indicate the attention from the MODEM. The dial up and wireless MODEMs (devices that involve machine to machine communication) need AT commands to interact with a computer. These include the Hayes command set as a subset, along with other extended AT commands. AT commands with a GSM/GPRS MODEM or mobile phone can be used to access following information and services:

Information and configuration pertaining to mobile device or MODEM and SIM card.

SMS services.

MMS services.

Fax services.

Data and Voice link over mobile network. The Hayes subset commands are called the basic commands and the commands specific to a GSM network are called extended AT commands.

The Telit wireless module family can be controlled via the serial interface using the standard AT commands1. The Telit wireless module family is compliant with:

Hayes standard AT command set, in order to maintain the compatibility with existing SW programs.

3GPP TS 27.007 specific AT command and GPRS specific commands.

3GPP TS 27.005 specific AT commands for SMS (Short Message Service) and CBS (Cell Broadcast Service)

FAX Class 1 compatible commands Moreover Telit wireless module family supports also Telit proprietary AT commands for special purposes. The following is a description of how to use the AT commands with the Telit wireless module family.

The following code taken from the LPC EXPRESSO suite describes the AT command initialization for the GSM modem via the LPC810 microcontroller

volatile unsigned char Check_for = 'A'; //this field changes for INVALID or ACTIVE packs volatile my_serial_register myreg; volatile my_flag_register myFlags; volatile my_gps_retvData mygps_retvData; volatile my_device_stat mydevice_stat; volatile unsigned char string1[]="AT\r"; volatile unsigned char string2[]="AT+CMGF=1\r"; //change modem encoding to ASCII chars volatile unsigned char string3[]="AT+CMGS="; volatile unsigned char SimNo[]="015259496296\r"; //should be changed for other receivers volatile unsigned char stringate0[]="ATE0\r";

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3.5- POWER SUPPLY UNITS

Linear regulator LM2937 -3.3 V

The LM2937-2.5 and LM2937-3.3 are positive voltage regulators capable of supplying up to 500 mA of load current.

Both regulators are ideal for converting a common 5V logic supply, or higher input supply voltage, to the lower 2.5V and

3.3V supplies to power VLSI ASICs and microcontrollers.

Special circuitry has been incorporated to minimize the quiescent current to typically only 10 mA with a full 500 mA load current when the input to output voltage differential is greater than 5V.

External Capacitor The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both ESR (Equivalent Series Resistance) and minimum amount of capacitance. Minimum Capacitance The minimum output capacitance required to maintain stability is 10 F (this value may be increased without limit). Larger values of output capacitance will give improved transient response.

Switch mode non-linear buck regulator

The LM2576 series of regulators are monolithic integrated circuits that provide all the active functions

for a step-down (buck) switching regulator, capable of driving 3A load with excellent line and load

regulation. These devices are available in fixed output voltages of 3.3V, 5V, 12V, 15V, and an

adjustable output version.

A block diagram of the IC is given above

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Absolute maximum ratings

As in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance generate voltage transients which can cause problems. For minimal inductance and ground loops, the length of the leads indicated by heavy lines should be kept as short as possible. Single-point grounding (as indicated) or ground plane construction should be used for best results. When using the Adjustable version, physically locate the programming resistors near the regulator, to keep the sensitive feedback wiring short.

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Here the R2 and R1 are calculated to be 4K Ohm and 2.2K Ohm respectively.

To maintain stability, the regulator input pin must be bypassed with at least a 100 F electrolytic capacitor. The capacitor's leads must be kept short, and located near the regulator. If the operating temperature range includes temperatures below 25C, the input capacitor value may need to be larger. With most electrolytic capacitors, the capacitance value decreases and the ESR increases with lower temperatures and age. Paralleling a ceramic or solid tantalum capacitor will increase the regulator stability at cold temperatures. All switching regulators have two basic modes of operation: continuous and discontinuous. The difference between the two types relates to the inductor current, whether it is flowing continuously, or if it drops to zero for a period of time in the normal switching cycle. The inductor value selection guides in figure above were designed for buck regulator designs of the continuous inductor current type. When using inductor values shown in the inductor selection guide, the peak-to-peak inductor ripple current will be approximately 20% to 30% of the maximum DC current. With relatively heavy load currents, the circuit operates in the continuous mode (inductor current always flowing), but under light load conditions, the circuit will be forced to the discontinuous mode (inductor current falls to zero for a period of time). This discontinuous mode of operation is perfectly acceptable. For light loads (less than approximately 300 mA) it may be desirable to operate the regulator in the discontinuous mode, primarily because of the lower inductor values required for the discontinuous mode. An output capacitor is required to filter the output voltage and is needed for loop stability. The capacitor should be located near the LM2576 using short pc board traces. Standard aluminum electrolytic are usually adequate, but low ESR types are recommended for low output ripple voltage and good stability. The ESR of a capacitor depends on many factors, some which are: the value, the voltage rating, physical size and the type of construction. In general, low value or low voltage (less than 12V) electrolytic capacitors usually have higher ESR numbers. To further reduce the output ripple voltage, several standard electrolytic capacitors may be paralleled, or a higher-grade capacitor may be used. Such capacitors are often called high-frequency, low-inductance, or low-ESR. These will reduce the output ripple to 10 mV or 20 mV. However, when operating in the continuous mode, reducing the ESR below 0.03 can cause instability in the regulator.

Feedback connection

The LM2576 (fixed voltage versions) feedback pin must be wired to the output voltage point of the switching power supply. When using the adjustable version, physically locate both output voltage programming resistors near the LM2576 to avoid picking up unwanted noise. Avoid using resistors greater than 100 k because of the increased chance of noise pickup.

ON /OFF Input

For normal operation, the ON /OFF pin should be grounded or driven with a low-level TTL voltage (typically below 1.6V). To put the regulator into standby mode, drive this pin with a high-level TTL or

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CMOS signal. The ON /OFF pin can be safely pulled up to +VIN without a resistor in series with it. The ON /OFF pin should not be left open.

The power control of the board PCB design is under the control of the switch mode power supply IC. The PIN number 4 (GPIO0) of the LPC is responsible for controlling the ON/OFF switching of the board. This, itself is directly responsible for power management rather then re-writing the python on-board kernel of the GL865 modem. At time 0sec, the board power is OFF, at after suitable and adjustable (through coding) delays, the suitable voltage is provided to the GSM modem, Quad state buffer and the GPS satellite receiver. At time t sec, the board switches ON and checks for available carrier signals via the SIM card, on the other hand the GPS receiver starts its signal reception for a valid packet entry into the UART. As soon as the data packet received is ACTIVE (A), initiates the AT command routine for carrier authentication and after a while sends a TEXT message body containing the desired coordinate information to the smart phone. The code for ON/OFF via pin 4 is given below:

3.6- QUAD TRI-STATE BUFFER

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Switch positions symbol sw1 sw2

tPZH Open Closed

tPZL Closed Open

tPLZ Closed Closed

tPHZ Closed Closed

The buffer is utilized here for the fact that we dont use the python kernel for power management and

standby mode for the GSM modem. The buffer is connected to GSM TX and GPS TX. On the side for

controlling the data flow from the two attached modules from the project, namely the MT3329 GPS

antenna and the telit GL865 DUAL modem interface, an inverter circuitry is designed to operate as a

switch with a always ON and always OFF logic. During the implementation of this logic. The GPS

antenna will remain active throughout the working plan of the apparatus, on the other hand, the GSM

only toggles ON and gets a network authentication when it is needed to send the desired data GPS

coordinates over to the mobile handy. The logic state of the tri buffer provides this functionality.

The output of the buffer states is connected to the LPC ARM cortexs RX. The function is of the

designed logic transmits the data over to LPC for intermediate storing and then serial transmission

over to the GSM modem and onto mobile phone.

The tristate quad buffer is used to queue the data coming in from the GPS module at pin number 2

which is treated with an inverted configuration from a transistor assembly which provides the usage of

the inverted state gates for data buffering. The schematic shows the design of wiring for the circuit

board. the pin 6 is utilized for GSM modem for relaying data as well as queuing data from LPC

microcontroller.

///com control setup #define gsm 0 #define gps 1 #define com_control_pin 2 //(port0 bit 2) #define com_to_(x) gpioSet_intihai_portVal(com_control_pin,x)

void select_device(unsigned char d) { if(d==gps) { myFlags.serial_data_recvd=0; myFlags.start_filling=0; myFlags.valid_packet=0; myreg.counter=0; mydevice_stat.GSM=0; mydevice_stat.GPS=1; com_to_(d); } else { myreg.counter=0; myFlags.serial_data_recvd=0;

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myFlags.start_filling=0; myFlags.valid_packet=0; mydevice_stat.GSM=1; mydevice_stat.GPS=0; com_to_(d); } }

// checking for data and relaying it :: unsigned char check_at_reply() { unsigned char valid_result=0; unsigned char stringat[]={'O','K'}; //have to confirm this unsigned char a=0,b=0; unsigned char noOfattempts=20; while(noOfattempts!=0 && b!=2) { if(myreg.buffer[a]==stringat[b]) { b++; } else b=0; a++; noOfattempts--; } if(b!=0) valid_result=1; else valid_result=0; return valid_result;}

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4- SCHEMATIC DIAGRAM OF THE SYSTEM

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The above mentioned diagrams for the schematic and PCB fabrication were implemented with the

help of Mr. Weber with the in house milling machine as it was only required as a single sided PCB.

5- HARDWARE OF THE SYSTEM

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6- FURTHER IMPROVEMENTS

Although the system designed is complete and comprehensive in its own virtue in terms of regarding

the system as a complete solution which was required in the first place. However, the area that can

be improved further on is the power management. The steps taken to minimize the power

consumption was based on the idea that instead of re-writing the kernel inside the modem, the switch

mode power supply was configured in a way that utilizes timely activation and delay based on valid

data to account for the idea for standby versus the cold start every time. This technique comes in

handy while rooting for saving power of the battery for a complete standalone and surveillance kit

solution of the system.

7- BIBLIOGRAPHY

1. All designs were made from scratch

2. Any generic idea for system configuration is taken from the datasheet of the respective

components

3. All datasheet and instruction manuals of respective components were utilized, quoted and

cited for technical data and system design utilization for the project presented here.