J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1

GRID.pdf

Vis i t us at e-GRID.net

Upcoming Conferences

Jan. 6 & 7: The 2006 Storage Visions Conference- Las Vegas Convention Center - Concurrent with the Consumer Electronics Show [more]

Jan. 23-26: Wireless Mobile Broadband Markets & Wireless GigaBit Transport for Distributed Antenna Systems Workshops - Westin Hotel, SF Airport (Millbrae) [more]

Feb. 6-9: DesignCon 2006 Santa Clara Convention Center [more]

Mar. 6-8: Internationalization and Unicode Conference Hyatt Regency Hotel, Burlingame [more]

Mar. 20-24: The Game Developers Conference - San Jose Convention Center - With GDC Mobile and Serious Games Summit [more]

Mar. 27-29: Int’l Symposium on Quality Electronic Design DoubleTree Hotel, S.J. [more]

January 2006

Support our advertisers MARKETPLACE – Services page 3 Faculty Positions at S.F. State Univ. page 6 Conference Calendar page 35

SCV-EMC - 1/10 | Stackup Analysis Using Simulation Tools (HyperLynx) - the arrangement of PCB layers and their effects .[more]

SCV-CPMT&LEOS - 1/11 | Enabling Technologies for Board-Level Optical Interconnects - integrated polymer waveguides, waveguiding elements, 3D optical wiring schemes ... [more]

SCV-MTT - 1/12 | Global Modeling and Design of Micro/nano Devices and Circuits - integration of circuit, electromagnetics, device transport physics, thermal, and mechanical simulators ... [more]

SCV-CPMT - 1/17 | Semiconductor Equipment and Materials Outlook - market forces affecting packaging, assembly, shipments, with predictions ... [more]

SCV-Mag - 1/17 | Beyond the Limits of Magnetic Recording: an Itinerant Magnetician Looks at Hysterical Loops - will we reach the ultimate limit of areal density? ... [more]

SF-Comm - 1/17 | High Speed Networking in Calif. Education - high speed networking to all of California’s public educational institutions (CalREN, CalREN-2) ... [more]

SCV-CNSV - 1/17 | Marketing Your Consulting Practice on the Web - don't miss your best opportunity to convince companies to engage you as a consultant ... [more]

SF-PES - 1/18 | Broadband over Power Lines - FCC Emissions Compliance Guidelines - high-speed internet access with fixes for interference problems ... [more]

SCV-PES/IAS - 1/18 | Short Circuit and Coordination Analysis - programs now available produce technically accurate studies ... [more]

SCV-GOLD - 1/18 | Digital Storage for the Studio and the Home - distribution of content: the entertainment value chain ... [more]

SCV-EMB - 1/18 | Stem Cell Applications in Biomedicine, Tissue Engineering, and Regenerative Medicine - an overview of stem cell biology and ongoing developments ... [more]

SCV-Rel - 1/18 | Best of ISTFA - from the Int'l Symposium for Testing and Failure Analysis in San Jose in November ... [more]

SCV-SSC - 1/19 | Introduction to the Stanford Nanofabrication Facility and Research Examples - an overview... [more]

OEB-IAS - 1/19 | Overview of the Stationary Fuel Cell Market - the market drivers and overview of the world's leading supplier ... [more]

SCV-CAS - 1/23 | EDA Challenges for Low-Power Design - power gating, dynamic voltage frequency scaling ... [more]

SCV-CE - 1/24 | CES Debrief - notable new products and technology from the 2006 Consumer Electronics Show ... [more]

SF-IAS - 1/24 | Medium Voltage Distribution Equipment - utility service requirements, types of equipment, circuit breakers, fuses [more]

SCV-CPMT- 2/8 | MultiLayer Ceramic Capacitor (MLCC) Value Drift (and) Embedded Passives - base-metal-electrode capacitors degrade at 500 hours; embedding capacitors... [more]

SCV-EMB - 2/15 | Biometrics: A Brief History and Review of Current Programs - face and iris recognition ... [more]

4-day theory+lab classes held March 29 – April 1 San Jose State Electrical Engineering Dept - DSP System Design and Implementations - FPGA DSP System Design - Wireless Transmitters - Embedded Systems and Embedded FPGAs - High-Speed Data Networks [more] Professional Skills Courses from EMS, CPMT, ETA:

Leadership Skills for Engineers Jan 24 at LSI Logic, Milpitas [more]

Clear Business, Technical, and E-mail Writing Feb 7 at National Semiconductor, Santa Clara [more]

High-Impact Communication Feb 9 at LSI Logic, Milpitas [more]

Memory Power (half-day) Feb 15 at Exar Corporation, Fremont [more]

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Your Networking Partner ®

January 2006 • Volume 53 • Number 1

IEEE-SFBAC ©2006

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for both news and opinion, the editorial objectives of IEEE GRID are to inform readers in a timely and objective manner of newsworthy IEEE activities taking place in and around the Bay Area; to publish the official calendar of events; to report on IEEE activities of a national and international scope; and to serve as a forum for comment on areas of concern to the engineering community by publishing contributed articles, invited editorials and letters to the editor. IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, and in a handly printable GRID.pdf edition, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID 12250 Saraglen Dr. Saratoga CA 95070 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

From the editor . . .

January marks a “new beginning” for many parts of IEEE. The SF Bay Area Council gets new leadership from the three Sections that govern it. Each Section (one for San Francisco, one for Oakland and the East Bay, and one for the Santa Clara Valley) have balloted their members and determined a new slate of officers for 2006. And finally, each and every local Chapter conducted voting (either at a regular meeting or by mail/email ballot) to determine which candidates you would like implementing the program for the next calendar year.

For most IEEE members, it is the local Chapters that provide much of your “contact” with the organization. Yes, you understand the world-wide reach of the IEEE, and it’s global Societies addressing various parts of the technology. Sometimes these Societies bring one or more of their major conferences to our locale, and in that way we see – if we find the time to attend – their strength and breadth of representation. But it is the one or two local Chapters of that Society that invigorate the debate about new technologies, the discussions about approaches to design, and the networking with our co-workers here in the S.F. Bay Area. That’s why the Chapter elections tend to be the most important and relevant to you, as a member of IEEE.

Many IEEE members belong to only one Society, and thus tend to associate themselves only with that local Chapter. Some members belong to NO Societies – perhaps their technical specialty doesn’t match a Society very well, or maybe they are generalists and “sample” from many Societies. In any case, just because you belong to, say, the Electromagnetic Compatibility Society doesn’t mean you shouldn’t see what meetings and seminars the Circuits and Systems Chaper is conducting. Today’s engineer or manager needs to be multidisciplinary while still maintaining strong depth in a specific area.

So, scan the e-GRID, and look down the first column on page 1 of this GRID.pdf, to find topics across all of our local offerings – you’ll broaden your capabilities!

Paul Wesl ing ed i to r@e-gr id .ne t

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net

Chairman Julian Ajello

Finance Chair Ron Kane

Editorial Board Chair Annie Kong

OEB Director Bill DeHope

SF Director James Lekas

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRID

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Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

info@file-ee-patents.com

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835

Bernie Siegal

650-961-5900

info@thermengr.com www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

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• From Inception to Production Transfer • Turnkey, Design Services & Consulting • Design Reviews & TroubleShooting

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Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)

m.siddappa@ieee.org 408-981-6612

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

Visit our Marketplace (page 3)

Download Rates and Services information: www.e-grid.net/docs/marketplace-f lyer.pdf

GRID.pdf

e-GRID

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

info@ozeninc.com www.ozeninc.com

Board Logic Systems

Complete Product Solutions Provider TM

Experienced consultants in the fields of: • Board & Verilog Design • Debug and Test • Signal Integrity • EMI • Power Electronics • Layout • Software Development • Documentation

www.boardlogics.com

info@boardlogics.com (650) 867-0869

Professional Services Marketplace – editor@e-GRID.net for information

Say you found them in our GRID MARKETPLACE

Professional Consulting Services to assist clients in developing & executing any and all elements of Reliability throughout an Organization & Product Life Cycle.

• Assessments • Goals • Benchmarking • Reliability Prog. Plans • MTBF Pred • FMECA • EOL Assessment • Warranty Analysis • HALT/HASS • DVT/V&V • Rel. Demo. Tests • Software Reliability • CAPA/CLCA • DoE • Training/teaching • RoHS/WEEE Transition

pioneered Reliability IntegrationSM - using multiple tools in conjunction to increase the power and value of any Reliability Program.

(408) 472-3889 info@opsalacarte.com www.opsalacarte.com

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Hear the latest on digital content technology from industry leaders – those who matter in the entertainment value chain – and find out how current and coming trends can benefit your company, from the experts at Turner Broadcast, Seachange, Microsoft, Scientific Atlanta, Seagate, Maxtor, Samsung Semiconductor, M-Systems, Agere Systems, Marvell, ST Microelectronics, HP, Atmel, Sonic Solutions, Silicon Image, Toshiba, and many others.

The Storage Visions™ 2006 Conference and the Consumer Electronics Association (CEA) are partnering to promote digital storage and the entertainment content value chain. Find out how digital content will be created, protected, and stored, from the executives, analysts, and professionals at the forefront of digital technology.

Sessions: – Storage and Content Creation, Editing and Distribution – Home Network Storage – Integration of Storage in CE Devices – Mobile CE Storage Products – Optical Storage – Storage and CE Analyst Session – Financial Analyst and VC Session Also at the International Consumer Electronics Show:

• Free One-Day Program • Thursday, January 5, 2006 • Sands Hotel, Las Vegas

9:00 AM: Disruptive Innovation Woodward Yang, Professor of Engineering, Harvard University

10:30 AM: Game Theory – critique of next-generation videogame consoles (Microsoft, Nintendo and Sony); ideas for ideal games machines

1:00 PM: New Frontiers - visions of the future of wireless technology & next big opportunities

2:30 PM: Innovation Generation - the future of innovation in America and suggestions for how companies can do a better job fostering it

4:00 PM: Digital Media - ubiquitous digital media in the future: connectivity, plug and play, long battery life, DRM

Keynote Speakers: Clyde Smith, Sr. VP, Turner Broadcasting Brodie Keast, Seagate Technology Mike Alexenko, Maxtor For complete information on Storage Visions 2006, please see the website:

www.storagevisions.com Or call Kathleen locally at Storage Visions, 408-871-8808, to register orally for the Conference and CES Show Exhibits.

This one day program, hosted by the editors of EE Times, begins with a one hour lecture delivered by Harvard Engineering Professor Woodward Yang describing how companies can use frameworks of disruptive innovation to build better businesses. A series of panel discussions will tackle issues in digital media, wireless and other technology areas related to consumer electronics. Plan to attend!

Review the “Great Minds” Program

Review and register for all CES events:

www.cesweb.org

January 6-7, 2006 Las Vegas Convention Center

Includes Exhibits pass to the Consumer Electronics Show

Concurrent with the Consumer Electronics Show

Great Minds, Great Ideas: the People, the Products, and the Technologies That Will Change Our World

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The Game Developers Conference 2006

March 20-24, 2006 @ the San Jose Convention Center

Next-gen game development will revolutionize every aspect of the gaming industry, and in turn influence other technology sectors that use advanced display, simulation, and interactive technologies. From increased production complexity, team sizes, and budgets to new ways to reach the mass market, GDC:06 will answer the questions critical to the industry's success. Industry luminaries will lead more than 300 lectures, tutorials, panels, roundtables and poster sessions covering all aspects of the industry for all platforms and all genres. Learn lessons from next-gen, handheld, and current game development, explore collaborations with the film industry and gain access to the people, technologies, and tools that define what's next for our industry.

25 Tutorials from which to choose. Exposition open Wed, March 22 - Friday, March 24

This year's GDC Tracks include the following: • Vision Track • Audio Track • Production Track • Programming Track • Business & Management Track • Game Design Track • Visual Arts Track

See the website for full details and a printable program. IEEE Professional Skills Courses Leadership Skills for Engineers

– Date/Time: Tuesday, January 24, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $375 for IEEE Members; $425 non-members

The challenges of leadership in high-tech companies have never been greater. Today's manager must be fully aware of his/her style and be able to adjust to fit the needs of others and the demands of the situation. In addition, obtaining relevant information and sharing it appropriately requires skills in phrasing questions, listening and speaking for results. This high-impact, one-day workshop provides technical managers with analytical tools and cultivates "street smarts".

Clear Business, Technical, and E-mail Writing

– Date/Time: Tuesday, February 7, 8:30AM-4:30PM – Location: National Semiconductor, Santa Clara – Fee: $400 for IEEE Members; $450 non-members

This workshop provides a step-by-step process for designing and writing a clear engineering document, e-mail message, or report. You will learn by doing, the only legitimate way to improve writing skills! The training involves writing, revising, and editing exercises; critiquing documents; games; and lecture. You will walk away with confidence in writing and editing skills and with a consciousness about international writing.

GDC Mobile 2006 March 20-21, Fairmont Hotel, San Jose

GDC Mobile is the definitive mobile gaming event for leading industry professionals looking to expand their knowledge of, and contacts within this exploding mobile entertainment sector. It provides mobile game developers from around the globe the opportunity to debate the future of their medium with executives from the leading mobile network operators, MVNOs, advanced technology providers and major console game publishers.

Serious Games Summit GDC March 20-21, Fairmont Hotel, San Jose

Serious Games are applications of interactive technology that extend far beyond the traditional videogame market, including: training, policy exploration, analytics, visualization, simulation, education and health and therapy. This forum allows game developers and industry professionals to examine the future course of serious games development in areas such as education, government, health, military, science, and corporate training.

Register by February 15th to save up to 35%! IEEE members - Use priority code IEMAPX to activate your registration. Academic, Student and Group rates are available. Visit:

www.gdconf.com SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies

High-Impact Communication – Date/Time: Thursday, February 9, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $350 for IEEE Members; $425 non-members

Memory Power – Date/Time: Wed, February 15, 8:30AM-Noon – Location: Exar Corporation, Fremont – Fee: $300 for IEEE Members; $325 non-members

Speed Reading – Date/Time: Wed, February 15, 8:30AM-4:30PM – Location: Carl Zeiss Meditec, Dublin – Fee: $375 for IEEE Members; $425 non-members

Improve your skills – register for one of these classes, or for others coming up this spring. Bring a team!

For complete course information, schedule, and registration form, see our website:

www.effectivetraining.com

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If you are involved in implementing the Unicode Standard or working on internationalization, this is a must-attend conference – the only industry event focused on the Unicode™ Standard. The conference features a variety of tutorials and conference sessions that cover current topics related to Unicode, the web, software and internationalization. Unicode experts, imple-menters, clients and vendors are invited to attend this unique conference. Exchange ideas with leading experts, find out about the needs of potential clients, or get information about new and existing Unicode-enabled products. Visit the website to sign up for email updates about Unicode’06 and its tutorials and sessions. Organized by the Object Management Group, a not-for-profit consortium that produces and maintains computer industry specifications for interoperable enterprise applications, including MDA®, UML®, CORBA®, MOF™, XMI® and CWM™.

March 6-8, 2006 Hyatt Regency Hotel

Burlingame (S.F. Airport)

Tutorials 3/6; Sessions 3/7-8 Conference topics: • Web internationalization • Text and data mining • Security and phishing • New and upcoming technologies • Enterprise software in a global environment • Web services, SOA and Internationalization • Language tags and locales: implications for developers • Making scripts and languages accessible • Global development best practices • What’s new with Unicode 4.0; Successful Implementations • Internationalized Domain Names/Resource Identifiers • Tips, tricks and traps in developing international software • Globalizing your product: business cases and technical issues Early-bird registration rates through January 23 – multi-attendee discounts. For more information and to register:

www.unicodeconference.org/ieee For information on exhibiting or other questions, visit the website or contact Kevin Loughry at loughry@omg.org, +1-781-444 0404 The Unicode Consortium is a non-profit organization founded to develop, extend and promote use of the Unicode Standard and related globalization standards.

San Francisco State University Assistant Professor Positions

The Engineering Department invites applications for two faculty positions: We offer a competitive salary, excellent benefits and an exceptional startup package. To apply, please send a detailed resume, statements of teaching and research interests, and a minimum of three recommendation letters to Chair, Hiring Committee, School of Engineering, San Francisco State University, 1600 Holloway Avenue, San Francisco, CA 94132. The review process will continue until the position is filled. SFSU is an equal opportunity/ affirmative action employer; applications are actively encouraged from underrepresented minorities and women.

For information about the SFSU School of Engineering, see engineering.sfsu.edu

Assistant Professor in Electrical Engineering

We invite applications for a tenure track Assistant Professor in Electrical and Computer Engineering, starting Fall 2006. Specific technical areas of interest include RF circuit design and analog electronics. We seek applicants who excel in both teaching and research. The successful candidate must be capable of pursuing externally supported research and possess a strong interest in teaching/developing new and existing courses and labs. A Ph.D. in EE or related field and an excellent record of publications in scholarly journals and conferences are required; industry experience is highly desirable.

Assistant Professor in Mechanical Engineering

We invite applications for a tenure track Assistant Professor in Mechanical Engineering, starting Fall 2006. The specific technical area of interest is materials engineering, including but not limited to the following: mechanical behavior of materials, bio-mechanical materials, electronic materials, nano materials,and composites or intelligent materials. We seek applicants who will excel in both teaching and research. The successful candidate must have the ability to pursue externally supported research, and have a strong interest in teaching/developing new and existing courses and labs in materials engineering and design. A Ph.D. or equivalent in Mechanical Engineering or a closely related field is required. Strong analytical skills with practical, hands-on design experience are highly desirable. Industry experience is a plus.

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Conference: February 6–9 Exhibition: February 7–8

Santa Clara Convention Center Developed specifically for

semiconductor and electronic design engineers, DesignCon is the essential design engineering event addressing the challenges facing these communities and providing the solutions attendees can implement immediately in their designs.

Exhibits feature leading organizations presenting EDA tools, test and measurement equipment, PCBs and related technologies, semiconductor components and IP, interconnect technologies, and more. Papers discuss leading-edge case studies, technology innovations, practical techniques, design tips and application overviews.

Technical tracks: • Chip-Level Functional Design • Chip-Level Physical Design and Verification • Power and Package Co-Design • PCB, Package, and Passive Technologies • Chip and Board Interconnect Design • High-Performance Backplane Interconnect Design • High-Speed Timing, Jitter and Noise • Power Integrity • Functional Verification • Business Issues

Technical Panels: Jitter and Its Challenges when Testing Serial Data Designs How to Choose Bypass Capacitors Strategies for Device Differentiation The Growing Impact of Power on SoC Design Ethernet Ecosystem Impact on Backplane & System Design OpenAccess Adoption and Proliferation Why So Many Chips Fail? Design Verification … and more

International Engineering Consortium www.iec.org

Keynote Speakers: Justin Rattner, Intel Sr Fellow, Corp Technology Group, Intel Brian Halla, Chmn. of the Board/CEO, National Semiconductor T.J. Rogers, Founder, President, CEO, Cypress Semiconductors Management Forum Panels: Engineering Education in the United States Today's DFM: the Supply Chain and its Effect on Designers Managing Verification ROI: Business Impact of Bug Escapes Make Technical On-Line Marketing Truly "Technical" The Growing Cost of EDA Tools: When to Build versus Buy The Business of DFM: Critical Issues and Implications … and more

Discover the latest tools and methods to overcome your design challenges and drive tomorrow’s innovations at DesignCon 2006. Semiconductor and electronic design engineers will find the right mix of technical education and networking opportunities, with access to cutting-edge design products.

Official Sponsor Diamond Sponsor

Arrive at the future of Design!

Visit: www.designcon.com

Early Bird registration through January 13th!

DESIGN CHALLENGES SLOWING YOU DOWN? FIND YOUR SOLUTION AT DESIGNCON 2006

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7th International Symposium on

QUALITY ELECTRONIC DESIGN March 27-29, 2006 DoubleTree Hotel, San Jose

The International Symposium on Quality Electronic Design (ISQED) is a premier Manufacturing, Design & Design Automation conference, aimed at bridging the gap among electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues front-to-back. The conference attendees are primarily designers of the VLSI circuits & systems (IP & SoC), process/device technologists, semiconductor manufacturing specialists including equipment vendors, and those involved in the R&D and application of EDA Tools & design flows. ISQED emphasizes a holistic approach toward design quality and intends to highlight and accelerate cooperation among the IC Design, EDA, Semiconductor Process Technology and Manufacturing communities. The conference spans three days, Monday through Wednesday, in three parallel tracks, hosting over 100 technical papers, six keynote speakers, two panel discussions, workshops /tutorials and other informal meetings. ISQED proceedings are published by IEEE Computer Society and hosted in the digital library. Proceedings CD ROMs are published by ACM.

CONFERENCE HIGHLIGHTS TUTORIALS/WORKSHOPS ISQED 2006 is pleased to offer a single full-day tutorial track, presented by six experts in their respective fields. This tutorial track consists of two (2) major topics shown below. The first topic examines the critical and timely issues of "variability" and its impact in design with 65nm and finer CMOS technologies. The second topic explores the exciting field of emerging Nanoelectronic technologies and their application toward future ULSI designs. Variability and its Impact on Design Dr. Keith Bowman, Intel Corporation Dr. Michael Orshansky, University of Texas-Austin Dr. Sachin S. Sapatnekar, University of Minnesota

Emerging Technologies for VLSI Design Dr. Rajiv Joshi, IBM T J Watson Research Center, NY Dr. Kaustav Banerjee, University of California, Santa Barbara, CA Dr. Andre DeHon, California Institute of Technology, Pasadena, CA

PLENARY SESSIONS Two plenary sessions will be held on Tuesday and Wednesday mornings. Six industry & academia leaders will discuss the issues surrounding electronic design, design for yield and manufacturability and other critical topics from various points of view. Plenary keynote speakers are:

PANEL DISCUSSIONS ISQED is pleased to offer two high-power evening panel discussion sessions, where many leading experts, address the important issue of quality design. These panels would focus on the following topics:

Dr. Risto Suoranta, Principal scientist & Research Fellow, Nokia Dr. Tohru Furuyama, GM, Toshiba SoC Research and Development Center Dr. Di Ma, Vice President of Field Technical Support, TSMC Dr. Raul Camposano, Sr. Vice President, CTO, and GM, Synopsys Dr. Changhyun Kim, Vice President and Fellow, Samsung Electronics Dr. Philip Wong , Professor, Stanford University

1 Power management and optimization challenges for sub 90nm CMOS designs - What is the real cost of long battery life? 2 Soft IP Quality: Who is responsible to ensure quality throughout the design process?

LUNCHEON SPEECH Simplicity and Executability: Cornerstones of Quality Michael Keating, Synopsys

VENDOR EXHIBITION The exhibition is being held for the 1st time in conjunction with ISQED, features vendors offering design tools and methodologies in the area of design for manufacturing and quality. Exhibit floor will be open on Tuesday March 28, in parallel with technical sessions.

TECHNICAL SESSIONS ISQED Technical sessions start on Tuesday March 27, and continue until the afternoon of Wednesday, March 29. Beside the above plenary sessions, panel discussions, and workshops, the program consists of nineteen technical sessions featuring over 100 papers on various challenging topics related to design for manufacturability and quality. Detail program would be available on the web at www.isqed.org. • EDA Tools, Flows & IP Blocks; Interoperability (EDA) • Design for Manufacturability & Quality (DFMQ) • Design Verification and Design for Testability (DVFT) • Package - IC Design Interactions & Co-Design (PDI)

• Robust Device, Interconnect, and Circuits (RDIC) • Physical Design, Methodologies & Tools (PDM) • Effects of Technology on IC Design, Performance,

Reliability, and Yield (TRD) • System Level Design, Methodologies and Tools (SDM)

Please refer to ISQED web site at www.isqed.org for information regarding the tutorials, conference, and hotel registration. Direct all conference inquiries to isqed@isqed.org. Early registration is recommended to take advantage of the discounted registration fee.

www.isqed.org

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SPRING SEMESTER CLASSES OF INTEREST

INTRO TO MICROELECTRONIC PACKAGING (ENGR 240) Meets weekly: Sat 9:00 AM – Noon Starts: January 28 Instructor: Mulugeta Abtew, Manager,

Sanmina/SCI This graduate-level course provides engineers the

fundamental understanding of microelectronics packaging and its critical role in the functioning of electronic products. It covers the functions and principal parameters that need to be considered in packaging and interconnect design, including Thermal, Electrical and Mechanical functions of packaging, Device and Board-level packaging including QFP, Plastic and Ceramic BGAs, CCGA, Micro BGA, 3-D CSP, COB, FCOB, interconnect methodologies, Wirebonding, TAB, Flip Chip, Wave and Reflow Soldering, interconnect failure modes and Reliability, including review of statistical modeling for reliability prediction. The physics and chemistry behind processes such as molding, sintering and soldering are covered. Aspects of optoelectronic and MEMS packaging will also be covered.

This course may be taken through SJSU’s Open University. The cost is approximately $630 + cost of textbook and instructional materials. Enrollment during the first class period will be allowed.

Contact Dr. Guna Selvaduray at SJSU for full course information. Tel: (408) 924-3874,

Email: gunas@email.sjsu.edu. Wireless Mobile Broadband Markets – Hype or Reality?

-- January 23-24, 2006 -- Westin Hotel, SF Airport (Millbrae)

Which wireless systems and technologies will have a financial impact on wireless industry markets in 2006 and beyond? The investor community has its view; industry leaders have their views. This Workshop brings together the financial market analysts with wireless industry and supply chain leaders to share real data and points of view to help you reach an understanding of current and future markets and deployments of various segments and technologies of the wireless industry.

Organized by the International Wireless Industry Consortium, and specially tailored for our 125 corporate members, their officers and employees.

For more information and full program for each Workshop, please visit

www.iwpc.org

or email/call Don Brown at +1-215-293-9000.

Spring Classes at San Francisco State Univ, ECE Department

ADVANCED VLSI DESIGN (ENGR 856) Meets weekly: Mondays 6:10 – 8:55 PM Instructor: Prof. Hamid Mahmoodi Starts: January 30

This course introduces advanced topics in VLSI device, circuit, and system design. High-performance and low-power design issues in modern and future process technologies are discussed in detail. The challenges of technology scaling are covered and state of the art technologies and solutions at different levels of abstraction are discussed. A class project is an integral part of this course.

DIGITAL IC DESIGN (ENGR 453) Lectures Mon & Wed 2:10 - 3:25 PM; Lab Mon 6:35 - 9:20 PM Instructor: Prof. Hamid Mahmoodi Starts: January 30

This course is designed to teach students the basics of analysis and design of digital integrated circuits, particularly in CMOS technology. The skills learned in this course will prepare students to do real-world design tasks in the field of digital IC design.

For further information and web description of courses, visit:

online.sfsu.edu/~mahmoodi/

or call Dr. Hamid Mahmoodi, 415-338-6579. These courses may be taken through SFSU’s Open University. For more information on Open University, visit:

www.cel.sfsu.edu/openuniversity

Two IWPC Interactive Technical Workshops in the Bay Area

Wireless GigaBit Transport for Distributed Antenna Systems – Is it a Viable Option?

-- January 24-26, 2006 -- Westin Hotel, SF Airport (Millbrae)

The worldwide demand for cost-effective mobile wireless voice and data infrastructure continues to grow – the challenge is to achieve more uniform coverage with increased datarates. Solutions such as WCDMA, HSDPA, etc. are emerging. Another may be distributed radio head-ends mounted on remote towers or sites for more uniform overall coverage. A key is cost-effective options for transporting the high data rates between the hub and the many remote sites -- dark fiber, broadband free space optic (FSO) or millimeter-wave links. This Workshop brings together senior leaders from THE ENTIRE SUPPLY CHAIN to facilitate and stimulate breakthrough thinking on emerging technologies for gigabit transport.

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 10

Career-Advancement Short Courses with Labs March Technology Series

• Theoretical Aspects • Hands-on Experience • For working professionals • Preparation for Tomorrow • Excellent value; practical; timely topics • 5 Choices, all in the week of March 29, 2006

Digital Signal Processing -- 4-day class with labs: DSP System Design and Implementations

Overview: Today’s technology provides DSP processors that can be easily used to design very sophisticated products for instrumentation, control systems, communications, and wireless systems. This course presents DSP system design and implementation using programmable signal processors. Hands-on laboratory exercises are used to present the design and implementation aspects, using hardware and software tools for system implementation. The 5 laboratory sessions follow the lectures, where participants will apply system design concepts by designing, implementing, debugging and evaluating DSP schemes.

Digital System Design -- 4-day class with labs: FPGA DSP System Design

Overview: This course provides an in-depth and state-of-the-art coverage of the design and FPGA-based implementation of high-performance DSP systems. After presenting FPGA architectures and design tools by Xilinx and Altera, several hands-on design labs on DSP, digital communications and video/imaging will be covered, including FFT, FIR filters, error detection/correction circuits, modem, color space converter, and DWT (Discrete Wavelet Transform). Contents: Basic DSP/Communication theory, FPGA architecture/design tools, HDL (VHDL and Verilog), DSP-specific arithmetic circuits, hardware design of digital filters, FFT circuits, error detection & correction circuits, encryption/decryption circuits, and video/imaging circuits.

Analog/RF Design -- 4-day class with labs: Wireless Transmitters Overview: Power amplifiers play a major role in the overall performance of transmitters. There are a number of transmitter architectures that satisfy the linearity requirements of modulation techniques employed in short and long range communication applications. This exceptional course introduces modulation techniques and wireless standards, presents different transmitter and power amplifier architectures and compares the RF properties and performance of CMOS, SiGe and GaAs technologies. Covered are the critical relationships among linearity, power and spectral efficiencies, output power level and frequency of operation. The lab sessions involve using MATLAB/VerilogA simulators for behavioral characterization of transmitters by generating baseband signals of constant envelope and applying transmitter nonlinearities.

Department of Electrical Engineering

Review the full descriptions:

www.engr.sjsu.edu/eeshortcourse

for course overviews, prerequisites, instructor profiles, registration, map

Come to San Jose State! Easy access: class starts before most students arrive on campus, so parking in the 7th Street garage is a snap! Cost: $995 per course; $945 for IEEE Members (includes student notebook, lunches and refreshments; CDs with class notes and problem solutions for certain classes) Digital System Design -- 4-day class with labs: Embedded Systems and Embedded FPGAs Overview: This short course introduces the fundamentals of embedded system and embedded FPGA design methodology. It gives an overview of the technology, covers fundamentals and advanced issues, and gives hands-on experience with embedded FPGAs. The first part addresses fundamental concepts such as microprocessor architecture, bus functionality/arbitration, memory and I/O, interrupts, instruction set, real-time operating system (ROS), and drivers in a conventional embedded system. The second focuses on advanced embedded systems design including embedded FPGA implementation and practice. The lab provides hands-on experience with configuration of processor cores, developing IP with VHDL, writing drivers, system integration, and test. Students will be exposed to a learning experience balanced between fundamental and advanced issues, theoretical concepts and hands-on experiments that will allow them progress from novice to expert within a short time. Networking Engineering -- 4-day class with labs: High-Speed Data Networks Overview: This course emphasizes architectures, delay modeling, and the latest innovations in broadband computer communication networks. It presents detailed studies of design and analysis of high-speed switches and routers, design of input/output interfaces for fast routers with quality-of-service provisions, design of multicast switches and networks, delay modeling, bandwidth allocations and congestion control methods for broadband networks, voice compression for higher data rates, voice over IP, and the latest techniques in wireless communication systems. Labs focus on computer networks.

• All classes are Wed, March 29, thru Sat, April 1 • All classes are 8:30 AM – 4:30 PM • For additional information, or assistance with

registration, contact Irma Alarcon de Rangel Telephone : (408) 924-3938

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 11

Stackup Analysis Using Simulation Tools (HyperLynx)

Speaker: Chuck Troia, Signal Integrity/High Speed

Design Engineer, Cisco Systems Time: Social at 5:30 PM; Presentation at 7:00 PM Cost: none Place: Applied Materials Bowers Cafeteria, 3090

Bowers Ave., Santa Clara, RSVP: not required Web: www.scvemc.org

Chuck Troia is a Signal Integrity/High Speed Design Engineer presently working for Cisco Systems, Inc. He has provided Signal Integrity Support and EMC Engineering Support for over 7 years at Cisco, primarily in the Cable Business Unit in support of the design for Cable Modem Terminal Systems and cable modems. Chuck has nearly 20 years experience in EMC Design and Regulatory Support and has worked for Hewlett Packard and 3Com Corporation where his work included designing and building 3Com’s first EMC lab and test facility.

Chuck holds a B.S. degree in Electrical Engineering from Cal Poly (Pomona) and has been an Electrical Engineer since 1973. He was past Chair of the Santa Clara Valley EMC Chapter.

It is important for electronic and hardware engineers to not only be knowledgeable of the circuits and components they use in their designs, but also to understand and be familiar with the construction of the circuit board stack up. The stack up is the specification of the arrangement of circuit board layers that defines make-up of the circuit boards that are used in the implementation of the designs. This presentation will cover topics such as how to identify basic stack-up goals, and the major elements and requirements for PCB stack-up analysis. It will include examples of how to perform stack up analysis using a simple simulation tool and conclude with some simple thoughts on how to review the data and information available from a PCB vendor.

TUESDAY JANUARY 10SCV Electromagnetic Compatibility

Bernie Siegal

650-961-5900

info@thermengr.com www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 12

Enabling Technologies for Board-Level Optical Interconnects

Speaker: Dr. Alexei Glebov, Fujitsu Laboratories of

America Time: Seated dinner at 6:30 PM; presentation at

7:30 PM Cost: $25 if reserved by Jan 8; $30 at the door;

presentation-only is free Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale

RSVP: Please reserve and pay in advance using our PayPal on-line system or email Janis Karklins at Karklins@ieee.org

Web: www.cpmt.org/scv

Dr. Alexei Glebov is a research project manager in the Advanced Optoelectronics Technology Department at Fujitsu Laboratories of America in Sunnyvale. His main research focus is on board-level optical interconnects, optical switches and other planar photonic device fabrication and packaging technologies. He received his Diploma in Physics from University of St. Petersburg, Russia, and Ph. D. in Physics with Honors from University of Göttingen, Germany. Prior to joining Fujitsu Laboratories in 2000 he worked at the Max Planck Institute in Göttingen and Bell Laboratories, Lucent Technologies, in Murray Hill, NJ. Dr. Glebov published about 45 papers in peer-reviewed journals (citation index 400+), co-authored more than 40 conference contributions, made over 30 invited and regular presentations at international meetings and seminars, and has ~20 patents issued or pending. He is a senior member of IEEE LEOS and CPMT, and is a member of OSA and SPIE.

Facing approaching speed, bandwidth, density

and scalability limitations in high-speed printed circuit boards, optical interconnects (OI) emerge as a viable alternative. Many industrial and governmental organizations project that board-level OI will evolve for commercial applications in this decade. The 4-5 year product development cycle suggests that complete prototypes of the modules should become available in several years. Among possible solutions for board-level OI, the planar waveguide approach shows to be more competitive in terms of cost, passive element integration, component alignment tolerances, and manufacturability.

This talk will review various topics and technologies of board-level OI. A strong emphasis will be given to elementary technologies enabling fabrication of OI prototype modules. The talk will cover integrated low loss polymer waveguides with vertical routing capabilities, microoptic and waveguiding elements, 3D optical wiring schemes, in- and out-of-plane light coupling, optical connectors, etc. The prototype optical backplane operation at 10+ Gbps will also be presented.

WEDNESDAY JANUARY 11

SCV Components, Packaging & Manufacturing Technology, and Lasers and ElectroOptics

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

info@ozeninc.com www.ozeninc.com

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 13

Global Modeling and Design of Micro/nano Devices and Circuits

Speaker: Dr. Yasser A. Hussein, Stanford University

& UCLA Time: 6:00 PM - Refreshments and Social Hour;

6:30 PM - Presentation Cost: none Place: SC12-Auditorium, Intel Corp., 3600 Juliette

Lane, Santa Clara RSVP: not required Web: www.mtt-scv.org

Yasser A. Hussein (M'03) received the Ph.D. degree in Electrical Engineering from Arizona State University, Tempe, AZ in 2003, and the B.S. and M.S. degrees, both in Electrical Engineering, from Cairo University, Cairo, Egypt, in 1995 and 1998. He currently holds a joint research position at Stanford University and UCLA. He developed and taught a new graduate course on high-frequency models of semiconductor devices in the Electrical Engineering Department at Stanford University. His current research interests include high-frequency computer-aided-design (CAD) of micro/nano devices, electromagnetics, and microwaves.

Dr. Hussein is a Member of IEEE, an elected Member of Commission D of the United States National Committee of The International Union of Radio Science (USNC-URSI), and a nominated member for Sigma Xi. He has more than 30 publications including a book chapter on CAD development for microwave and millimeter-wave applications. He serves as a technical reviewer for several journals.

Global modeling of complete high-frequency devices and circuits requires the integration of circuit, electromagnetics, device transport physics, thermal, and mechanical simulators into a single package. While much attention is currently being focused on simulating the full electromagnetic field environment, the solid-state devices within the circuit are usually modeled using equivalent circuit elements and sources, behavioral models, or simplified carrier transport equations. Further, thermal and mechanical models are usually ignored.

In this talk, I will go over different models that couple an appropriate transport model for charge flow in the semiconductor devices with full-wave solution of Maxwell's equations. The semiconductor device simulators employed are based on the semi-classical Boltzmann transport equation using either moment expansions (drift diffusion DD and hydrodynamic models HD), or direct solutions employing particle based Monte Carlo approaches. Further, an efficient model to characterize high-frequency PIN switches will be provided. An accurate model for the problem based on a circuit model coupled with electromagnetics will be presented. The circuit model is extracted using a drift-diffusion physical model. Also, breakdown of the PIN diode is simulated by including the impact ionization phenomenon. S-parameters are calculated and compared to independent measurements.

Board Logic Systems

Complete Product Solutions Provider TM

Experienced consultants in the fields of: • Board & Verilog Design • Debug and Test • Signal Integrity • EMI • Power Electronics • Layout • Software Development • Documentation

www.boardlogics.com

info@boardlogics.com (650) 867-0869

WEDNESDAY JANUARY 12SCV Microwave Theory and Techniques

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 14

Semiconductor Equipment and Materials Outlook

Speaker: Dr. Dan P. Tracy, SEMI Time: Buffet lunch at 11:45 AM;

presentation at 12:15 PM Cost: $15 if reserved by Jan 14; $20 at door;

vegetarian available Place: Ramada Inn, # 1217 Wildwood Ave (Fwy

101 frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale

RSVP: using our PayPal link, or by email to John Jackson, Analog Devices, at john.jackson@analog.com

Web: www.cpmt.org/scv Dr. Dan P. Tracy is responsible for developing and executing a global strategy for SEMI industry research and statistics products and services and information products. Current market statistic monthly and quarterly programs cover capital equipment, materials and component markets, with in-depth annual reports on a variety of topics such as packaging materials, the China market and nanoelectronics. Tracy is responsible for preparing market reports and presenting on trends impacting the electronic materials and equipment markets globally. In addition, Tracy is also responsible for managing market statistics partnerships globally. Prior to joining SEMI in 2000, Tracy was a research associate with Rose Associates, where he focused on packaging materials market research. Prior to this, Tracy served in the Package Technology Group at National Semiconductor. Tracy has a Ph.D. in Materials Engineering from Rensselaer Polytechnic Institute, a masters of science in Materials Science & Engineering from Rochester Institute of Technology and a bachelors of science in Chemistry from the State University of New York (SUNY) College of Environmental Science and Forestry. Tracy has authored numerous market research studies and articles in industry trade publications. He is also the author of the monthly SEMI Book-to-Bill report.

Though contracting in 2005, the semiconductor capital equipment market will record billings at the third highest level in history. While the industry remains cautious, positive growth is anticipated in 2006 given the strength in the 300mm production ramp. There are 11 new 300 mm fabs expected to begin production in 2006 and a possible 12 new 300mm fabs in 2007. Paralleling the 300mm fab investment is the integration of new materials into the wafer fabs and into semiconductor packages. Both the fab and packaging materials grew in 2005, and growth is forecasted for 2006.

TUESDAY JANUARY 17SCV Components, Packaging & Manufacturing Technology

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 15

Beyond the Limits of Magnetic Recording: an Itinerant Magnetician Looks at

Hysterical Loops Speaker: Mason L. Williams, Hitachi Global Storage

Technologies (Retired) Time: Cookies & Conversation at 7:30 PM,

Presentation at 8:00 PM Cost: none Place: KOMAG, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Mason L. Williams received a B.S. in Engineering in

1964 from the California Institute of Technology, and the M.S.E.E. degree in 1966 and a PhD in Electrical Engineering with Physics minor in 1970 from the University of Southern California

In 1970, Dr. Williams joined IBM in San Jose, initially in a Manufacturing Research department. In his first year he was assigned to work with R. Larry Comstock on characterization and testing of experimental magnetite film media. That collaboration led to the so-called “Williams-Comstock” analytical model of digital magnetic recording. In 1982, he joined the Magnetic Recording Institute and managed an investigation of perpendicular magnetic recording. In 1985 he became manager of Advanced Recording Heads at the IBM Almaden Research Center in San Jose. In that role he managed the development of micro-magnetic modeling for magneto-resistive head elements and the first building of spin-valve head test structures to verify biasing techniques. In 1992, Dr. Williams became the IBM representative to the Ultra-High Density Magnetic Recording Head project of the National Storage Industry Consortium, aimed at 10 Gb/sq in technology. In 1996, he became part of the Extremely High Density Recording Strategy Team at INSIC. In 1999, he was elected to the IEEE grade of Fellow. In 2001, he was selected as an IBM Master Inventor, and holds several recording head patents. At the end of 2002, Dr. Williams retired from IBM and joined Hitachi Global Storage Technologies. He worked on novel perpendicular head approaches and then focused again on recording physics and integration modeling until retiring from Hitachi in 2005.

For several decades there have been declarations that digital magnetic recording as we know it is about to reach the ultimate limit of areal density. Technological advances have enabled steady progress primarily through simultaneous scaling of dimensions and tolerances over several orders of magnitude and use of materials with larger energy densities. In the 1990’s it became clear that then current approaches would be limited to about 40 Gb/ sq. in. by the combined requirements that individual grains have reversal barriers of above 40 kT for long term data retention and that a bit cell contain 100 or more grains for adequate media signal-to-noise. Recent areal density demonstrations at about 6 times that limit have been possible with perpendicular recording and improved materials, but perhaps we are again nearing the ultimate physical limits, unless a novel idea comes along. In addition to perpendicular recording, technologies suggested to extend the limits include patterned media, thermally-assisted writing and tilted media. We’ll discuss the potential advantages and challenges of these approaches. Areal density is primarily limited by write head materials and fabrication tolerances, while data-rate is limited by sensor technology which must provide several times kT of signal energy (and low noise levels) to detect a bit. Sensors have evolved from inductive heads to anisotropic magneto-resistive

heads to in-plane giant magneto-resistive (GMR) devices with CPP (current across the gap) GMR devices with spin-tunneling sensors also under consideration. We’ll discuss the attributes of these technologies and the anticipated requirements. Powerful error correction codes will also be required

if we are to reach 1 Tb/ sq. in, so attention must be paid to writing, reading and arithmetic.

TUESDAY JANUARY 17SCV Magnetics

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High Speed Networking in California Education

Speaker: Jim Dolgonas, President-COO, CENIC

(Corp for Education Network Initiatives in California)

Time: Presentation at 6:30 PM Cost: none Place: The Public Utilities Commission,

505 Van Ness Ave, San Francisco RSVP: not required Web: www.ewh.ieee.org/r6/san_francisco/comsoc

Jim Dolgonas is President and Chief Operating Officer of CENIC, a non profit corporation that represents the common interests of California's education and research communities in achieving robust, high capacity, next generation Internet communications services. Prior to joining CENIC Dolgonas served for 25 years in various technology leadership positions within the University of California system. He has served on various industry advisory committees, including those of IBM and SUN. Jim holds a Bachelors Degree from the University of California, Davis and an MBA from UCLA.

The presentation will discuss the critical role high

speed networking plays in all segments of education in the State. This will include a discussion of the role CENIC (Corporation for Education Network Initiatives in California), a non profit corporation, plays in providing high speed networking to all of California’s public educational institutions and to several prominent private Universities. Also included will be discussion of California’s leadership role in providing high end networking to research institutions across the nation.

Join us at the S.F. ComSoc for professional networking and interesting industry discussions. Make industry contacts, and maybe volunteer to make the SFComSoc active, rewarding and relevant for your needs.

TUESDAY JANUARY 17SF Communications

Mixed-Signal IC Development

• From Inception to Production Transfer • Turnkey, Design Services & Consulting • Design Reviews & TroubleShooting

Mixel, Inc. Excellence in Mixed Signal Design

(408) 274-2736 sales@mixl.com www.mixl.com

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 17

Marketing Your Consulting Practice on the Web

Speaker: Helen Kennedy, Nimbus Design Time: Networking at 7:00 PM;

Presentation at 7:30 PM Cost: none Place: Keypoint Credit Union, 2805 Bowers

Avenue (between Kifer and Central), Santa Clara

RSVP: not required Web: www.CaliforniaConsultants.org/notices.htm

Helen Kennedy is Director of Marketing and Business Development for Nimbus Design. She has a broad range of international business experience that includes positions in Internet Development, Worldwide Sales and Marketing, Strategy, Business Development, Technology, and Operations. Nimbus Design is the recent winner of two WebAwards for outstanding website development for its clients Juniper Networks and Elsevier MDL. Other Nimbus clients include Cisco Systems, Google, Namco, THX, Wham-O, Horn Murdock Cole and Dickson Allan.

You've got a website, but are you doing a good job of marketing yourself and your business? Why should you bother? Unless you are so busy with work that you never need to attract new clients, you may be missing your best opportunity to convince companies to engage you as a consultant.

Learn how to adapt common marketing principles to your individual practice, such as:

• What differentiates you from other consultants? • How can you establish your credibility? • Why does a professional image help you stand out

from the crowd? • What common mistakes can work against you on

your website? • Who looks at your website, and how do they find

it?

TUESDAY JANUARY 17SCV Consultants' Network of Silicon Valley

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

Visit our Marketplace (page 3)

Download Rates and Services information: www.e-grid.net/docs/marketplace-f lyer.pdf

GRID.pdf

e-GRID

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 18

Broadband over Power Lines - FCC Emissions Compliance

Guidelines Speaker: Jerry Ramie, NCT, ARC Technical

Resources, Inc. Time: Noon Cost: $6.00 (includes lunch) or Free (no lunch) Place: PG&E Building, 77 Beale St. Room 307,

San Francisco RSVP: by Jan 17 to Julian Ajello j.ajello@ieee.org

(415) 703-1327, or Chuck Magee cm1@cpuc.ca.gov (415) 703-4683.

Web: ewh.ieee.org/r6/san_francisco/pes

Jerry Ramie is the President and founder of ARC Technical Resources, Inc. which provides training, equipment, systems and services for Electromagnetic Compatibility (EMC). He is a member of the IEEE EMC Society, the dB Society and is a NARTE (National Association of Radio and Telecommunications Engineers) certified EMC technician. He can be reached at (408) 263 6486. Mr. Ramie has over 23 years experience in EMC and founded ARC Technical Resources, Inc. in 1989. Mr. Ramie authored an article on BPL Certification requirements in the August 2005 issue of Conformity.

By using ordinary power lines, Broadband over Powerlines (BPL) can provide high-speed internet access to subscribers without the need to install additional wiring. It provides competition for existing broadband providers such as Cable TV, Telephone and satellite and can be used for distribution automation and remote meter reading. BPL has a bad reputation for radio interference yet there are many fixes for interference problems. There is no excuse for BPL radio interference except ignorance.

Mr. Ramie will give us a snapshot of the state of BPL, and will go into some of the requirements and standards to prevent radio interference. He will also describe some of the equipment and techniques for enforcing those requirements.

WEDNESDAY JANUARY 18SF Power Engineering

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 19

Short Circuit and Coordination Analysis

Speaker: Glyn J. Lewis, P.E., Applied Power Time: Dinner 6:00 PM, Presentation 7:00 PM Cost: $25.00 IEEE members, $30.00 nonmembers,

and $10.00 students Place: Ramada Inn, 1217 Wildwood (near 101 and

Lawrence), Sunnyvale RSVP: to James Alvers, (925) 730-3105,

james.alvers@us.schneider-electric.com Web: www.e-grid.net/docs/0601-scv-pes.pdf

Mr. Glyn J. Lewis is a recognized authority who

graduated from the University of Wales Institute of Science and Technology in 1964. He has worked for two switchgear suppliers in the UK as a commissioning engineer, joined GE in 1968 and worked in several positions until forming Applied Power in 1981.

He has performed over 400 analytical studies on electrical distribution systems in the areas of short circuit analysis, coordination, load flow and motor starting and has been responsible for the design of numerous generating and cogenerating plants. He specializes in the design of high voltage systems and controls utilizing the latest technology devices.

Mr. Lewis has been selected for numerous IEEE presentations, classes and short courses that have been well attended and received.

The production of short circuit and coordination

studies is now more of a science than an art as in years gone by. The new science is the plethora of computer programs now available at comparatively low cost. People who have rigorously studied the multitude of standards have incorporated their methodology into these programs to produce technically accurate studies. However, the longstanding problem of interpretation still exists and requires further knowledge of the hardware devices and their application standards. This presentation provides some guidelines in the analysis of the studies’ computed and graphical results. Topics will include:

• Low and High Voltage Systems • All major system components: breakers,

switches & fuses, transformers, conductors, etc.

• Series Ratings, Selective Tripping and Ground Fault

So, please join us for an informative presentation and discussion.

WEDNESDAY JANUARY 18

SCV Power Engineering & Industry Applications

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 20

Stem Cell Applications in Biomedicine, Tissue Engineering,

and Regenerative Medicine Speaker: Daniel Kraft, M.D., Stanford University

Medical School Time: Dinner 6:15 PM, Presentation 7:30 PM Cost: none (parking is free after 4 PM) Place: Dinner with the speaker in the Stanford

Hospital cafeteria at 6:15 PM (no reservation needed); Presentation in Room M114 of the Stanford Medical School (see map on website)

RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs/

pages/upcoming.html

Dr. Daniel Kraft will provide an overview of stem cell biology, including embryonic and adult stem cells, their current use in the clinic, and ongoing developments in the push for therapeutic applications utilizing stem cells in biomedicine and the evolving field of tissue engineering and regenerative medicine. This talk will include a summary of major stem cell technologies, and related bioengineering and devices.

Daniel Kraft, MD is a physician-scientist at

Stanford University Medical School, where his clinical focus is hematology/oncology and stem cell transplantation. He is also on clinical faculty at UCSF on the bone marrow transplant service and is a lecturer for the Stanford Bioengineering program. Daniel graduated cum laude from Brown University, and received his medical degree from Stanford University, where he was also a Howard Hughes Research Fellow, and graduated with honors in research. He went on to complete a combined residency at Harvard in Internal Medicine and Pediatrics at the Massachusetts General Hospital and Boston Children's Hospital, followed by fellowships in hematology/oncology and bone marrow transplantation at Stanford. He is currently funded by the NIH and conducting research in the laboratory of Irv Weissman.

Daniel has extensive biomedical research experience, including at the National Institutes of Health, where his proof of concept publications demonstrating monoclonal antibody mediated inhibition of allergic reactions laid the groundwork for Xolair, an approved therapy by Genentech. Additional research at Brown University, Stanford, Systemix Inc, and Harvard has resulted in multiple peer reviewed publications. Daniel is also an avid pilot with extensive space life sciences research experience with NASA, and serves as a flight surgeon with an F-16 squadron in the California Air National Guard. He was recently a finalist in NASA astronaut selection.

Dr. Kraft has extensive medical device experience from his work with the Stanford Biodesign Innovation Program, and has two patents pending. He is the founder of StemCor Systems Inc, developing tools to enable stem cell therapy, including his invention for a minimally invasive device for the harvest of adult marrow derived stem cells. He previously founded 'The Online Medical Bookstore' which was acquired by Medinex Inc. as part of its IPO.

WEDNESDAY JANUARY 18

SCV Engineering in Medicine and Biology

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 21

Digital Storage for the Studio and the Home

Speaker: Thomas M. Coughlin, President, Coughlin

Associates Time: Refreshments and Networking at 6:00 PM,

Presentation at 6:30 PM Cost: $1 for food Place: Cypress Semiconductor, Building 3

Auditorium, 3901 N 1st St, San Jose RSVP: by email to Rukmini Sivaraman,

nsrukmini@ieee.org Web: www.ewh.ieee.org/r6/scv/gold/

scvgoldhome.php

T. M. Coughlin has degrees in Physics and Electrical Engineering with a minor in Materials Science from the University of Minnesota. His 25+ years of magnetic recording experience included flexible tape and floppy as well as rigid disk recording at such companies as Polaroid, Seagate Technology, Maxtor, Micropolis, Nashua Computer Products, Ampex and SyQuest. He has been active with IDEMA where he is chairman or a member of several committees. He is a senior member of the IEEE, was publicity chairman of the 1992, 1996, 2002, and 2004 TMRC conferences and is a past chair of the Santa Clara Valley Magnetics Society chapter and current Treasurer of the Santa Clara Valley IEEE Section. He has organized magnetic recording Symposia from 1997-2002 for IIST at Santa Clara University where he is also an adjunct professor. He is a member of the IEEE Computer Society, Association of Computer Machinery, American Physical Society, American Association for the Advancement of Science, and the American Vacuum Society.

One of the fastest growing segments of the digital

storage industry revolves around the creation, distribution and reception of entertainment content. This talk will discuss the various segments of this market as well as their growth trends and speculation on how new applications for digital storage for the entertainment value chain will change digital storage devices and architectures. Digital storage is a key enabling technology for creating high-resolution entertainment and for preserving this content for the future. Advanced tiered storage concepts are used in the distribution of this content to a growing number of audience channels from broadcast, cable, satellite, digital cinema to pod-casts. The growth of high capacity hard disk drives will enable greater than 1 Terabyte home storage devices for Digital Video Recording and Home Media sharing in the very near future. Improvements in power management and power sources as well as high capacity small form factor disk drives and flash memory will give portable devices copious libraries of content as well as enable new types of personal content capture and sharing that could create huge markets for the coming decade. Finally home and personal storage devices will become networked into a home storage utility that will automatically backup and preserve personal content no matter where it is in and around the house, sort and index that data for the greatest use and make sure that content is where it should be, when it should be there.

T. M. Coughlin (cont.)

Since 1997 Tom has written market and technology analysis reports and articles including the Digital Entertainment series focusing on data storage and the creation, distribution and reception of entertainment content, Computer Peripheral Test and Process Equipment Report and the New Applications for Data Storage Market and Technology Report. He has given technology and market assessment presentations at the annual Storage Visions and Network Storage conferences, IDEMA and IIST Symposia and for the IEEE Magnetics Society. He has published over 50 articles, reports, technical papers and presentations. He has provided marketing, intellectual property and technology assessments and projections for several data storage technology companies, company analysts, and venture capitalists including Engenio, Network Appliance, PriceWaterHouseCoopers, and The Woodside Fund. In addition he has served as project and general manager for technical projects involving budgets of several million dollars.

WEDNESDAY JANUARY 18SCV Grads of the Last Decade (GOLD)

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 22

Best Talks from the International Symposium for Testing and

Failure Analysis Panel Members: organized by Art Rawers and

Leo Henry Time: Refreshments and Networking at 6:30 PM;

Presentation at 7:00 PM Cost: none Place: Hewlett Packard Oak Room, Bldg 48 (near

Pruneridge Ave. and Wolfe Rd), Cupertino RSVP: not required Web: www.ewh.ieee.org/r6/scv/rs

The International Symposium for Testing and Failure Analysis (ISTFA) provides a forum for the latest developments in wafer, chip, package, and board level test and failure analysis. The 31st ISTFA was held November 6-10, 2005, in San Jose. Information on ISTFA is available on the web at http://www.asminternational.org/istfa/. The January Santa Clara Valley IEEE Reliability Society meeting is a joint meeting with the Santa Clara Valley ESD Society. The joint meeting will feature a panel discussion of selected papers from ISTFA. The panel is being organized by Art Rawers and Leo Henry. We are looking for additional panel members, especially ISTFA attendees. If you are interested in helping select papers, being on the panel, leading a discussion, or contributing in another way, please e-mail us at reliability@ieee.org.

WEDNESDAY JANUARY 18SCV Reliability

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 23

Introduction to the Stanford Nanofabrication Facility and

Research Examples Speaker: Paul Rissman, Director of Research

Operations, Stanford Nanofabrication Facility

Time: Refreshments at 6:00 PM, Presentation 6:30 PM

Cost: donation for food/drinks Place: National Semiconductor Building 31

Auditorium, 955 Kifer Road, Sunnyvale RSVP: by email to

ssc_scv_rsvp@yahoogroups.com Web: www.ewh.ieee.org/r6/scv/ssc

Paul Rissman is the Director of Research Operations of the Stanford Nanofabrication Facility at Stanford University. His undergraduate and graduate education was in Electrical and Computer Engineering at the University of Wisconsin in Madison. Paul worked 26 years in the semiconductor industry, including 2 years at Amdahl Corporation, 20 years at Hewlett Packard, and 4 years at LSI Logic, serving in various management positions for the last 19 years. He has 26 publications, 4 patents granted, 2 patents filed, and 2 patents disclosed in the fields of semiconductor processing, electron beam lithography, superconducting junction technology and other fields.

The Stanford Nanofabrication Facility is part of the

SNF's National Nanotechnology Infrastructure Network. It is a research and development facility with a wide variety of semiconductor processing equipment that is open to external use. In a typical month, there are 200 users of the facility comprised of 120 Stanford graduate students, 20 students and faculty from other universities, and 60 industrial users, primarily from start-up companies. Projects in the lab come from the study of MEMS/NEMS, bio-MEMS/NEMS, sensors/actuators, nanotubes/ nanowires, semiconductor materials and device research, magnetic technology, photonic devices and many other fields.

THURSDAY JANUARY 19SCV Solid State Circuits

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 24

Overview of the Stationary Fuel Cell Market

Speaker: Joseph R Heinzmann Director of Business

Development - West Region, FuelCell Energy

Time: No-host social at 5:30 PM; Presentation at 6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM

Cost: $22 for IEEE members; $25 for non-members

Place: Marie Callender's Restaurant - The Garden Room, 2090 Diamond Blvd, Concord (near the Concord Hilton)

RSVP: by email by January 17th to Gregg Boltz gboltz@brwncald.com or telephone (925) 210-2571

Web: ewh.ieee.org/r6/oeb/ias.html

Joseph Heinzmann is the West Region Director

of Business Development for FuelCell Energy. He has a dual degree in Marine and Mechanical Engineering from the California Maritime Academy. His practical expertise encompasses onsite-distributed generation, generator controls and protection, automated control systems and onsite generation project economics.

At FuelCell Energy Mr. Heinzmann is responsible for working with both end customers and FuelCell Energy’s Distributors to develop economically justified solutions that promote the use of Fuel Cells in the commercial marketplace. Additionally Mr Heinzmann works within the regulatory arena to develop sound policy that benefits all Californians with ultra clean, efficient and reliable power. Mr. Heinzmann was formerly the West Region Power Users Technical Sales Leader for the General Electric Company.

This presentation will provide an overview of the

Stationary Fuel Cell Market, the drivers that are propelling this market and an overview of the world’s leading supplier of high temperature stationary fuel cells, FuelCell Energy.

THURSDAY JANUARY 19OEB Industry Applications

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 25

EDA Challenges for Low-Power Design

Speaker: Anand K. Iyer, Encounter platform

marketing director,Cadence Design Systems

Time: Fast Food & drinks at 6:30; Presentation at 7:00 PM

Cost: none Place: Cadence, bldg. 5, 2655 Seely Avenue,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/cas

Anand K. Iyer is a product marketing director for

Encounter platform at Cadence Design Systems, Inc. His main focus is low power design tools. He has published several papers and articles and has been quoted in a recent Electronic Engineering Times article on low power designs. He is closely involved in supporting several low power customer designs. He has been with Cadence for the last six years. Previously, he worked at HAL Computer Systems, a wholly owned subsidiary of Fujitsu, for 6 years as CAD Manager. He received his MBA from Santa Clara University in 2002, MSEE from the University of California, Santa Barbara in 1994 and M.Tech in Reliability Engineering from IIT, Bombay, in 1992.

Low power techniques in design are becoming

prominent because of the growth in mobile applications as well as the higher leakage currents in advanced process technology. Once relegated to wireless and medical designs, the power reduction techniques are widely used in designs today. Designers have a wide choice of low power techniques such as power gating and dynamic voltage frequency scaling. This talk addresses the range of power reduction techniques available to the designer and weighs the relative advantages and disadvantages of these options. Finally, it gives recommendation as to how to decide between these techniques.

MONDAY JANUARY 23SCV Circuits and Systems

Digital Chip Design Services

ASIC Design • EDA Evaluation • Verilog HDL • Synthesis • Design for Visibility • Timing • Scan • Verification • Low Power techniques • Power Analysis • BIST • DFT • ATPG • Silicon Debug

Testable logic for high-volume production with low DPM

Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)

m.siddappa@ieee.org 408-981-6612

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 26

Consumer Electronics Show Debrief

Speakers: CES Chapter officers who attended the

Conference Time: 6:30 PM Cost: none Place: Oak Room, HP campus at Pruneridge and

Wolfe (off 280), Cupertino RSVP: not required Web: www.ewh.ieee.org/r6/scv/ce

Photos and descriptions of interesting new products and technologies from the Consumer Electronics Show (CES) and the International Conference on Consumer Electronics (ICCE), held earlier in January in Las Vegas.

For several publicized CES events (Storage Visions and the “Great Minds – Great Ideas” sessions, see Page 5.

TUESDAY JANUARY 24SCV Consumer Electronics

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 27

Medium Voltage Distribution Equipment

Speaker: Gary H. Fox, General Electric Company Time: 5:30 PM social; 6:00 PM presentation;

7:00 PM dinner Cost: $25 (At the door) Place: Sinbad's Restaurant, Pier 2 The

Embarcadero, San Francisco RSVP: Email Jack Lin, jlin@sfwater.org to reserve

and to qualify for the drawing Web: www.ewh.ieee.org/r6/san_francisco/ias

Gary H. Fox received his BSEE from California Polytechnic State University, San Luis Obispo in 1978. He became a Member of IEEE in 1989, and a Senior Member in 2001. He has been employed by General Electric Company for 27 years. His current assignment is as a Systems Engineer for GE Industrial in Concord, providing application and technical support for power distribution and control equipment. Mr. Fox is a member of the IEEE Industry Applications and IEEE Power Engineering Societies. He has held several IEEE officer positions including Chair for the San Francisco Chapter, IAS; Chair, San Francisco Section; and Chair, San Francisco Bay Area Council. In addition, he has lectured at several local IEEE workshops covering the subjects of high voltage substation design, short circuit calculations, and power system protection. He has been a Professional Engineer licensed in California since 1982.

The presentation will cover the applications typically served by medium voltage equipment and found in the Bay Area/Northern California, including utility service requirements, types of distribution equipment available, overview of MV circuit breakers and fuses, the ANSI device numbers, and the information that should be included on a well-drawn single-line diagram.

TUESDAY JANUARY 24SF Industry Applications

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 28

MultiLayer Ceramic Capacitor (MLCC) Value Drift

and Embedded Passives

Speakers: Dr. Daniel N. Donahoe, Exponent Inc,

and Dr. Nicholas Biunno, Sanmina-SCI Time: Seated dinner at 6:30 PM; presentations

at 7:30 PM Cost: $25 if reserved by Feb 5; $30 at the door;

presentation-only is free Place: Ramada Inn, 1217 Wildwood Ave (Fwy

101 frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale

RSVP: Please reserve and pay in advance using our PayPal on-line system or email Janis Karklins at Karklins@ieee.org

Web: www.cpmt.org/scv Dr. Daniel N. Donahoe is a Managing Engineer

in Exponent’s Mechanical Engineering and Materials/Metallurgy practice. Dr. Donahoe has over two decades of industrial experience working with defense electronics and commercial electronics. Prior to joining Exponent, he has been employed at Lockheed, Motorola, Ford Aerospace, Teledyne, Compaq Computer and Iomega, and the University of Maryland’s industry and government sponsored CALCE Electronic Products, and Systems Center. His functional assignments include work as a design engineer, reliability engineer, thermal engineer, manager, technologist, and scientist. In military electronics he worked on electronics exposed to extreme environments ranging from the high acceleration loads of gun launch to thermal challenges faced in life support and the design of radar systems. In addition to electronic products exposed to exotic environments, he has worked on cost-driven commercial electronics products such as cooling of computer components. He has worked on integrating rack and stacked electronics into facilities, especially focusing on the design of HVAC (Heating, Ventilation and Air Conditioning). His electronic packaging analysis skills include thermal analysis, stress and dynamics analysis and failure analysis.

(continued, next column)

As IC progress drives more functionality onto

each IC, fewer ICs are typically placed on each PCB. In addition to this trend, ever-increasing operating frequencies and lower IC voltages require more passive components. As a result, the multilayer ceramic capacitor (MLCC) has become the most common component used in digital electronics.

The capacitor industry has not stood still while the IC industry moved forward. MLCCs have continued to shrink in size, primarily to satisfy the requirements driven by modern handheld products such as cell phones. In addition, an almost 10 times market spike in the price of palladium (electrodes were made of silver and palladium are called precious metal capacitors) forced the industry to transition to nickel electrodes. The use of nickel electrodes in a MLCC is termed base metal electrodes (BME). Today, most MLCCs are BME.

Humidity testing for both precious metal electrode and base metal electrode (BME) capacitors showed that the precious metal capacitors aged according to a well known aging mechanism, but the BME capacitors degraded to below the failure criterion at 500 hours of exposure. The reasons for this new failure mechanism are complex. This talk will outline the testing and provide a theory why this degradation was witnessed. Standard testing protocols will likely not uncover this problem.

(continued …) His Ph.D. dissertation on ceramic capacitors included failure analysis work using modern tools of failure analysis including the environmental scanning electron microscope (ESEM™), electron backscatter diffraction (EBSD) and focused ion beam (FIB). Dr. Donahoe has worked on several industry standards related to electronics. He has also served as an Associate Editor of the IEEE Transactions on Components and Packaging Technologies for seven years.

Dr. Nicholas Biunno is a Principal Scientist for

the PCB Division of Sanmina-SCI. Current projects include embedded passives, new product development and high speed electrical properties characterization for PCB laminates. He is a member of CPMT's Technical Committee on Discrete and Integral Passives.

WEDNESDAY FEBRUARY 8SCV Components, Packaging & Manufacturing Technology

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 29

Biometrics: A Brief History and Review of Current Programs

Speaker: Dr. James L. Wayman, Director,

Biometric Identification Research Program, San Jose State University

Time: Dinner 6:15 PM, Presentation 7:30 PM Cost: none (parking is free after 4 PM) Place: Dinner with the speaker in the Stanford

Hospital cafeteria; Presentation in Clark Center Auditorium (see map on website)

RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs/

pages/upcoming.html

Dr. Jim Wayman is Director of the Biometric Identification Research Program of San Jose State University. He received the Ph.D. degree in engineering in 1980 from the University of California, Santa Barbara. In the 1980s, under contract to the U.S. Department of Defense, he invented and developed a biometric authentication technology based on the acoustic resonances of the human head. He joined San Jose State University in 1995 to direct the Biometric Identification Research Program, serving as Director of the U.S. National Biometric Test Center at San Jose State from 1997-2000. He has written dozens of book chapters and journal articles on biometrics and is co-editor of J.Wayman, A. Jain, D. Maltoni and D.Maio (eds) Biometric Systems (Springer, London, 2005). He is a Fellow of the British Institution of Electrical Engineers, a "Principal UK Expert" on the ISO/IEC JTC1 SC37 standards committee on biometrics, a "core member" of the U.K. Biometrics Working Group, a member Biometrics Executive Committee of the U.K. Home Office, a member of the EC-funded BioSecure Network of Excellence and a member of the International Board for External Review and Validation of the US Dept of Homeland Security. He is also a member of the U.S. National Academies of Science/National Research Council Committee "Whither Biometrics?" and previously served on the NAS "Authentication Technologies and their Implications for Privacy" committee. He holds 4 patents in speech processing and has served as a paid biometrics advisor to eight national governments. His Erdos number is four.

Although it was the Frenchman Alphonse Bertillion

who developed the first scientific method of recognizing people in the1870s, it was the British who simplified and advanced the art and science of human recognition with the development and promotion of fingerprinting in the decades that followed. It took Californians, however, to apply computers to automating these processes in the 1960s. In this talk, we will review British and Californian contributions to automated human recognition (a field now called "biometrics"), explain a bit about the recent algorithmic approaches to face and iris recognition, and discuss current national biometric programs within both governments.

WEDNESDAY FEBRUARY 15SCV Engineering in Medicine and Biology

Professional Consulting Services to assist clients in developing & executing any and all elements of Reliability throughout an Organization & Product Life Cycle.

• Assessments • Goals • Benchmarking • Reliability Prog. Plans • MTBF Pred • FMECA • EOL Assessment • Warranty Analysis • HALT/HASS • DVT/V&V • Rel. Demo. Tests • Software Reliability • CAPA/CLCA • DoE • Training/teaching • RoHS/WEEE Transition

pioneered Reliability IntegrationSM - using multiple tools in conjunction to increase the power and value of any Reliability Program.

(408) 472-3889 info@opsalacarte.com www.opsalacarte.com

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 30

Magnetic Biochips: Laboratory Curiosity or Killer App?

Speaker: Prof. Shan X. Wang, Materials Science &

Engineering and Electrical Engineering; Director, Center for Magnetic Nanotechnology, Stanford University

Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM

Cost: none Place: KOMAG, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Dr. Shan Wang currently serves as the director of the Center for Magnetic Nanotechnology and is an associate professor in the Department of Materials Science & Engineering and jointly in the Department of Electrical Engineering at Stanford University. He is also with the Geballe Laboratory for Advanced Materials, and is affiliated with Stanford Bio-X Program. His current research interests lie in magnetic nanotechnologies in general and include bio-magnetic sensing, magnetic microarrays, novel magnetic nanoparticles, magnetoresistive materials and spin electronics, magnetic inductive heads and soft magnetic materials, as well as magnetic integrated inductors. He has published over 100 papers and holds 11 patents (issued and pending) on these subjects. He and Alex Taratorin also published a book titled "Magnetic Information Storage Technology" through Academic Press. Dr. Wang was among the inaugural group of Frederick Terman Faculty Fellows at Stanford University (94-97), and an IEEE Magnetics Society Distinguished Lecturer (2001-2002). He also received an IBM Partnership Award in 1999, and was selected to the CUSPEA program organized by Nobel Laureate T. D. Lee in 1986. He has served the IEEE Magnetics Society in many capacities, most recently as the Finance Chair (2002-3), Local Chair for TMRC’03 and 05, and Program Chair for Intermag’06. He received the B.S. degree in physics from the University of Science and Technology of China in 1986, the M.S. in physics from Iowa State University in 1988, and the Ph.D. in electrical and computer engineering from the Carnegie Mellon University (CMU) at Pittsburgh in 1993.

We are developing a sensitive and quantitative

DNA detection system which is based on magnetic nanotags (nanoparticles) and spin valve sensor arrays. The magnetic biochips can be used for rapid and portable DNA fingerprinting, pathogen detection, and functional genomics. We have designed and fabricated several types of such magnetic biochips (MagArray) consisting of arrays of spin valve detectors with appropriate dimensions, surface chemistry, and microfluidics. An ASIC circuit with a footprint of 2 mm by 2 mm and including row and column addressing decoders and parallel fast readout schemes have been designed and fabricated. The MagArray chips feature redundant and high density of sensors, with a sensor density as high as 0.1 million sensors per squared cm. An advanced electronic test station has been set up as a demonstration vehicle for the integrated evaluation of our magnetic biochips with the custom magnetic nanotags and DNA-based biochemistry. Real-time detection of biological events has been successfully performed in laboratories, suggesting that MagArray holds unparalleled capabilities as compared to existing biochip technologies. Several practical issues need to be addressed in time for MagArray to emerge as a killer application for biomedicine in the near future.

TUESDAY FEBRUARY 21SCV Magnetics

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 31

SCV Education Education Challenges in the Age

of Nano-Scale Technologies Speaker: Dr. Ali Iranmanesh, Chairman and CEO,

Silicon Valley Technical Institute Time: Pizza/drinks at 6:30 PM;

Presentation at 6:45 PM Cost: none Place: Silicon Valley Technical Institute, 1762

Technology Drive, Suite 227, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/es

Dr. Ali Iranmanesh received his MS and Ph.D. in Electrical Engineering and Physics from Stanford University in 1983, and Master in Business administration from San Jose State University in 1995. During the past 3 decades he has been actively involved with many leading Silicon Valley companies such as Advanced Micro Devices, Fairchild, National Semiconductor, and Synopsys. He is a semiconductor industry veteran, having participated in the development of many generations of advanced semiconductor technologies and design methodologies that have resulted in many advancements in the field as well as earning him nearly 50 US and international patents. In 1999 he founded the International Society for Quality Electronic Design (ISQED), a multidisciplinary international organization devoted to the advancement of design for quality and manufacturing. The ISQED conference, which is now in its seventh year, has been a leading design and design automation conference with worldwide reputation and participation. In 2000 he joined the founding team of Tavanza Inc. a wireless communication startup that was successfully acquired by Anadigics Inc.

Dr. Iranmanesh is the chairman of Ascend Design Automation, and the founder and Chairman of Silicon Valley Technical Institute (SVTI) where he is now serving as the president and CEO. He is a Senior IEEE member, senior member of the American Society for Quality, and the Vice Chair of the IEEE Education Society Chapter in the Santa Clara Valley.

Over the past several decades, advances in

semiconductor technology and manufacturing – combined with a relentless device-scaling trend – have resulted in a phenomenal increase in the transistor count per chip. This powerful trend (known as Moore’s Law) has provided the fuel for economic growth and resulted in tremendous gains for the electronics industry in much of the industrial world. As the obstacles to traditional device scaling are mounting, emergence of Nanotechnology and its impact on Nanoelectronics promises the dawn of a new and exciting age. Nanotechnology represents a powerful set of technologies destined to shape the future of the electronics industry and create a vast array of other new and exciting industries. Throughout all these years, universities and educational organizations – which have been training generation after generation of engineers for the micrometer era – have remained relatively unchanged. However, due to recent advancements in technology and business globalization, these organizations too are finding themselves in the midst of powerful transforming changes; such changes are bound to raise many challenges and threaten to evolve the landscape of higher education for the years to come. This presentation explores these topics and examines how they could alter the future of education in the era of the nanometer generation.

WEDNESDAY FEBRUARY 22

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 32

Restriction of Hazardous Substances (RoHS) Directive Implementation Challenges

and RoHS: Long-Term Perspective

and Legal and Trade Challenges Speakers: Thomas Ellison, Finisar and

John Burke, Optichron Time: Seated dinner at 6:30 PM; presentations

at 7:30 PM Cost: $25 if reserved by March 5; $30 at the

door; presentation-only is free Place: Ramada Inn, 1217 Wildwood Ave (Fwy

101 frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale

RSVP: Please reserve and pay in advance using our PayPal on-line system or email Janis Karklins at Karklins@ieee.org

Web: www.cpmt.org/scv

Thomas Ellison has worked in electronics manufacturing for the last 17 years. His experience includes research and development work in vapor phase soldering and nitrogen inerting of reflow ovens while at Air Products and Chemicals, ASIC design management and process engineering management of a high volume surface mount assembly facility for Trimble Navigation, and SMT and fiber optic transceiver engineering for Finisar Corporation. More recently Tom has been the lead technical engineer for Finisar's RoHS compliance efforts. He provided technical leadership for Finisar's conversion to lead-free soldering processes and is currently working on component issues, materials declarations and data management aspects of RoHS compliance. He has a B.S. in Chemistry from University of Missouri - Rolla and an M.S. in Materials Science and Engineering from Iowa State University.

John Burke founded the UK based Surface Mounted and Related Technologies (SMART) Group in 1984, and has worked in the area of advanced manufacturing for many years. He has taught at various universities on technology, including university of Dundee, University of Hull, University of Limerick and University of Cambridge. (continued, next page)

RoHS Directive Implementation Challenges Implementation of the Restriction of Hazardous

Substances (RoHS) Directive presents special challenges for small and medium sized companies. Limited staff and dependence on outsourced services creates cost burdens for smaller OEMs.

The first major challenge is conversion of existing product Bills of Materials. Conversion is usually much more involved than just re-specifying RoHS compliant parts on the AVL. For some components, it may be difficult to eliminate the offending RoHS element (Cd, Pb, etc.) and still have the product function successfully. Major corporations have been active in proposing and receiving special exemptions from the TAC committee but further additions seem less likely without substantial data.

A second major challenge is the "due diligence" process of collecting, compiling and evaluating supplier certificates of compliance and materials declarations for the multiple suppliers of hundreds of components. New database systems must be added, populated and sustained. Since most "due diligence" protocols advocate random component testing, arrangements must be made to screen and chemically test sample lots from most suppliers. Testing at the assembly level for extremely low levels of the six RoHS elements at the homogenous constituent layer level is problematic for many tiny electronic components. In some cases, it may take 5-10 components to make up the minimum quantity required for chemical testing. Yet Pb is exempt in some layers while forbidden in other layers of the same component.

A third major challenge is assessing the reliability impact of conversion to RoHS. Thankfully, national and international consortia have addressed many of the major technical issues but each company must still address the impact of tin whisker mitigation strategies, SAC alloy fatigue behavior and higher reflow temperatures on their specific products. In most cases, converted products must be completely re-qualified to assess the impact of these changes on reliability.

RoHS: Long-Term Perspective The much-heralded WEEE deadlines arrived - and

passed -- with no fanfares, just another date on the calendar, and the July 1 2006 RoHS deadline will be just the same. The difference though, as we all know, is that these dates transitioned any manufacturer (continued, next page)

WEDNESDAY MARCH 8SCV Components, Packaging & Manufacturing Technology

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 33

John worked on the generation of IPC 1752 as a part

of the 2-18 committees, and dealt with reporting standards for hazardous materials. For many years he has been involved in the drive towards environmentally sound electronics assemblies, and has been heavily involved in trying to aid engineers caught up in the drive towards RoHS and JIG compliance.

John is currently employed by Optichron Inc., a fabless semiconductor vendor based out of Fremont, as the Senior Operations Manager.

Thomas Ellison

shipping products into Europe from the crystal clear waters of margin-based commerce into the murkier waters of environmental compliance.

This talk looks back on the RoHS legislation, looks at what is good about it (the environmental protection) and what is bad about it (the way it has been implemented). It considers how such legislation can be handled by the industry going forwards, particularly in view of the next impending round of legislation which will be directly impacting the product design in terms of its ease of recycling.

The talk also considers how manufacturers need to address the "worth" of compliance data from their vendors, the route by which it arrived, and the guarantees which came with it. This part of the talk will take the form of a series of "what if" scenarios should a company be challenged on its product compliance, and hopefully will throw some light onto the correct way to approach data collection and audit procedures.

Professional Consulting Services to assist clients in developing & executing any and all elements of Reliability throughout an Organization & Product Life Cycle.

• Assessments • Goals • Benchmarking • Reliability Prog. Plans • MTBF Pred • FMECA • EOL Assessment • Warranty Analysis • HALT/HASS • DVT/V&V • Rel. Demo. Tests • Software Reliability • CAPA/CLCA • DoE • Training/teaching • RoHS/WEEE Transition

pioneered Reliability IntegrationSM - using multiple tools in conjunction to increase the power and value of any Reliability Program.

(408) 472-3889 info@opsalacarte.com www.opsalacarte.com

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 34

Professional Selling in a Competitive Market:

Systematic B2B Sales Techniques to Substantially Increase

Your Revenue Speaker: Gerd Neumann, Ph.D., GN Consulting, LLC Time: Networking at 7:00 PM;

Presentation at 7:30 PM Cost: none Place: Keypoint Credit Union, 2805 Bowers

Avenue (between Kifer and Central), Santa Clara

RSVP: not required Web: www.CaliforniaConsultants.org/notices.htm

Dr. Gerd Neumann is President and CEO of GN Consulting, LLC, a firm that provides expertise in business consulting. Gerd has achieved measurable and lasting increases in revenue and profit with companies in a variety of business sectors by applying systematic and successful sales techniques for sales teams and management tools for sales managers. He helps managers achieve their sales goals.

Gerd has extensive experience in general management. During his work as CEO of Nokia Cable, he handled multiple business cultures and successfully developed and implemented visions for future businesses. His strong results-orientation is demonstrated by substantial revenue and profit increases during his tenure.

He has more than 20 years of experience in sales, and has been Vice President of Sales in the telecommunication and data network equipment industry. He has managed a profit center with more than 80 sales persons, and he has personally started new business sectors using his marketing and sales skills.

His educational background includes a Ph.D. in Physics from the University of Cologne, Germany, and he has extensive experience with and understanding of European cultures and businesses.

The goal of all businesses is to generate profit, which requires getting customers/clients. That’s why the process of winning customers is one of the most important processes in every company. It consists of:

a) The Marketing Cycle: How to get leads and how to turn leads into prospects?

b) The Sales Cycle: How to turn prospects into customers / clients?

After an introduction into the marketing and sales cycles, Gerd will present proven techniques which can be used to win sales projects in a competitive market without sacrificing price. He will address “Business Analysis (of your prospect’s business)” and the “Extended Value Concept” to better financially justify your business' offerings, and to differentiate them from those of your competition. Gerd will also discuss “Relationship Management,” how to make relationships measurable, and how to actively fight competition. Finally, he will address the issue of every business owner: how to make the sales process measurable so you can better judge the status of your sales projects at any time within a sales cycle.

TUESDAY MARCH 21SCV Consultants' Network of Silicon Valley

J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 35

CONFERENCE CALENDAR

The CONFERENCE CALENDAR is a service to our IEEE Members. It outlines upcoming IEEE workshops and conferences in the Bay Area. Please submit items to the GRID Editor: editor@e-grid.net.

Conferences are also encouraged to purchase display space in the GRID.pdf and publicize their events on our website and in our e-GRID email notification service. For the Conference Publicity flyer, please download:

www.e-gr id.net /docs/conf- f lyer .pdf

Int'l Consumer Electronics Show:

The 2006 Storage Visions Conference

-- January 6 & 7, 2006 -- Las Vegas Convention Center -- Concurrent with the Consumer Electronics Show -- Admission to the CES Exhibits

Hear the latest on digital content technology from industry leaders -- those who matter in the entertainment value chain -- and find out how current and coming trends can benefit your company.

See Page 4

For more details

DesignCon 2006 -- Connecting the World of Electronic Design

-- Conference February 6-9, 2006 -- Santa Clara Convention Center -- Exhibits February 7-8

Developed specifically for semiconductor and electronic design engineers, DesignCon is the essential design engineering event addressing the challenges facing these communities and providing the solutions attendees can implement immediately in their designs.

See Page 7

For more details

Internationalization and Unicode Conference

• March 6-8, 2006 • Hyatt Regency Hotel, Burlingame (SF Airport) • Tutorials: Monday, March 6 • Sessions: Tuesday-Wednesday, March 7-8 Unicode experts, implementers, clients and vendors are invited to attend this unique conference on the Unicode Standard and internationalization. Exchange ideas with leading experts, find out about the needs

of potential clients, or get information about new and existing Unicode-enabled products. See www.unicodeconference.org/ieee

for more details

Game Developers Conference GDC:06

-- Conference March 20-24, 2006 -- San Jose Convention Center -- Exhibits March 22-24

Next-gen game development will revolutionize every aspect of the gaming industry, and in turn influence other technology sectors that use advanced display, simulation, and interactive technologies. Concurrent with:

GDC Mobile 2006 - March 20-21, 2006 - Fairmont Hotel, San Jose

Serious Games Summit GDC - March 20-21, 2006 - Fairmont Hotel, San Jose

See Page 5

For more details

Workshops from the IWPC: Wireless Mobile Broadband Markets –

Hype or Reality?

-- January 23-24, Westin Hotel, SF Airport (Millbrae)

Which wireless systems and technologies will have a financial impact on wireless industry markets in 2006 and beyond? The investor community has its view; industry leaders have their views.

Wireless GigaBit Transport for Distributed Antenna Systems

– Is it a Viable Option?

-- January 24-26, Westin Hotel, SF Airport (Millbrae)

The worldwide demand for cost-effective mobile wireless voice and data infrastructure continues to grow -- the challenge is to achieve more uniform coverage with increased datarates. Solutions such as WCDMA, HSDPA, etc. are emerging.

See Page 9

For more details

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J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 36

Calls for Papers

IEEE Radio Frequency Integrated Circuits Symposium

• Paper Summary Deadline: January 2, 2006 • Location: San Francisco, June 11-13, 2006 RFID’06 is part of Microwave Week in San Francisco. Check out the Call for Papers for topics.

Go to www.e-grid.net/docs/rfic06.pdf to download the Call for Papers

IEEE Computer Society Symposium on Field-Programmable Custom Computing Machines

• Abstract Deadline: January 13, 2006 • Location: Napa Valley Marriott, April 24-26 2006

FCCM is a forum for presenting new research on reconfigurable computing -- the use of field-programmable technologies for high performance and/or low energy computation.

Go to www.fccm.org to download the Call for Papers