goepel electronics tap checker
DESCRIPTION
Learn about TAP Checker, a software tool for BSDL verification and automated validation of chip-level JTAG / boundary-scan implementations; support for multi-chip modules; IEEE 1149.1 and IEEE 1149.6 compliant; VHDL, VERILOG, and STIL output;TRANSCRIPT
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Automated validation of JTAG / boundary scan implementations
(C) 2012 GOEPEL Electronics, Austin, TX / USA
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Outline
• Why implement JTAG in ICs in the first place?
• Why validate and verify JTAG implementations?
• Automating the validation of JTAG implementations
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Benefits of JTAG / boundary scan
• Test for manufacturing defects at board and system level
• Access to on-chip test / debug / emulation resources
• In-system programming
• Efficient ATPG tools, pin level diagnostics
• Deterministic (predictive) test coverage
• Standardized:IEEE 1149.1, 1149.4, 1149.6, 1149.7, 1500, 1532, P1149.8.1, P1687, ...
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© 2012 GOEPEL electronics JTAG/Boundary Scan
JTAG / boundary scan applications
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Outline
• Why implement JTAG in ICs in the first place?
• Why validate and verify JTAG implementations?
• Automating the validation of JTAG implementations
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Why verify JTAG implementations?
• IEEE standard compliance
• Enable your customers to reap the benefits of JTAG
• Board / system applications:
• Connectivity tests rely on Boundary Register, EXTEST functionality
• Multiple devices daisy chained need to coexist
• Reliance on correct description of JTAG features (BSDL)
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• Automated generation of test bench based on BSDL
• IEEE 1149.1 and IEEE 1149.6
• Support for multi-chip modules and 3-D ICs
• Output formats: Verilog (IEEE 1364), VHDL (IEEE 1076), and STIL (IEEE 1450)
• Validation of JTAG design prior to tape-out
• Test on ATE for verification of JTAG implementation
© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
Verilog,VHDL STIL
SimulatorSemiconductor
ATE
BSDL, .ALLIEEE 1149.1IEEE 1149.6
TAPChecker™
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Outline
• Why implement JTAG in ICs in the first place?
• Why validate and verify JTAG implementations?
• Automating the validation of JTAG implementations
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![Page 9: GOEPEL Electronics TAP Checker](https://reader034.vdocuments.us/reader034/viewer/2022051412/549c006bac7959b52a8b45e1/html5/thumbnails/9.jpg)
© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
• Select the tests to include in the test bench
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© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
• Select input and output directories and files
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© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
• Adjust timing and test related settings as needed
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© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
• Select output formats and select various output options as needed
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© 2012 GOEPEL electronics JTAG/Boundary Scan
TAP Checker™
• Run the test bench generation
• Output file(s) are generated and stored in specified location
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© 2012 GOEPEL electronics JTAG/Boundary Scan
Summary
• JTAG/boundary scan features can provide huge benefits for device, board, and system test
• Requirement: IEEE 1149.x compliance
• JTAG implementations must be validated & verified
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© 2012 GOEPEL electronics JTAG/Boundary Scan
• For further information, please:• Visit our website at www.goepelusa.com
• Call us at 1-888-4GOEPEL
• Email us at [email protected]
Thank you for your attention
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