Global TriggerGlobal TriggerH. Bergauer, Ch. Deldicque, J. Erö, K. Kastner, S. Kostner, A. H. Bergauer, Ch. Deldicque, J. Erö, K. Kastner, S. Kostner, A.

Nentchev, Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer,

H. Sakulin, H. Sakulin, J. Strauss, A. Taurok, C.-E. WulzJ. Strauss, A. Taurok, C.-E. Wulz

Vienna GroupVienna Group

presented by

Claudia-Elisabeth WulzClaudia-Elisabeth WulzTrigger Meeting, CMS Week, CERN, 16 March 2004

C. - E. Wulz 2 Trigger Meeting, March 2004

Global Trigger Rack

A.Taurok 25. Feb 2004

Global Trigger

56U Rack

4 Tracker Emulators,..

other 6U_boards

(standard VME backplane)

GMT, GT, TCS

(non-standard backplane)

Conversion boards

(Fast signals,...)

(standard VME backplane)

2 S-links: DAQ,EVM

JTAG

PCI-VME link

16 DT,CSC,RPC muon cables

12 cables MIP/QUIET bits

7 cables Calo trigger data

+1 free cable trigger data

nn TOTEM trigger cables

32 TTC_data (L1A,cmd)

24 Subdetector STATUS cables

8 DAQ STATUS cables

1U=1.75“=44.45mm

56U racks, w=60cm,

depth=90cm, h=256cm

Ethernet

inside airflow

PCs outside Air Flow

Rack Layout according to CMS Standard

Rack: CMS-DISIR-IG-0002 v.2 (EDMS Id:

114226)

9kW cooling power

3 kW per crate

(=max. standard value)

8 PTC STATUS cables

8x2 Emulator cables

3U used for

16 Muon cables,

40 Status cables,

TOTEM cables

converted Status bits

Panel outside Air Flow

to get cables from bottom

1 U Heat Exchanger

2 U Fan Unit

9U/6U crate

1 U Heat Exchanger

2 U Fan Unit

9U crate

1 U Heat Exchanger

2 U Fan Unit

1 U Heat Exchanger

2 U Air Flow Guide

4 U Cross Flow Fan

with Monitoring Unit

EMULATOR -PC

GT -PC

9/6U crate

1 U panel

3U cable panel

8 Subdetector STATUS

cables to Emulators

C. - E. Wulz 3 Trigger Meeting, March 2004

All boards on front side.

Boards arranged for minimum cable length.

Global Trigger Crate

L1 GLOBAL TRIGGER 9U Crate

CLK,BCRES, L1A

8 FinOR

+8 TechTrig

A.T. 19.1.04

RUN

Control

4MUONS

VME

VME

VME

Top view

FRONT SIDE BACK SIDE

GTL9U

GTL9U

BACKPLANE

SIGNALS

2 S-links

DAQ, EVM

GTFE

TIM6UTTC

4TAU, ET*, JetNr, 4 free

ET*=total ET

, HT

,MET

Technical signals

4IEG, 4EG, 4JET, 4fJET

PSB9U

PSB9U

PSB9U

RO-data

12 ChLinks

slot not used

8 RPC, 4 DT

4 CSC muon

12 CABLES

MIP/QUIET

PSB9U

PSB9U

PSB9U

GMT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

FDL 9U128 Algo

APVE,

DAQ

Status

Signals

TCS 9U

SLOT_Nr

PSB9UTTIN

L1A_OUT

L1A_OUT

16 TTCvi

16 TTCvi

TTC racks

TTS racks

Conv

Crate

GCT crate

M/Q bits

GCT data

L1A, Bgo

32 cables to

32 TTCvi

C. - E. Wulz 4 Trigger Meeting, March 2004

VME INTERFACE

Infiniband connector

CLOCKL1A BCRES RESETJTAG

CHANNEL LINK

GTL+ signals

PSB9U board

4 x 32 bit channels+2 x 12 bits for GMT

DS92LV161.4Gbps Serial Link

RJ45

LVDS parallel è16 bits/40 MHz

VME160

386

ZPACK2mm

ZPACK2mm

POWER+1.5V/3A+2.5V/3A

LEDs

SYNCDERANDOMIZING BUFFERS

PhaseadjustmentDELAY

SPY/SIMDPM

RINGBUFFER

MUX

READOUT CIRCUITS

XC2V3000-4BF957

R/TR/T

RECREC

R/TR/T

RECREC

386

386

386

16 bits/80 MHz

PSB-9U Input Board

One PSB board is reserved for technical triggers. The preferred solution for input of technical triggers is via Ethernet connectors, with 4 LVDS signals per connector.Agreement with subsystems wanted!

C. - E. Wulz 5 Trigger Meeting, March 2004

Global Trigger Prototypes

PSBPSB

GTL6U

GTL_CONV

VMEinterface

Prototype GT Crate GTL6U + GTL_CONV

C. - E. Wulz 6 Trigger Meeting, March 2004

TTCrx

CLOCK circuits

LVDS driversCLK, BCRES, L1A, RESET

to each VME slot

VME

TIM-Chip

Front Panel

NEW: This board is tested. 2 modules are finished, and components are being put on the 3rd one. A new version compatible with the QPLL-TTCrx (TTCrq) is under development and expected in Feb. 2005. Same functions as old version, but will have new driver chips for clock signals on front panel. Both versions can be used by GT and DTTF.

TIM6U Timing Module

C. - E. Wulz 7 Trigger Meeting, March 2004

VME INTERFACE

IDC connectors

4(6) x 32 bits CLOCKL1A BCRES RESET

JTAG

CHANNEL LINK

LVDS signals

FDL9U board

8 Final_OR 8 Techn_OR

LVTTL40 MHz parallel

VME160

ZPACK2mm

ZPACK2mm

POWER+1.5V/3A+2.5V/3A

LEDs

STATUS bitsTechnical Trigger bits

CHANNEL LINKDAQ_recordEVM_record

128 ALGO bits32 Technical Trigger bits

FDL chip

XC2V2000-4BF957

DOWNSCALERS

RINGBUFFER

DERANDOMIZING BUFFERS

READOUT CIRCUITS

STATUS logic

Registers, masks

RATEcntrs

2x8FinalOR

NEW: The FDL9U is in the process of layout. The board is expected in June 2004.

FDL9U Final Decision Logic

C. - E. Wulz 8 Trigger Meeting, March 2004

TCS-9U Central Trigger Control Board

NEW: The TCS-9U board is available and components are being mounted. The end of tests is expected in May 2004. The VME interface works, the base address can be set by software.

C. - E. Wulz 9 Trigger Meeting, March 2004

40, 80 MHz CLK drivers

DS92LV16 receivers

Registers for 40 80 MHz conversion

Infiniband connectors

DS92LV16 transmitter for

tests

PSB_IN80 for PSB-6U

C. - E. Wulz 10 Trigger Meeting, March 2004

CONV6U

NEW: CONV6U boards, needed by the TCS9U board to receive the fast status signals, have been produced and will be soldered shortly.

CONV6U board

Channel Link DS90CR217MTD

VME96

POWER+3.3V/5A

386

RJ45 with LEDs

CLK

VME96

P1

P2

CLKCDC586PAHPLL 40/80 MHz

217

LVDS Receiver 75LVDT386

386

217

386

LED drivers74LVCH16245ADL245

245

+5V

Board contains only I/O chips and no VME interface

C. - E. Wulz 11 Trigger Meeting, March 2004

bottom sidetop side50 Ohm

connectorsXC2V2000-4FF896C

BGA: 1mm pitch, track width=83 m

Mezzanine Boards

MEZZ896 will be used in TCS-9U and GMT.

NEW: For MEZZ957 (for XCV3000 to be used in TCS-9U, GMT, GTFE, FDL9U)layout is finished. Final checks before production, boards expected in June 2004.

C. - E. Wulz 12 Trigger Meeting, March 2004

LA1OUT Boards

NEW: L1AOUT output boards are in production and expected by April 2004.

HR25-9R-16SC Hirose connector

L1AOUT boardLVDS drivers for 8 bit/cable

ZPACK2mm

ZPACK2mm

for 16 partitions

8bitsper partition:L1A, 4BGo, Strobe, CLK, ORBIT

+3.3V

387

387

387

387

387

387

387

DF11-8DS-2C connectorDF11-8DP-2DSA

387

C. - E. Wulz 13 Trigger Meeting, March 2004

• Custom Backplane for VME crate 6U Prototype: Channel Links ... exists MS 03/02 9U Backplane: 80MHz GTLp and Channel Links ... New: board tested MS 09/03

• PSB Input board (synchronisation, monitoring)

PSB 6U Prototype: Channel Link receivers ... board tested MS 03/02 PSB-IN80: DS92LV16 serial receivers ... board tested

– PSB 9U: memories inside FPGAs … New: working on FPGA logic MS 08/04 (updated)• GTL Logic board:

GTL_CONV Conversion board for prototype ... board tested MS 03/02 GTL6U prototype: 20 channels … New: board tested MS 06/03

• Signal transfer tested with test patterns -> ok … working on firmware

• XDAQ compatible test program in C++ exists

• Loading of conditions software developed

– GTL9U board: 32 channels ...conceptual design MS 11/04

• 4, 4 isol. e/, 4e/, 4 central jets, 4 fwd jets, 4 -jets, ET, ET mis, HT, 12 jet counts

Global Trigger Status and Milestones March 2004Global Trigger Status and Milestones March 2004

Boards

C. - E. Wulz 14 Trigger Meeting, March 2004

TIM6U Timing board with TTCrx ... 2 boards tested MS 06/03

(clock and L1A distribution, this version can be used by GT and DTTF)• TIM6U Timing board with TTCqx ... in progress MS 02/05 (new)

(also used by DTTF)

• MEZZ896 (used on TCS9U, GMT) ... boards available MS 04/04 (updated)

• MEZZ957 (used on TCS9U, GMT,FDL9U, GTFE) ... layout MS 04/04 (new)

• FDL9U Final Decision board ... layout MS 06/04 (updated)

• TCS9U Central Trigger Control board ... board produced, testing MS 05/04 (updated)• L1AOUT Module (needed by TCS9U) ... boards in production MS 04/04 (new)• CONV6U Status signals reception (needed by TCS9U) ... board produced MS 05/04 (new)• TTIN Input module for technical triggers … hopefully not needed!• GTFE9U Readout board ... conceptual design MS 10/04 (updated)

Integration test with GCT MS 06/03• Test of 20-channel GT system MS 06/04• Integration with GMT MS 01/05 • Test of full GT system MS 06/05• Integration of GMT with DT, CSC, RPC MS 06/05 • Start of integration with DAQ MS 01/06

Global Trigger Status and Milestones March 2004Global Trigger Status and Milestones March 2004

System and Integration

C. - E. Wulz 15 Trigger Meeting, March 2004

Review in Vienna and URL’s

A review of the Global Trigger (and the DTTF and GMT) will be performed on 19 April 2004.Information is available and can be accessed from a special web site:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/Review/review_welcome.htmlThe normal web site for the Global Trigger is:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTriggerThis talk may be found at:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/wulz_GT_mar2004.pdf