GHDL TutorialFrom http://mbmn.net/uer/tutorials/vhdl-with-ghdl/

Makefile# vhdl filesFILES = src/*VHDLEX = .vhd # testbenchTESTBENCHPATH = testbench/${TESTBENCH}$(VHDLEX) #GHDL CONFIGGHDL_CMD = ghdlGHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic SIMDIR = simulation# Simulation break condition#GHDL_SIM_OPT = --assert-level=errorGHDL_SIM_OPT = --stop-time=500ns WAVEFORM_VIEWER = gtkwave all: compile run view new :echo "Setting up project ${PROJECT}"mkdir src testbench simulation compile :ifeq ($(strip $(TESTBENCH)),)@echo "TESTBENCH not set. Use TESTBENCH=value to set it."@exit 2endif mkdir -p simulation$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCHPATH) $(FILES)$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCH)@mv $(TESTBENCH) simulation/$(TESTBENCH) run :@$(SIMDIR)/$(TESTBENCH) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(TESTBENCH).vcdgz view :gunzip --stdout $(SIMDIR)/$(TESTBENCH).vcdgz | $(WAVEFORM_VIEWER) --vcd clean :$(GHDL_CMD) --clean --workdir=simulation

Source: src/and_2.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity and_2 is port ( a, b : in std_logic; c : out std_logic );end entity;

architecture behav of and_2 is

begin c

Testbench: testbench/and_2_tb.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity and_2_tb isend entity;

architecture TB of and_2_tb is

component and_2 port( a, b: in std_logic; c : out std_logic); end component;

signal sa, sb, sc: std_logic;

begin

a : and_2 port map(a => sa, b => sb, c => sc);

sa

Usagemake TESTBENCH=and_2_tb