george mason university timing analysis ece 545 lecture 8a
TRANSCRIPT
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George Mason University
Timing Analysis
ECE 545Lecture 8a
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Required reading
• P. Chu, RTL Hardware Design using VHDL
Chapter 8.6 Timing Analysis of a Synchronous
Sequential Circuit
Chapter 16.1 Overview of a Clock Distribution
Network
Chapter 16.2 Timing Analysis with Clock Skew
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3ECE 448 – FPGA and ASIC Design with VHDL
Hold & Setup Time
Metastability
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Violation of Hold or Setup Time
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Response of a Flip-Flop to Timing Violation
There exists a third and unstable point of equilibrium
between the two stable states representing the binary states 0 and 1 respectively.
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Points of Equilibrium in Flip-Flops and Latches
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Patterns of Metastable Behavior
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Response to Timing Violation
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Impact on Downstream Circuitry
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10ECE 448 – FPGA and ASIC Design with VHDL
Clock Skew
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Clock Skew
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Clock Skew Map for a Cell Processor
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Incorrect Clock Tree Layout – Narrow Meander
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Optimized Clock Tree Layout – H Tree
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Clock Skew - Summary