Generating a Novel Sequence of Random

Variables Using a Power Optimized LFSR

A Major Project Report

submitted in partial fulfillment

for the award of the degree

Of

Bachelor of Engineering

In

Electronics & Telecommunication

By

Harshita Jaiswal

P.Gowtami

Ria Ghosh

to the

BHILAI INSTITUTE OF TECHNOLOGY, DURG

CHHATTISGARH SWAMI VIVEKANAND TECHNICAL

UNIVERSITY

June 2016

DECLARATION

We the undersigned solemnly declare that the report of the project work entitled “Generating a

Novel Sequence of Random Variables Using a Power Optimized LFSR” is based on our own

work carried out during the course of our study under the supervision of Mrs. Swati Agrawal.

We assert that the statements made and conclusions drawn are an outcome of the project work.

Harshita Jaiswal

(3012812036)

P.Gowtami

(3012812060)

Ria Ghosh

(3012812074)

CERTIFICATE

It is certified that the work contained in the report entitled “Generating a Novel Sequence of

Random Variables Using a Power Optimized LFSR” by Harshita Jaiswal (3012812036),

P. Gowtami (3012812060) and Ria Ghosh (3012812074) has been carried out under the

supervision of Mrs. Swati Agrawal and this work has been submitted for award of the degree of

Bachelor of Engineering in Electronics & Telecommunication.

Mr. Sourabh Yadav Mrs. Swati Agrawal

Project Incharge Supervisor

Associate Professor Associate Professor

Electronics and Telecommunication Electronics and Telecommunication

Bhilai Institute of Technology, Durg Bhilai Institute of Technology, Durg

Dr. (Mrs.) Manisha Sharma

Professor & Head of the Department

Electronics and Telecommunication

Bhilai Institute of Technology, Durg

CERTIFICATE BY THE EXAMINERS

The report entitled “Generating a Novel Sequence of Random Variables Using a Power

Optimized LFSR” submitted by Harshita Jaiswal (3012812036), P. Gowtami (3012812060)

and Ria Ghosh (3012812074) has been examined by the undersigned as a part of the

examination and is hereby recommended for the award of the degree of Bachelor of Engineering

in Electronics & Telecommunication to Chhattisgarh Swami Vivekanand Technical University.

Internal Examiner External Examiner

ACKNOWLEDGEMENT

In the first instance, we would like to express our deep and sincere gratitude to Dr. (Mrs.)

Manisha Sharma, Head of the Department, Electronics and Telecommunication Department,

BIT Durg for providing us necessary permission and creating an excellent facility in the

department to carry out our team project during B.E. (8th Semester).

We are indebted to Mrs. Swati Agrawal, Associate Professor, Faculty member of Electronics

and Telecommunication Department, BIT, Durg, for her continuous inspiration and effective

guidance in selecting and completion of the major project. We are also grateful to Mr. Saurabh

Yadav, Assistant professor, Faculty member of Electronics and Telecommunication department

for constantly motivating us during the entire project work.

We express our thankfulness towards the laboratory instructors and supporting staff of

Electronics and Telecommunication Department, BIT Durg for their constant help.

Last but not the least, we owe thanks to our classmates and family for providing necessary help

and fruitful tips during discussions.

Harshita Jaiswal

P. Gowtami

Ria Ghosh

Abstract

This project proposes the generation of a novel sequence of random variables using the X-ORed

output of a power optimized 5-bit Linear Feedback Shift Register (LFSR) and a 5-bit Counter.

With relevance with the recent essential VLSI technology requirements, the LFSR being used

will be power optimized using the Clock gating technique, which will significantly increases the

efficiency of the output. The reduction in power dissipation will also be verified through

hardware implementation on a FPGA kit. This power optimized LFSR and a 5-bit counter

individually give an output of pseudo-random variables, but if the output of the two are X-ORed

then the final output will be a totally unique random variable sequence which will further be used

for cryptographic applications like Data Encryption keys and Bank Security Communication

Channels.

Table of Contents

Chapter Title Page No.

List of Figures ix

List of Tables x

1 Introduction

1.1 Random Variables 1

1.1.1 Types of Random Variables 1

1.1.2 Methods of Generation 1

1.1.3 Need of Random Variables 2

1.1.4 Applications of Random Variables 2

1.1.5 Pseudo-Random Generators 2

1.2 VHDL Language 3

1.2.1 Fundamental VHDL Units 3

1.2.2 Library 4

1.2.3 Entity 4

1.2.4 Architecture 4

1.2.5 Pre-Defined Data types 5

2 Literature Review

Reports of various journals 6

2.1 Problem Identification 9

3 Methodology

3.1 Random Number Generator 11

3.1.1 True Random Generators 11

3.1.2 Pseudo-Random Generators 12

3.2 Linear Feedback Shift Register 13

3.2.1 Optimum Taps 14

3.2.2 Maximum Length 14

3.2.3 Lock-up States 16

3.2.4 Power Optimizing the LFSR 18

3.3 Counter Overview 19

3.3.1 Types of Counters 19

3.3.2 Synchronous Counters 20

3.4 Generating the Novel Random Sequence 22

3.4.1 Application of the novel sequence 23

3.4.2 Use in Science 24

3.4.3 Need in Simulation 24

3.4.4 Use in Cryptography 25

3.5 CPLD Hardware implementation 25

3.5.1 CPLD Features 26

3.5.2 CPLD Kit and Prototyping 26

4 Result and Performance Analysis

4.1 RTL Schematic and Test Bench Simulation 28

4.1.1 D-ff 29

4.1.2 X-Nor 30

4.1.3 Clock-gated D-ff 31

4.1.4 Clock-Gated internal LFSR 32

4.1.5 5-bit Counter 33

4.1.5 X-ored LFSR and Counter 34

4.2 Performance Analysis 35

Conclusion and Further Work

References

List of Figures

Fig 3.1 5 bit external LFSR 13

Fig 3.2 4 bit internal LFSR 14

Fig 3.3 3-bit LFSR 16

Fig: 3.4 4-Bit Synchronous Up-Counter 21

Fig 3.5 Block Diagram of Proposed Idea 23

Fig.3.6 CPLD Hardware Implementation 27

Fig 4.1 RTL of D-ff 29

Fig 4.2 Test-bench of D-ff 29

Fig 4.3 RTL of X-NOR 30

Fig 4.4 Test-Bench of X-nor gate 30

Fig 4.5 RTL of Clock-gated D-ff 31

Fig 4.6 Test Bench output of Clock-gated D-ff 31

Fig 4.7 RTL of Internal Clock-gated LFSR 32

Fig 4.8 Test bench of Internal Clock-gated LFSR 32

Fig 4.9 RTL of 5-bit Counter 33

Fig 4.10 Test Bench of 5-bit Counter 33

Fig 4.11 RTL of X-ored LFSR and Counter 34

Fig 4.12 Test Bench of X-ored LFSR and Counter 34

List of Tables

Table 3.1 5 bit LFSR sequence 15

Table 3.2 3 bit LFSR sequence with XOR feedback taps 17

Table 3.3 3 bit LFSR sequence with XNOR feedback tap 17

Table 3.4 Output States of 5-bit Counter 22

1

1.1 Random Variables

A random variable is a variable whose value is unknown or a function that assigns values to

each of an experiment's outcomes. Random variables are often designated by letters and can

be classified as discrete, which are variables that have specific values, or continuous, which

are variables that can have any values within a continuous range.

A random variable's possible values might represent the possible outcomes of a yet-to-be-

performed experiment, or the possible outcomes of a past experiment whose already-existing

value is uncertain (for example, due to imprecise measurements or quantum uncertainty).

They may also conceptually represent either the results of an "objectively" random process

(such as rolling a die) or the "subjective" randomness that results from incomplete

knowledge of a quantity.

The meaning of the probabilities assigned to the potential values of a random variable is not

part of probability theory itself but is instead related to philosophical arguments over the

interpretation of probability. The mathematics works the same regardless of the particular

interpretation.

1.1.1 Types of Random Variables

Random variables can be Discrete, that is, taking any of a specified finite or countable list of

values, endowed with a probability mass function, characteristic of a probability

distribution; or Continuous, taking any numerical value in an interval or collection of

intervals, via a probability density function that is characteristic of a probability distribution;

or a mixture of both types. The realizations of a random variable, that is, the results of

randomly choosing values according to the variable's probability distribution function, are

called random variates.

1.1.2 Methods of Generating Random Variables

Up till date all of the famous random variate generation/sampling techniques are derived

from combinations of the following six fundamental methods:

1. Physical Sources

2. Empirical Resampling

3. Pseudo-random Generators

2

4. Simulation/Game Play

5. Rejection Sampling

6. Transform Methods

1.1.3 Need of Random Variables in Engineering

An adequate understanding of uncertainties in an engineering task requires a number of

actions, among them reflection about the choice of model and failure mechanisms;

accessing the variability of the inputs and outputs variables and model parameters;

sensitivity analysis or accessing the reliability of a structure. Randomness of anything

determines the probable extent to which the thing can be implemented. It gives new

scopes for research and development and better possibilities to the society. Hence both

logically and practically random variables play a very essential role in generating newer

opportunities.

1.1.4 Applications of Random Variables

Random variables form the base of almost every mathematical calculation required in

engineering. Right from generating wave signals in communication to checking the

probability of resistance of a building against earthquake all require random trails to get

to the accurate results. Random variables in communication, gives us the probable

periodic repetition of signals and error due to noise disturbances in the form of waves and

probability distribution charts. Random variables have an extremely essential role in

Cryptography and secure communication where they are used in generation of jamming

and anti-jamming codes and keys for protection purposes. In medical science, random

variables are used to find out extensive gene sequences and solution to medicinal

problems.

1.1.5 Pseudo-Random Generators

The technique best suited to generate random variables through practical point of view is

with the help of Pseudo-random generators. In this project a novel sequence of random

variables will be generated using the combination of a linear Feedback Shift Register and

a Counter, both of which give pseudo-random sequences as an output. The entire

generation will be through VHDL coding which will be further explained.

3

1.2 VHDL Language

VHDL (Very Large Scale Integrated Circuits Hardware Description Language) is a

hardware description language used in electronic design automation to describe digital and

mixed-signal systems such as field-programmable gate arrays and integrated

circuits. VHDL can also be used as a general purpose parallel programming language.

The key advantage of VHDL, when used for systems design, is that it allows the behavior of

the required system to be described (modeled) and verified (simulated) before synthesis

tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system. VHDL is

a dataflow language, unlike procedural computing languages such as BASIC, C, and

assembly code, which all run sequentially, one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in

many other projects. However, many formational and functional block parameters can be

tuned (capacity parameters, memory size, element base, block composition and

interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project

can be ported on another element base, for example VLSI with various technologies.

VHDL is commonly used to write text models that describe a logic circuit. Such a model is

processed by a synthesis program, only if it is part of the logic design. A simulation program

is used to test the logic design using simulation models to represent the logic circuits that

interface to the design. This collection of simulation models is commonly called a testbench.

1.2.1 Fundamental VHDL units

A standard piece of VHDL code is composed of at least three fundamental sections:

LIBRARY declaration: Contains a list of all libraries to be used in the design. For e.g.- ieee,

std, etc.

ENTITY: Specifies the I/O pins of the circuit.

ARCHITECTURE: Contains the VHDL code proper, which describes how the circuit

should behave.

4

1.2.2 Library

A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside

the library allow them to be reused or shared by other designs. The code is usually written in

the form of functions, procedures or components which are placed inside packages and

then complied into the destination library.

Library declarations:

To declare a LIBRARY (i.e. to make it visible to design) two lines of code are needed, one

containing the name of the library and the other a use clause, as shown in the syntax below-

LIBRARY library_name;

USE library_name.pakage_parts;

1.2.3 Entity

Entity can be seen as the black box view of the system. We define the inputs and outputs of

the system which we need to interface.

Entity ANDGATE is

Port (A: in std_logic;

B: in std_logic;

Y: out std_logic);

End entity ANDGATE;

Entity name ANDGATE is given by the programmer, each entity must have a name.

1.2.4 Architecture

Architecture defines what is in our black box that we described using ENTITY. We can use

either behavioral or structural models to describe our system in the architecture. In

Architecture we will have interconnections, processes, components, etc.

Architecture AND1 of ANDGATE is

--declarations

Begin

--statements

Y <= A AND B;

End architecture AND1;

5

Entity name or architecture name is user defined. Identifiers can have uppercase

alphabets, lowercase alphabets, and numbers and underscore (_).First letter of identifier

must be an alphabet and identifier cannot end with an underscore. In VHDL, keywords

and user identifiers are case insensitive. VHDL is strongly typed language i.e. every

object must be declared.

1.2.5 Pre-Defined Data types

VHDL provide a whole number of predefined types declared and gathered in the so

called packages. The package standard contain the most important base types, the

package textio contains important predefined types for text input and output. Both

packages standard and textio must be available in any VHDL implementation.

-- predefined in package 'standard':

TYPE boolean IS (false, true);

TYPE bit IS ('0', '1');

TYPE character IS (... die ASCII-Zeichen ...)

TYPE severity_level IS (note, warning, error, failure);

-- predefined in package 'textio'

Also the predefined type character is an enumeration type that contains all ASCII characters.

The two characters '0' and '1' belong to both the type character, as well as to type bit. In case

that both characters '0' or '1' appear, the VHDL compiler must always determine according

the context which type to use.

Packages std_logic_signed and sta_logic_unsigned of library ieee; contain functions that

allow operations with STS_LOGIC_VECTOR data to be performed as if the data were of

type SIGNED or UNSIGNED.

6

Shatadal Mishra & et.al (2010) presented a thesis regarding the FPGA based random

number generator for cryptographic applications in which the random variables are generated

through VHDL programming. Random numbers are generated by various methods. The two

types of generators used for random number generation are pseudo random number generator

(PRNG) and true random number generator (TRNG). The numbers generated are random

because no polynomial – time algorithm can describe the relation amongst the different

numbers of the sequence. Numbers generated by true random number generator (TRNG) or

cryptographically secure pseudo random number generator (CSPRNG). The sources of

randomness in TRNG are physical phenomena like lightning, radioactive decay, thermal noise

etc. The source of randomness in CSPRNG is the algorithm on which it is based. In this

project, the random numbers generated for cryptographic applications were generated by

using the Blum Blum Shub generator, the CSPRBG. It was implemented on a FPGA platform

using VHDL programming language and the simulation was done and tested on the Xilinx

ISE 10.1i. [1]

Sruti Hathwali & et.al presented a research article in the Int. Journal of Engineering

Research and Applications which explained the proposed design of

Linear Feedback Shift Register which generates pseudo-random test patterns as the input bit

is a linear function of its previous state. The total number of random state generated on LFSR

depends on the feedback polynomial. As it is simple counter so it can count maximum of 2n -

1 by using maximum feedback polynomial.

The main challenging areas in VLSI are performance, cost, testing, area, reliability and

power. The demand for portable computing devices and communications system are

increasing rapidly. These applications require low power dissipation for VLSI circuits. The

power dissipation during the test mode is 200% more than in normal mode. Hence it is

important aspect to optimize power during testing. Power optimization is one of the main

challenges. Linear feedback shift registers have multiple uses in digital systems design.

Here they have implemented a 32 bit length sequence on FPGA using VHDL with maximum

length feedback polynomial to understand the memory utilization and speed requirement.

Also, they have presented the comparison of performance analysis based on synthesis and

simulation result as well identify the simulation problem for long bit LFSR.

7

Understanding and analyzing the results given in the research, we designed our own efficient

model of the LFSR. [2]

Laung-Terng Wang & et.al in the year 2011,in a technical report on Designing Transformed

Linear Feedback Shift Registers with Minimum Hardware Cost provides a proof that given a

standard or modular linear feedback shift register(LFSR) that uses k 2-input XOR gates to

generate pseudorandom sequences, any transformed LFSR (t-LFSR) implementing the same

characteristic polynomial, f(x), as the standard or modular LFSR cannot use fewer than

log2(k+1) 2-input XOR gates when k is an odd number, or 1+log2k 2-input XOR gates when

k is an even number. This property applies to any n stage t-LFSR design regardless of whether

f(x) is a primitive polynomial or not. A new class of minimum-cost LFSRs (min-LFSRs) is

subsequently developed to reduce the hardware cost to a minimum.

This conclusion, helped us to rectify the block diagram and circuit design of the LFSR,

reducing the cost and enhance the efficiency of our model. [3]

P.V. Dibal & et.al in August 2013, in a journal titled Design and Implementation of Mod-6

synchronous Counter using VHDL explained the design structure of a counter and how to

implement the coding. Their paper deals with the design of a MOD-6 synchronous counter

using VHDL (VHSIC Hardware Description Language). The VHSIC stands for Very High

Speed Integrated Circuit. Using this approach, the behaviour of the counter is the most

important aspect of the design. In the first section, the paper introduced counters in general,

and their areas of specialization, like frequency synthesizers. The synchronous counter was

then introduced, stating the behaviour of the flip-flops that make the counter.

In almost all digital systems, counters are extensively used in areas such as frequency

synthesizers, analog-to-digital converters and circuits used in communication systems. A

synchronous counter in particular, is the counter type in which all the flip-flops in the counter

change their state in synchronism with the input clock signal (Anil, 2007). The clock signal in

a synchronous counter is simultaneously applied to all the clock input of the flip-flops. [4]

2.1 Methods of Power Reduction and Speed Augmentation

Vikas Sahu and Mr. Pradeep Kumar in their publication in the International Journal of

Computer Trends and Technology (IJCTT) - volume4Issue4 –April 2013, compared different

types of LFSR on the basis of performance parameter such as power consumption,

8

propagation delay and leakage current at 65nm, 45 nm, 32 nm and 25nm technologies for high

performance LFSR design. In many electronics circuit Linear Feedback Shift Register (LFSR)

used for generating sequences. So for high performance applications LFSR should have to

generate efficient sequences. There are so many methods of generating very efficient

sequences. The demand and popularity of portable LFSR is driving designers to strive for

small silicon area, higher speeds, low power dissipation and reliability. Compared to static

LFSR, dynamic LFSR offers good performance. Wide fan-in logic such as domino LFSR is

used in high-performance applications. Dynamic domino LFSRs are widely used in modern

digital VLSI circuits. These dynamic LFSRs are often favored in high performance designs

because of the speed advantage offered over static LFSR circuits. [5]

2.1.1 Using Reversible Logic

Kavya Shree C &et.al in 2012, emphasized on the issue that reversible logic has emerged as

one of the most important approaches for the optimization of power in low power VLSI

design. They are also the basic requirement for the emerging field of the Quantum computing

having their applications in the areas such as Digital Signal Processing, Nano-Technology,

Cryptrography etc. It means performing computation in such a way that any previous state of

the computation can always be reconstructed with given description of the current state. Here

Reversible logic is used for designing a Linear Feedback Shift Register (LFSR).

C. H. Bennett in 1973 discovered that the power dissipation in any device can be made zero

or negligible if the computation is done using reversible model.

During any computation the intermediate bits used to compute the final result are lost; this

loss of bits is one of the main reason for the power dissipation. [6]

2.1.2 Increasing the correlativity between the successive vectors

A low power Test Pattern Generator (TPG) designed by modifying Linear Feedback Shift

Register is proposed to produce low power test vectors that are deployed on Circuit under

Test (CUT) to slenderize the dynamic power consumption by CUT. The technique involved in

generating low power test patterns is performed by increasing the correlativity between the

successive vectors; the ambiguity in increasing the similarity between consecutive vectors is

resolved by reducing the number of bit flips between successive test patterns. Upon deploying

9

the low power test patterns at the inputs of CUT, slenderizes the switching activities inside

CUT that in turn reduces its dynamic power consumption. The resulted low power test vectors

are deployed on CUT to obtain fault coverage. The experimental results demonstrate

significant power reduction by low power TPG than compared to standard LFSR.

2.1.3 Clock Gating Method

Wikipedia defines Clock gating as a popular technique used in many synchronous circuits for

reducing dynamic power dissipation. Clock gating saves power by adding more logic to a

circuit to prune the clock tree. Pruning the clock disables portions of the circuitry so that

the flip-flops in them do not have to switch states. Switching states consumes power. When

not being switched, the switching power consumption goes to zero, and only leakage

currents are incurred.

Clock gating works by taking the enable conditions attached to registers, and uses them to

gate the clocks. Therefore it is imperative that a design must contain these enable conditions

in order to use and benefit from clock gating. This clock gating process can also save

significant die area as well as power, since it removes large numbers of muxes and replaces

them with clock gating logic. This clock gating logic is generally in the form of "Integrated

clock gating" (ICG) cells. However, note that the clock gating logic will change the clock tree

structure, since the clock gating logic will sit in the clock tree.

Clock gating logic can be added into a design in a variety of ways:

1. Coded into the RTL code as enable conditions that can be automatically translated into

clock gating logic by synthesis tools (fine grain clock gating).

2. Inserted into the design manually by the RTL designers (typically as module level clock

gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks

of specific modules or registers.

3. Semi-automatically inserted into the RTL by automated clock gating tools. These tools

either insert ICG cells into the RTL, or add enable conditions into the RTL code. These

typically also offer sequential clock gating optimizations. [7]

10

2.2 Problem Identification

The papers presented above describe how to generate pseudo-random variables using pseudo-

random generators in VHDL programming. But in the above methods the randomness is quite

and hence periodic series can be detected easily that too not in a very efficient manner. Our

task is to generate a completely novel sequence of random variables, with much more

increased randomness, which will be difficult to decode. Our approach in this project is to

create a better sequence of random variables, improved from the usual pseudo-random

variable generators which are unable to provide randomness to better efficiencies. Combining

two types of pseudo-generators is our main idea of the thesis, so as to give better randomness

rather than very giving randomness only up to 32 to 64 states. Power optimizing the pseudo-

random generators is also an integral part of our project, so as to ensure better results.

Changing the design components will also be on our experiment list, as that would ensure

maximum results with minimum hardware.

11

3.1 Random Number Generation

A random number generator (RNG) is a device designed to generate a sequence of numbers or

symbols that don‘t have any pattern. Hardware-based systems for random number generation are

widely used, but often fall short of this goal, albeit they may meet some of the statistical tests for

randomness for ensuring that they do not have any ―de-cod able‖ patterns. Methods for

generating random results have existed since ancient times, including dice, coin flipping, the

shuffling of playing cards, the use of yarrow stalks and many other techniques.

The many applications of randomness have led to many different methods for generating

random data. These methods may vary as to how unpredictable or random they are, and how

quickly they can generate random numbers.

3.1.1 True Random Number Generators (TRNGs):

There are two principal methods used to generate random numbers. One measures some physical

phenomenon that is expected to be random and then compensates for possible biases in the

measurement process. The other uses mathematical algorithms that produce long sequences of

apparently random numbers, which are in fact completely determined by an initial value, known

as a seed. The former one is known as True Random Number Generator (TRNG).

In comparison with PRNGs, TRNGs extract randomness from physical phenomena and

introduce it into a computer. One can imagine this as a die connected to a computer. The

physical phenomenon can be very simple, like the little variations in mouse movements or in the

amount of time between keystrokes. In practice, however, one has to be careful about which

source one chooses. For example, it can be tricky to use keystrokes in this fashion, because

keystrokes are often buffered by the computer's operating system, meaning that several

keystrokes are collected before they are sent to the program. To a program waiting for the

keystrokes, it will seem as though the keys were pressed almost simultaneously, and there may

not be a lot of randomness there after all.

However, there are many other methods to get true randomness into your computer. A really

good physical phenomenon to use is a radioactive source. The points in time at which a

radioactive source decays are completely unpredictable, and they can easily be detected and fed

into a computer, avoiding any buffering mechanisms in the operating system. The HotBits

service at Fourmilab in Switzerland is an excellent example of a random number generator that

12

uses this technique. Another suitable physical phenomenon is atmospheric noise, which is quite

easy to pick up with a normal radio.

The fan from the computer can contribute to the noise, and since the fan is a rotating device,

chances are the noise it produces won't be as random as atmospheric noise. Undoubtedly one of

the effective approaches was the lavarand generator, which was built by Silicon Graphics and

used snapshots of lava lamps to generate true random numbers.

3.1.2 Pseudo Random Number Generators (PRNGs):

A pseudorandom number generator (PRNG), is an algorithm for generating a sequence of

numbers that approximates the properties of random numbers. The sequence is not truly random.

Although sequences that are closer to truly random can be generated using hardware random

number generators, pseudorandom numbers are important in practice for simulations (e.g., of

physical systems with the Monte Carlo method), and are important in the practice of

cryptography.

A PRNG can be started from an arbitrary starting state using a seed s. It will always produce the

same sequence thereafter when initialized with that state. The maximum length of the sequence

before it begins to repeat is determined by the size of the state. However, since the length of the

maximum period doubles with each bit of 'state' added, it is easy to build PRNGs with periods

long enough for many practical applications. Most pseudorandom generator algorithms produce

sequences which are uniformly distributed by any of several tests.

The security of most cryptographic algorithms and protocols using PRNGs is based on the

assumption that it is infeasible to demarcate use of a suitable PRNG from the usage of a truly

random sequence. The simplest examples of this dependency are stream ciphers, which work by

exclusive or-ing the plaintext of a message with the output of a PRNG, producing cipher text.

The design of cryptographically secure PRNGs is extremely difficult; because they must meet

additional criteria .The size of its period is an important factor in the cryptographic suitability of

a PRNG, but not the only one. The following algorithms are pseudorandom number generators:

Blum Blum Shub

Inversive congruential generator

ISAAC (cipher)

Lagged Fibonacci generator

13

Linear congruential generator

Linear feedback shift register

Multiply-with-carry

Well Equidistributed Long-period Linear

Xorshift

Cipher algorithms and cryptographic hashes can also be used as pseudorandom number

generators. These include:

Block ciphers in counter mode

Cryptographic hash function in counter mode

Stream Ciphers

3.2 Linear Feedback Shift Register as a Pseudo-Random Sequence Generator

Feedback around an LFSR's shift register comes from a selection of points (taps) in the register

chain and constitutes XORing or X-NORing these taps to provide tap(s) back into the register.

Register bits that do not need an input tap, operate as a standard shift register. It is this feedback

that causes the register to loop through repetitive sequences of pseudo-random value. The choice

of taps determines how many values there are in a given sequence before the sequence repeats.

The implemented LFSR uses a one-to-many structure, rather than a many-to-one structure, since

this structure always has the shortest clock-to-clock delay path.A diagram of a five bit external

LFSR is as follows:

Fig 3.1: 5 bit external LFSR

14

In similar manner the internal feedback LFSR can be designed in the following diagram-

Fig 3.2: 4 bit internal LFSR

3.2.1 Optimum Tap Points

The choice of which taps to use determines how many values are included in a sequence of

pseudo-random values before the sequence is repeated. Certain tap settings yield the maximal

length sequences of (2N-1).

The external feedback LFSR as per Fig 3.1 has taps at stages 1 and 4 with XOR feedback. Note

also that the LS bit of the shift register is, by convention, shown at the left hand side of the shift

register, with the output being taken from the MS bit at the right hand side.

The LFSR output will produce a pseudorandom sequence of length 2n-1 states (where n is the

number of stages) if the LFSR is of maximal length. The sequence will then repeat from the

initial state for as long as the LFSR is clocked.

Assume that the example LFSR above is set to 1FH after initialization. The output of the

feedback XOR gate will be 0 (since 1 XOR 1 = 0) and the first clock edge will load 0 into stage

0.

3.2.2 Maximum Length

An LFSR is of 'maximal' length when the sequence generated passes all possible 2n-1 values.

Only certain combinations of taps will produce a maximal length LFSR. There can be more than

one combination of taps that give maximal length for each LFSR. If the taps on the 3-bit LFSR

are changed to stages 1 and 2, a maximal length shift register will still be produced, but with a

different sequence. The LFSR sequence depends on the seed value, the tap positions and the

feedback type. There is no easy way to decide where the taps should be for maximal length.The

following table shows the sequence:

15

Table 3.1: 5-bit LFSR pseudo-random sequence

LFSR stage Hex value

0 1 2 3 4 (0:4)

1 1 1 1 1 1F

0 1 1 1 1 0F

0 0 1 1 1 07

1 0 0 1 1 13

1 1 0 0 1 19

0 1 1 0 0 0C

1 0 1 1 0 16

0 1 0 1 1 0B

0 0 1 0 1 05

1 0 0 1 0 12

0 1 0 0 1 09

0 0 1 0 0 04

0 0 0 1 0 02

0 0 0 0 1 01

1 0 0 0 0 10

0 1 0 0 0 08

1 0 1 0 0 14

0 1 0 1 0 0A

1 0 1 0 1 15

1 1 0 1 0 1A

1 1 1 0 1 1D

0 1 1 1 0 0E

1 0 1 1 1 17

1 1 0 1 1 1B

0 1 1 0 1 0D

0 0 1 1 0 06

0 0 0 1 1 03

1 0 0 0 1 11

1 1 0 0 0 18

1 1 1 0 0 1C

1 1 1 1 0 1E

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3.2.3 Lock-up States

The one state that the 5-bit LFSR doesn't pass through is 00H. If the LFSR contained 00H, then

the feedback would also be 0 (since 0 XOR 0 = 0) and the LFSR would never leave the 00H state

i.e. it would be 'locked-up'. This is very important since in some FPGAs, the internal d-type flip-

flops clear to 0 on power-up or when the global reset net is activated. To avoid this problem, the

XOR feedback gate should be changed to an XNOR feedback (since 0 XNOR 0 = 1). Some

FPGAs (e.g. Xilinx) allow the individual flip-flops to be either set or reset on power-up or

initialization and the problem can be avoided by providing a non-zero initial value (sometimes

called the 'seed value').

If the feedback had been of XNOR type, then the lock-up state would be 1FH (since 1 XNOR 1 =

1). The designer should verify the power-on and/or global initialization state of the flip-flops in

the target device then choose XOR or XNOR feedback or provide a seed value which is neither

all zeroes or all ones. Note also that the sequence produced will be different for the two types of

feedback. The tables below show the sequences of a 3-bit, maximal length LFSR (taps at stage0

and stage2) with seed value 001 for both XOR and XNOR feedback:

Fig 3.3: 3-bit LFSR

There can be more than one maximum-length tap sequence for a given LFSR length. Also, once

one maximum-length tap sequence has been found, another automatically follows. If the tap

sequence, in an n-bit LFSR, is [n, A, B, C, 0], where the 0 corresponds to the x0 = 1 term, then the

corresponding 'mirror' sequence is [n, n − C, n − B, n − A, 0]. So the tap sequence [32, 7, 3, 2, 0]

has as its counterpart [32, 30, 29, 25, 0]. Both give a maximum-length sequence.

17

Table 3.2 : 3 bit LFSR sequence with XOR feedback taps 0, 2 : lock-up state = 0

Table 3.3 : 3 bit LFSR sequence with XNOR feedback taps 0,2 : lock-up state = 7

There is a way however, with the addition of extra logic, to force an LFSR into the lock-up state

and then out again, so cycling through all 2n states:

1. Detect the state in which the MS stage is 1 and all other stages are 0. Generate an active high

(logic 1) signal, 'force_lock' when this condition occurs.

LFSR stage

0 1 2 Value

0 0 1 1

1 0 0 4

1 1 0 6

1 1 1 7

0 1 1 3

1 0 1 5

0 1 0 2

LFSR stage

0 1 2 Value

0 0 1 1

0 0 0 0

1 0 0 4

0 1 0 2

1 0 1 5

1 1 0 6

0 1 1 3

18

2. 'XOR' this signal with the other taps used to produce the feedback. This will cause the

feedback signal to be logic 0. On the next clock edge, the LFSR will enter the all zeroes state

(lock-up).

3. Since all stages are at logic 0, the 'force lock' signal is still at logic 1, so the feedback signal

will still be at logic 1. Therefore on the next clock edge, the LFSR will enter the state where

the LS stage is logic 1 and all other stages are logic 0.

4. The LFSR will then continue with its sequence as normal.

3.2.4 Power Optimizing the LFSR

The best way of optimizing the LFSR through coding is through Clock-gating method. Clock

gating is a popular technique used in many synchronous circuits for reducing dynamic power

dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree.

Pruning the clock disables portions of the circuitry so that the flip-flopsin them do not have to

switch states. Switching states consumes power. When not being switched, the switching power

consumption goes to zero, and only leakage currents are incurred.[1]

Clock gating works by taking the enable conditions attached to registers, and uses them to gate

the clocks. Therefore it is imperative that a design must contain these enable conditions in order

to use and benefit from clock gating. This clock gating process can also save significant die area

as well as power, since it removes large numbers of muxes and replaces them with clock gating

logic. This clock gating logic is generally in the form of "Integrated clock gating" (ICG) cells.

However, note that the clock gating logic will change the clock tree structure, since the clock

gating logic will sit in the clock tree.

Clock gating logic can be added into a design in a variety of ways:

1. Coded into the RTL code as enable conditions that can be automatically translated into

clock gating logic by synthesis tools (fine grain clock gating).

2. Inserted into the design manually by the RTL designers (typically as module level clock

gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks of

specific modules or registers.

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3. Semi-automatically inserted into the RTL by automated clock gating tools. These tools

either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically

also offer sequential clock gating optimizations.

Clock gated circuit reduced the power consumption by almost 30%, which will be shown later in

the form of screen shots. Power optimization enhances the performance of the overall circuit

which is very important for any VLSI circuit.

3.3 Counter Overview

In digital logic and computing, a counter is a device which stores (and sometimes displays) the

number of times a particular event or process has occurred, often in relationship to a clock signal.

The most common type is a sequential digital logic circuit with an input line called the "clock"

and multiple output lines. The values on the output lines represent a number in

the binary or BCD number system. Each pulse applied to the clock

input increments or decrements the number in the counter. A counter circuit is usually

constructed of a number of flip-flops connected in cascade. Counters are a very widely-used

component in digital circuits, and are manufactured as separate integrated circuits and also

incorporated as parts of larger integrated circuits.

3.3.1 Types of Counters

In electronics, counters can be implemented quite easily using register-type circuits such as

the flip-flop, and a wide variety of classifications exist:

Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state

flip-flops

Synchronous counter – all state bits change under control of a single clock

Decade counter – counts through ten states per stage

Up/down counter – counts both up and down, under command of a control input

Ring counter – formed by a shift register with feedback connection in a ring

Johnson counter – a twisted ring counter

Cascaded counter

modulus counter.

20

Each is useful for different applications. Usually, counter circuits are digital in nature, and count

in natural binary. Many types of counter circuits are available as digital building blocks, for

example a number of chips in the 4000 series implement different counters.

Occasionally there are advantages to using a counting sequence other than the natural binary

sequence—such as the binary coded decimal counter, a linear feedback shift register counter, or

a Gray-code counter.

Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.

3.3.2 Synchronous Counters

n synchronous counters, the clock inputs of all the flip-flops are connected together and are

triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).

The circuit below is a 4-bit synchronous counter. The J and K inputs of FF0 are connected to

HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2

are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. A simple

way of implementing the logic for each bit of an ascending counter (which is what is depicted in

the image to the right) is for each bit to toggle when all of the less significant bits are at a logic

high state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and

bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.

Synchronous counters can also be implemented with hardware finite-state machines, which are

more complex but allow for smoother, more stable transitions.

Hardware-based counters are of this type. A simple way of implementing the logic for each bit of

an ascending counter (which is what is depicted in the image to the right) is for each bit to toggle

when all of the less significant bits are at a logic high state.

With a synchronous counter (or any synchronous system for that matter), the inputs have time to

stabilize before they affect the outputs. This precludes race-around situations, transient output

states (think ripple-carry counter), and errant output states. The disadvantage is that a clock

circuit has to be included in order to gate the logic (advance the logic to the next state).

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3.3.3 Synchronous up Counter

Fig 3.4: 4-Bit Synchronous Up Counter

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each

of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in

toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic

“1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a

predetermined sequence of states in response to the common clock signal, advancing one state

for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but

the Jand K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also

supplied with signals from the input and output of the previous stage. These

additional AND gates generate the required logic for the JK inputs of the next stage.

If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs

(Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but

without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same

time.

Then as there is no inherent propagation delay in synchronous counters, because all the counter

stages are triggered in parallel at the same time, the maximum operating frequency of this type of

frequency counter is much higher than that for a similar asynchronous counter circuit.

22

Table 3.4: Output of a 5-Bit Synchronous UP- Counter

PRESENT STATE NEXT STATE(Hex Data)

00H 01H

01H 02H

02H 03H

03H 04H

04H 05H

05H 06H

06H 07H

07H 08H

08H 09H

09H 0AH

0AH 0BH

0BH 0CH

0CH 0DH

0DH 0EH

0EH 0FH

0FH 10H

10H 11H

11H 12H

12H 13H

13H 14H

14H 15H

15H 16H

16H 17H

17H 18H

18H 19H

19H 1AH

1AH 1BH

1BH 1CH

1CH 1DH

1DH 1EH

1EH 1FH

1FH 00H

3.4 Generating the Novel Random Sequence

The output of the linear feedback shift register is in general pseudo-random in nature and can

vary maximum up to 2N-1 states. Also the counter that has to be designed will have the same

number of bits as output as the LFSR. Planning to generate a better and more random sequence

led us to apply an X-OR between each bit of the output of the LFSR and Counter.

23

The output states of the Linear feedback shift register and counter are different from each other,

which mean when the output of the two will be X-ORed there will be numerous random

variables before the actual repetition of the variables start. The randomness of the variables is

more than the LFSR output individually. The designs implemented through VHDL coding,

clearly shows the difference between the randomness of the X-ored LFSR and the normally

Clock-gated LFSR. Hence basically through our project we have found out a method to increase

the randomness of the sequence generated by a LFSR.

Novel Random Variable Sequence

Fig 3.5: Block Diagram of the proposed Idea

3.4.1 Applications of the Novel Sequence Generated

Random variables have many uses in science, art, statistics, cryptography, gaming, gambling,

and other fields. For example, random assignment in randomized controlled trials helps scientists

to test hypotheses, and random numbers or pseudorandom numbers help video games such as

video poker.

These uses have different levels of requirements, which leads to the use of different methods.

Mathematically, there are distinctions between randomization, pseudorandomization, and

quasirandomization, as well as between random number generators and pseudorandom number

generators. For example, applications in cryptography usually have strict requirements, whereas

other uses (such as generating a "quote of the day") can use a looser standard of

pseudorandomness. Many ancient cultures saw natural events as signs from the gods; many

attempted to discover the intentions of the gods through various sorts of divination. The

underlying theory was that the condition of, say, a chicken's liver, was connected with, perhaps,

5-Bit Synchronous

UP Counter

X-NOR

24

the dangerous storms or military or political fortune. Divination is still practiced and on much the

same basis as formerly.

3.4.2 Use in Science

Random numbers have uses in physics such as electronic noise studies, engineering, and

operations research. Many methods of statistical analysis, such as the bootstrap method, require

random numbers. Monte Carlo methods in physics and computer science require random

numbers.

Random numbers are often used in parapsychology as a test of precognition. Statistical practice

is based on statistical theory which is, itself, founded on the concept of randomness. Many

elements of statistical practice depend on randomness via random numbers. Where those random

numbers fail to be actually random, any subsequent statistical analysis may suffer from

systematic bias.

3.4.3 Need in Simulation

In many scientific and engineering fields, computer simulations of real phenomena are

commonly used. When the real phenomena are affected by unpredictable processes, such as

radio noise or day-to-day weather, these processes can be simulated using random or pseudo-

random numbers.

Automatic random number generators were first constructed to carry out computer simulation of

physical phenomena, notably simulation of neutron transport in nuclear fission.

Pseudo-random numbers are frequently used in simulation of statistical events, a very simple

example being the outcome of tossing a coin. More complicated situations are simulation of

population genetics, or the behaviour of sub-atomic particles. Such simulation methods, often

called stochastic methods, have many applications in computer simulation of real-world

processes.

25

3.4.4 Important in Cryptographic Implementations

A ubiquitous use of unpredictable random numbers is in cryptography which underlies most of

the schemes which attempt to provide security in modern communications (e.g., confidentiality,

authentication, electronic commerce, etc.).

Even if a better random number generator is used, it might be insecure (i.e., its starting value, the

seed might be guessable), producing predictable keys and reducing security to nil. (A

vulnerability of this sort was famously discovered in an early release of Netscape Navigator,

forcing the authors to quickly find a source of "more random" random numbers.) For these

applications, truly random numbers are ideal, and very high quality pseudo-random numbers are

necessary if truly random numbers, such as coming from a hardware random number generator,

are unavailable.

Truly random numbers are absolutely required to be assured of the theoretical security provided

by the one-time pad — the only provably unbreakable encryption algorithm. Furthermore, those

random sequences cannot be reused and must never become available to any attacker, which

implies a continuously operable generator..

For cryptographic purposes, one normally assumes some upper limit on the work an adversary

can do (usually this limit is astronomically sized). If one has a pseudo-random number generator

whose output is "sufficiently difficult" to predict, one can generate true random numbers to use

as the initial value (i.e., the seed), and then use the pseudo-random number generator to produce

numbers for use in cryptographic applications. Such random number generators are called

cryptographically secure pseudo-random number generators, and several have been

implemented.

3.5 CPLD Hardware Implementation

A complex programmable logic device (CPLD) is a programmable logic device with

complexity between that of PALs and FPGAs, and architectural features of both. The main

building block of the CPLD is amacrocell, which contains logic implementing disjunctive

normal form expressions and more specialized logic operations.

26

3.5.1 CPLD Features

Some of the CPLD features are in common with PALs:

Non-volatile configuration memory. Unlike many FPGAs, an external

configuration ROM isn't required, and the CPLD can function immediately on system start-

up.

For many legacy CPLD devices, routing constrains most logic blocks to have input and

output signals connected to external pins, reducing opportunities for internal state storage

and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD

product families.

Other features are in common with FPGAs:

Large number of gates available. CPLDs typically have the equivalent of thousands to tens

of thousands of logic gates, allowing implementation of moderately complicated data

processing devices. PALs typically have a few hundred gate equivalents at most, while

FPGAs typically range from tens of thousands to several million.

Some provisions for logic more flexible than sum-of-product expressions, including

complicated feedback paths between macro cells, and specialized logic for implementing

various commonly used functions, such as integerarithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-

chip non-volatile memory in the CPLD, which allows CPLDs to be used for "boot loader"

functions, before handing over control to other devices not having their own permanent program

storage. A good example is where a CPLD is used to load configuration data for an FPGA from

non-volatile memory.

3.5.2 CPLD kit Design and Prototyping

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first

shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that

offered no programmability and were used to build logic functions by physically wiring several

standard logic chips together (usually with wiring on a printed circuit board, but sometimes,

especially for prototyping, using wire wrap wiring).

27

The main distinction between FPGA and CPLD device architectures is that FPGAs are internally

based on look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (for

example, sum of products).

The daughter board in the CPLD Hardware kit comes with various FPGA and CPLD options

from XILINX and ALTERA. It also provides test pins to connect Pattern generator and Logic

analyzer to connect various Inputs and Outputs of the FPGA. Apart from this the base board

contains various interface options to readily connect switches and displays etc. A number of

tutorial exercises have been worked out. An exhaustive easy to follow documentation has been

provided for quick learning of various environments, schematic and VHDL programming.

Fig 3.6: Flow Diagram of CPLD hardware implementation

28

4.1 RTL and Test-bench Simulations

In digital circuit design, register-transfer level (RTL) is a design abstraction which models

a synchronous digital circuit in terms of the flow of digital signals (data) between hardware

registers, and the logical operations performed on those signals.

Register-transfer-level abstraction is used in hardware description languages (HDLs)

like Verilog and VHDL to create high-level representations of a circuit, from which lower-level

representations and ultimately actual wiring can be derived. Design at the RTL level is typical

practice in modern digital design.

When designing digital integrated circuits with a hardware description language, the designs are

usually engineered at a higher level of abstraction than transistor level (logic families) or logic

gate level. In HDLs the designer declares the registers (which roughly correspond to variables in

computer programming languages), and describes the combination logic by using constructs that

are familiar from programming languages such as if-then-else and arithmetic operations. This

level is called register-transfer level. The term refers to the fact that RTL focuses on describing

the flow of signals between registers.

RTL is used in the logic design phase of the integrated circuit design cycle.

An RTL description is usually converted to a gate-level description of the circuit by a logic

synthesis tool. The synthesis results are then used by placement and routing tools to create a

physical layout.

Logic simulation tools may use a design's RTL description to verify its correctness.

A test bench or testing workbench is a virtual environment used to verify the correctness or

soundness of a design or model, for example, a software product.

The term has its roots in the testing of electronic devices, where an engineer would sit at a lab

bench with tools for measurement and manipulation, such as oscilloscopes, multimeters,

soldering irons, wire cutters, and so on, and manually verify the correctness of the device under

test (DUT). In the context of software or firmware or hardware engineering, a test bench refers to

an environment in which the product under development is tested with the aid of software and

hardware tools. The suite of testing tools is often designed specifically for the product under test.

29

4.1.1 Design of D-ff for LFSR

The following are the output simulation for the D-flip flop, which forms the basic component of

the LFSR.

Fig 4.1: RTL of D-ff

Fig 4.2: Test-bench of D-ff

30

4.1.2 Design of X-NOR for LFSR

The X-nor gate block diagram and the output test bench wave form have been shown as below. It

is used as an input for the feedback.

Fig 4.3: RTL of X-NOR

Fig 4.4: Test-Bench of X-nor gate

31

4.1.3 Design of Clock Gated D-ff for Power Optimization

Power optimization of the Linear feedback shift register is done by clock gating the initial D-ffs

used. Below figures show the block diagram and test bench output of the Clock-gated LFSR.

Fig 4.5: RTL of Clock Gated D-ff

Fig 4.6 Test Bench output of Clock Gated D-ff

32

4.1.4 Design of Clock-Gated Internal LFSR

The power optimized LFSR is shown as follows. In the block diagram, the first part represents

the clock and the next is the final LFSR design. The Hex values are also shown in the test bench

output.

Fig 4.7: RTL of Clock-Gated Internal LFSR

Fig 4.8: Test bench of Clock-Gated Internal LFSR

33

4.1.5 Design of 5-bit Counter

The counter required for x-oring with the LFSR is a 5 bit counter that counts from 0 to 31. The

following is the block diagram and test bench output waveform for the counter.

Fig 4.9: RTL of 5-bit Counter

Fig 4.10: Test bench of 5-Bit Counter

34

4.1.6 Design of the X-ORed LFSR and Counter

The x-ored output of the LFSR and the counter can be seen as follows after the simulation. In the

Test bench result the first row of Hex values is that of the LFSR, the next row of Hex values is of

the counter and the final row represents that of the x-ored output which has much more smaller

state lengths as compare to the previous two.

Fig 4.11: RTL of 5-bit Counter

Fig 4.12: Test bench of X-ORed LFSR and Counter

35

4.2 Performance Analysis

According to the simulation results the following can be observed:-

1. A normal internal LFSR gives a power dissipation of 34mW whereas the power

optimized Clock-gated LFSR has a power dissipation of 24mW. This means the power got

optimized by more than 30% when the clock gated D-flip flops were used in the place of the

normal D-ffs.

2. The output of the Linear Feedback shift register which is a series of Pseudo-random

variables when X-ORed with the output of a counter gives a totally new series of randomness

which is much more greater than the maximum number of states that can be achieved when only

the LFSR is used.

3. A normal 5-bit LFSR can give a maximum out of varied randomness of 32 states, where

as the simulation of the XORed LFSR and Counter gave 64 states of random variables which is

almost double the number of states generated by a normal LFSR.

4. The Power dissipation of the entire system also didn’t come out to be too high and ended

up to 34mW only, which is almost equal to the power dissipation of the non clock gated LFSR.

This increment was due to increased number of circuits in the system.

36

Conclusion and Further work

The following project concludes an entirely new concept and idea of increasing the randomness

of the output generated by a pseudo-random generator without affecting neither the speed of the

generation or the power dissipation of the circuit. When the output of the clock-gated LFSR is X-

ORed with the output of a 5 bit counter gives more number of random states.

There have been many ways of generating random variables for e.g. – through true random

variable generators, empirical resampling and also through pseudo-random generators. But

making a pseudo-generator give more than the expected maximum result is a necessity of present

times. True random variable generators can generate variables with no repetition at all but these

true random variables reduce the speed and efficiency of the system.

A LFSR generates a maximum of 2n-1 output states, but x-oring increases the randomness of the

final output. This is because, the time duration of each state output of the counter and LFSR

different from each other, so when the output states get x-ored the state of the LFSR remains

same while that of the clock changes; hence the final output gives many more x-ored outputs

than an individual LFSR. Thus, through this project we present a totally new method of

increasing the frequency of random variable generation.

This enhanced randomness of the LFSR can play a very important role in cryptographic

applications. Increasing the randomness of the output series will result in generating improved

random variable series which can be used in security purpose of Bank Security Keys and Data

Communication Channels and many other purposes. The method used to increase the

randomness is very easy and can be used on a large scale to generate random variables

equivalent to true random variable generators.

37

References

1. Shatadal Mishra and Mrutyunjay Das,” FPGA based random number generation for

cryptographic applications”, project work, National Institute of Technology,

Rourkela,2010.

2. Shruti Hathwalia and Meenakshi Yadav, “Design and Analysis of a 32 Bit Linear

Feedback Shift Register Using VHDL”, Int. Journal of Engineering Research and

Applications, ISSN: 2248-9622, Vol. 4, Issue 6( Version 6), June 2014, pp.99-102.

3. Laung-Terng Wang, Nur A. Touba, Richard P. Brent, Hui Xu, and Hui Wang,

”Designing Transformed Linear Feedback Shift Registers with Minimum Hardware

Cost”, Computer Engineering Research Center, Department of Electrical & Computer

Engineering, The University of Texas at Austin, November 8, 2011.

4. P.Y. Dibal, “Design and Implementation of Mod-6 Synchronous Counter using VHDL”

Arid Zone Journal of Engineering, Technology and Environment. August, 2013; Vol. 9,

17-26.

5. Vikas Sahu, Mr. Pradeep Kumar, “Power Reduction and Speed Augmentation in LFSR

for Improved Sequence Generation Using Transistor Stacking Method.” International

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4.

6. Kavya Shree C, Praveen Kumar Y G, M Z Kurian , “A Novel approach for

Implementation of LFSR using Reversible Logic”, International Journal on Advanced

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(2015) Special Issue of ICACE 2015 - Held on March 02, 2015,Mysore, India

7. Clock gating, Linear feedback shift register, Synchronous up-counter- Wikipedia, the free

encyclopedia.

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