1

General Up Conversion

• 70 MHz IF, 2.5. 8, & 22 MHz BWs (3dB).

• 204.8 MHz DAC Sample Rate

• Modem provides 25 KHz fine tune step

• Receiver/Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz.

Modem

FPGA

DAC14DUC

Fs = 204.8 MHz

I

Q 2nd IF70 MHz

Exciter

TuningStep=0.5 MHzTsettling = < 100 Hz < 100us

22 MHz 8 MHz

2.5 MHz

22 MHz

1st IF

2

Digital Up Converter

• Baseband samples are converted to 70 MHz “digital IF”

• Polyphase filter approach reduces required 204.8 Msps processing to simple data transfer.

18.8 MHz + 51.2 MHz = 70 MHz

14

x2 Interpolation

DAC

21

sinc

x2 Interpolation

NCO

sincos

21

sinc

+

-

+

+

Complex MixerDACComp

Fine Tune18.8 MHz ± 250 KHz25 KHz step

PolyPhase

FIR

PolyPhase

FIR

CommutateI & Q

204.8 MHz

I

Q

102.4 Msps 204.8 Msps

BasebandWaveformProcessing

51.2 Msps

-1

-1

3

DUC Continued

• 204.8 Msps DAC sample rate required to reduce DAC sinx/x roll-off.

• Final 2x interpolation process employs parallel FIR (polyphase) filters that process at 1x rate.

• Number of filter taps is reduced by factor of two resulting from quarter wave frequency shift.

Equivalent

2

x2 Interpolation

2

14

sin( )

n

cos( )

n

Fs = 204.8 Msps

40 Taps

40 Taps

14

x2 Interpolation

PolyPhase

FIR

PolyPhase

FIR

-1

CommutateI & Q

Fs = 102.4 Msps Fs = 204.8 Msps

-1

20 Taps

20 Taps

4

DUC Filters

14

x2 Interpolation

DAC

2

x2 Interpolation

NCO

sincos

2

+

-

+

+

Complex Mixer CommutateI & Q

204.8 MHz

I

Q

DUC Filter 1Programmable FIR47 Taps each

DUC Filter 220 Taps each

-1

-1

5

DUC Filter 1• 47 tap programmable FIR, 16 bit symmetric coefficients

• BW is adjusted according to waveform mode, I.e., 20, 6, or 1 MHz modes.• Three sets of coefficients must be stored. The proper set of coefficients are

downloaded upon change in waveform BW.

6

DUC Filter 2Simplification

• Original filter is split into even and odd phases and processed in parallel at 102.4Msps (half rate).

• Each output is selected once per 1x sample period to provide x2 rate change.

2

2

Even coef

Odd coef

102.4 Msps 204.8 Msps

102.4 Msps 204.8 Msps

X2 Interploation X2 Interploation

Even coef

Odd coef

Conversion

I

Q

40 taps

40 taps

40 taps

40 taps

7

DUC Filter 2Simplification

• One of two filter phases can be eliminated as a result of quarter wave frequency shift.

• Number of taps is reduced by factor of two.• Real frequency mixer and quarter wave shift is reduced to simple commutation

between I & q filter outputs.• Provides complex to reak conversion and fs/4 frequency shift.

Even coef

Odd coef

Even coef

Odd coef

-sin( )

n

cos( )

n

I

Q

={1,0,-1,0}

={0,-1,0,1}

Even coef

-120 taps

20 taps

-1Odd coef

yi(n)

-yi(n)

-yq(n)

yq(n)

DUC OutConversion

20 taps, each

Output Sequence = { yi(n), -yq(n), -yi(n), yq(n), …}

8

DUC Filter 2• 20 tap FIR, 16 bit symmetric coefficients.

40 taps

h 0,h 2

,h 4,...h 38

EvenCoef

OddCoef

h1 ,h

3 ,h5 ,...h

39

I Channel

Q Channel

20 taps

20 taps

9

DUC Output After 1st Interpolation

14

x2 Interpolation

DAC

2

x2 Interpolation

2

+

-

+

+

Complex Mixer CommutateI & Q

204.8 MHz

I

Q

-1

-1

-120

-100

-80

-60

-40

-20

0

20

0 12.8 25.6 38.4 51.2 64 76.8 89.6 102.4

MHz

dB

DUC Filter1

Signal

-120

-100

-80

-60

-40

-20

0

20

0 12.8 25.6 38.4 51.2 64 76.8 89.6 102.4

f/fs

dB

Shifted Signal

10

DUC Output SpectrumDUC Output

20 MHz & 1 MHz Waveform Modes

-120

-100

-80

-60

-40

-20

0

20

0 25.6 51.2 76.8 102.4 128 153.6 179.2 204.8

MHz

dB

20 MHz

1 MHz

NOTE: Analog IF Filters provide >80 dB additional rejection @ 30 MHz bandwidth.

11

General Down Conversion

• 70 MHz IF, 2.5. 8, & 22 MHz BWs (3dB).

• 102.4 MHz ADC Sample Rate

• Modem provides 25 KHz fine tune step

• Receiver/Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz.

Modem

FPGA

14DDC

Fs = 102.4 MHz

I

Q 2nd IF70 MHz

Receiver

22 MHz 8 MHz

2.5 MHz

22 MHz

1st IF

ADC

TuningStep=0.5 MHzTsettling = < 100 Hz < 100us

12

Digital Down Converter102.4 Msps51.2 Msps

12ADC

102.4 MHz

sincos

NCO

47 tap FIR

47 tap FIR

2

2

I/Q

FFT / PSAM

Freq Error

Tune Freq

Freq Constant

Digital Down Converter

SyncTiming/Freq

Tim

ing

/Fre

q E

rror

BasebandWaveform Processing

13

DDC Output Spectrum

14

DDC / DUC Commonality

• The DDC filter (47 tap) and DUC filter #1 are the same. The DDC and DUC can share the same FPGA filter structures.

• The DDC and DUC share a single DDS FPGA instantiation.

15

DDC / DUC Commonality

14

DAC

2

2

+

-

+

+

204.8 MHz

I

Q

-1

-1

12ADC

102.4 MHz

-sin

cos

NCO

47 tap FIR

47 tap FIRI/Q

Freq Constant

Digital Down Converter

Freq Error

Tune Freq

2

2

SyncTiming/Freq

Digital Up Converter

I

Q

47 tap FIR

47 tap FIR

20 tap FIR

20 tap FIR

Common Filter.

I/Q filter pair is instantiated once in FPGA and shared between DDC and DUC.

Common NCO/DDS

Shared between DUC and DDC.

16

Direct Digital Synthesizer (DDS)• DDS is implemented using Xilinx ip with Taylor series phase

correction.• SFDR » -115 dB • Df < 1 Hz• Phase Accumulator = 32 bits• cos & -sin outputs = 20 bits

17

Direct Digital Synthesizer (DDS)• Output frequency is a combination of a constant frequency

term, tune frequency term, and error frequency term.

MHzf

KHzfKHz

KHzfKHz

where

ff

fMHzf

ffMHzf

clk

error

tune

clk

out

tuneout

errortuneout

4.102

1111

size step 25KHz ,250250

:

2

8.18 :Case DUC

4.32 :Case DDC

32

18

Frequency Uncertainty/Error• Specifications

• Reference Frequency = +/- 1 ppm• Max Doppler Velocity = 700 m/s

Hz

HzMHzsme

smf

c

v

HzMHzppm

833,10yUncertaintFrequencyTotal

58332500/83

/700ErrorDopplerMax

500022500*1ErrorReference

19

Frequency CorrectionRx Packet• Frequency Error is determined during Synchronization

process and applied prior to demodulating Rx packet. (See timing charts.)

Tx Packet• Frequency error term = 0 for Tx slots.

20

DDC/DUC Processing• Maintain 16 bits in/out of DDC and DUC.

• Complex mixer functions should maintain 18 bits at input and truncate to 16 bits at output.

DDS(NCO)

20 bits 18 bitscos

-sin 20 bits

Tru

nca

te18 bits16 bits

Filter/Decimate

16 bitsBasebandProcessing

DDCI or Q

From ADC