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    COMPUTER ORGANIZATION

    ARCHITECTURE

    For

    Computer Science

    Information Technology

    By

    www.thegateacademy.com

    http://www.thegateacademy.com/http://www.thegateacademy.com/http://www.thegateacademy.com/http://www.thegateacademy.com/http://www.thegateacademy.com/http://www.thegateacademy.com/http://www.thegateacademy.com/
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    Syllabus Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30thCross, 10thMain, Jayanagar 4thBlock, Bangalore-11 080 65700750 i f @th t d C i ht d W b th t d

    Syllabus for

    Computer Organization and Architecture

    Machine instructions and addressing modes, ALU and data-path, CPU control design, Memory

    interface, I/O interface (Interrupt and DMA mode), Instruction pipelining, Cache and main

    memory, Secondary storage.

    Analysis of GATE Papers

    (Computer Organization and Architecture)

    Year

    Percentage of marks

    Overall Percentage

    2013

    11.00

    9.48

    2012

    6.00

    2011

    7.00

    2010

    9.00

    2009

    6.66

    2008

    16.00

    2007 9.33

    2006

    9.33

    2005 14.67

    2004

    10.00

    2003

    5.33

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    Contents Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30thCross, 10thMain, Jayanagar 4thBlock, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d Page I

    C O N T E N T S

    Chapter Page No.

    1. Introduction 1 28

    Computer Design 1 4

    Binary Data Representation 4 12

    CPU Design 12 13

    Binary Adder 13 19

    Arithmetic Logic Unit 19 22

    Assignment 1 23

    Assignment 2 24

    26 Answer Keys 27

    Explanations 27 28

    2. Memory 29 60

    Memory Parameter 29 30

    Main Memory 31 36

    Cache Memory 36 42

    Virtual Memory 42 45

    Solved Examples 45

    47 Assignment 1 48 51

    Assignment 2 51 53

    Answer Keys 54

    Explanations 54 60

    #3. Pipelining and Vector Processing 61 82

    Parallel Processing 61 65

    Pipelining 65 74

    Solved Example 74

    Assignment 1 75 77

    Assignment 2 77 78

    Answer Keys 79

    Explanations 79 82

    4. Instruction Set and Addressing Mode 83 99

    Introduction 83

    Instruction format 83 86

    Addressing Modes 86 -87

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    Contents Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30thCross, 10thMain, Jayanagar 4thBlock, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d Page II

    CISC and RISC 87 88

    Solved Example 89

    Assignment 1 90

    93

    Assignment 2 93 94

    Answer Keys 95

    Explanations 95 99

    #5. CPU Operation and Design 100 - 110

    CPU Operations 100 103

    Data Path and Control Path 103 104

    Machine Cycle 104 107

    Assignment 108 109

    Answer Keys 110

    Explanations 110

    #6. I/O Interface (Interrupt and DMA Mode) 111 131

    Introduction 111

    Difference between the Computer and Peripheral Devices 111

    I/O Bus and Interface Modules 111 112

    Modes of Data Transfer 112

    116 I/O Communication Technique 116 118

    Direct Momory Access (DMA) 119 124

    Assignment 1 125 126

    Assignment 2 126 128

    Answer Keys 129

    Explanations 129 131

    #7. Control Unit Design 132 141

    Von-Neumann Architecture 132

    133 Von-Neumann Bottleneck 133

    Harvard Architecture 134

    Control Unit 134 137

    Solved Examples 137 138

    Assignment 139 140

    Answer Keys 141

    Explanations 141

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    Contents Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30thCross, 10thMain, Jayanagar 4thBlock, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d Page III

    Module Test 142 153

    Test Questions 142 148

    Answer Keys 149

    Explanations 149 153

    Reference Books 154

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    Chapter-1 Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30th

    Cross, 10th

    Main, Jayanagar 4th

    Block, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d P 1

    CHAPTER 1

    Introduction

    Computer Architecture

    Computer architecture deals with the structure and behavior of the computer system. It includesthe information formats, the instruction set and the hardware units that implement the

    instructions along with the techniques for addressing memory.

    Computer Organization

    Computer organization deals with the way the various hardware components operate and the

    way they are connected together to form the computer system. It also deals with the units of the

    computer that receive information from external sources and send computed results to externaldestinations.

    Computer Design

    Computer design is concerned with the hardware design of the computer. This aspect of

    computer hardware is sometimes referred to as computer implementation. Figure 1.1 shows the

    basic building blocks of a typical computer system.

    The basic blocks available in any digital computer are, Arithmetic Logic Unit (ALU), ControlUnit, Memory and Input/Output Unit.

    Input Unit

    It is a medium of communication between the user and the computer. With the help of input

    unit only, it is possible to enter programs and data to the computer.

    Examples

    Keyboard, floppy disk drive, hard disk drive, mouse, Magnetic Ink Character Recognition(MICR), Optical Character Recognition (OCR), paper tape reader, Magnetic tape reader,

    Scanner etc.

    Output Unit

    It is a medium of communication between the computer and the user. With the help ofoutput unit only, it is possible to get results from the computer.

    Example: Printers, Video Display Unit (VDU), Floppy disk drive, Hard disk drive, Magnetictape drive, punched cards, paper tape, plotter, digitizer etc.

    MEMORY

    INPUT OUTPUT

    ALU

    CPU

    CU

    Fig. 1.1 Basic functional units of a computer

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    Chapter-1 Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30th

    Cross, 10th

    Main, Jayanagar 4th

    Block, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d P 2

    Memory

    The memory unit is responsible for storing the user programs and data. The digital computer

    memory unit mainly consists of two types of memories: Read Only Memory (ROM) and ReadWrite Memory (R/WM) or Random Access Memory (RAM).

    ROM

    ROM is used to store permanent programs or system programs. It does not have writecapability.

    Types: PROM, EPROM, EEPROM

    RAMIt is also called user memory because the user programs or application programs are

    stored in this memory. The CPU is able to write or read information into or from thistype of memory.

    Types:static, dynamic, scratch pad etc.

    Central Processing Unit CPU)

    The ALU and Control Unit together are called CPU. It is the heart of any digital computer.

    ALU Arithmetic Logic Unit)

    The data processing part of CPU is responsible for executing arithmetic and logical instructionson various operand types including fixed point and floating point numbers.

    Various circuits used to execute data processing instructions are usually combined in a single

    circuit called an arithmetic logic unit (ALU). The complexity of an ALU is determined by the wayin which its arithmetic instructions are realized. Simple ALUs that perform fixed point additionand subtraction as well as word based logical operations, can be realized by combinationalcircuits. Much more extensive data processing and control logic necessary to implement is

    floating point arithmetic in hardware.

    Example

    For finding the sum of a series , how will you usean ALU without a multiplier unit but with an adder and barrel shifter? Barrel shifter is a shifter

    that does shift at an instance.SolutionLeft shift by 7 means multiplication by 128,6 means multiplication by 64,5 means multiplicationby 3 and means multiplication by. Hence the shift operations will be faster forcomputing . Using the barrel shifter seven times for shifting by 3 .. we find and store leftshifted values of in a register and add these.Two Types of ALUs

    1.

    Combinational ALUs

    The simple ALU combine the functions of s complement adder-subtracter with those of acircuit that generates word based logic functions of the form f(x, y).For example AND XOR and NOT. They can thus implement most of a CPUs fixed point dataprocessing instructions.

    2.

    Sequential LUs

    Both multiplication and division can be implemented by combinational logic. It is generally

    impractical to merge these operations with addition and subtraction into a single,

    combinational ALU.

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    Chapter-1 Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30th

    Cross, 10th

    Main, Jayanagar 4th

    Block, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d P 3

    The combinational multipliers and dividers are costly in terms of hardware. They are also

    much slower than addition and subtraction.

    An n-bit combinational multiplier or divider is typically composed of n or more levels of

    add-subtract logic making multiplication and division at least n times slower thanaddition (or) subtraction, where addition and subtraction each take one clock cycle, whilemultiplication and division are multicycle operations.

    Example

    How many 16-bit ALU slices can be used for designing a 64-bit ALU?

    SolutionFour slices will be needed in parallel if ALU 64-bits operations are to take nearly the same time

    as 16-bit slice, and four slices will be needed in series if ALU 64- bits operations are to takenearly four times of 16-bit slice.

    Interconnection of basic of blocks

    In order to form an operational system individual components or parts of computer that we

    have discussed need to be connected in some organized way for this purpose u is introducedwhich is defined as a group of lines that serves as a connecting path for several devices. Theselines carry data, address and control signals.

    Figure 1.2 shows a exemplanary interconnection using single bus structure

    Since, this bus can be used only for single transfer at a time Multiple busesare introduced so asto achieve more concurrency in operations so that two or more transfers can be carried out atthe same time. Hereby, increasing performance but at an increased cost.

    Control Unit

    The control unit (CU) is the heart of the CPU. Every instruction CPU supports has to be decidedby the CU and executed appropriately. Every instruction consists of a sequence of micro

    instructions that carries out that instruction the CU controls the elements inside the CPU theinterface to the external data rate.

    Following are the basic tasks of the control unit

    1. For each instruction the CU causes the CPU to go through a sequence of control steps:

    2.

    In each control step the CU issues a set of signal which caused the correspondingoperation to be executed.

    OutputMemory CPU

    Fig1.2. Single-bus Structure

    Input

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    Chapter-1 Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30th

    Cross, 10th

    Main, Jayanagar 4th

    Block, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d P 4

    3. The signals to be generated by CU depends upon the actual step to be executed, the

    condition and states of flag register of the processor, the actual instruction to be executed

    and any external signals received on the system bus (i.e., interrupt signals)

    Binary data representation

    In digital computer, integers are represented as binary numbers of fixed length. A binarynumber of length x is an ordered sequencex x x . . . x xOf binary digits where each digit

    x(also known as a bit)

    Can assume one of the values 0 or 1The above sequence of x digits represents the integer value

    X x x . . . . x x x.

    Since operands and results in an arithmetic unit are started in resisters of a fixed length, there isa finite number of distances that can be represented with in an arithmetic unit. Let x andxdenote the smallest and largest representable value. We say that x x is the rangeof the number

    A sequence of n digits in a register does not necessarily have to represent an integer. We can getsuch a sequence to represent a mixed number that has a fractional part as well as an integral

    part. This is done by portioning the n digits into two series; k digits in integral part and in digitsin the fractional part, satisfying k +m = n

    xx. . . . . xx xx. . . . . x The above sequence of n digits represents the value

    X x x . . . . . x x x . . . . . x x

    The radix point is now stored in the register but is understood to be in a fixed position between

    k most significant digits and the m least significant digits. For this reason we call suchrepresentation as fixed-pointrepresentation

    IR

    Common signals

    internal to the CPU

    Common signals

    internal on system bus

    Signals from system bus

    Control Unit (CU)

    Clock

    Flags

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    Chapter-1 Computer Organization

    THE GATE ACADEMY PVT.LTD. H.O.: #74, Keshava Krupa (third Floor), 30th

    Cross, 10th

    Main, Jayanagar 4th

    Block, Bangalore-11

    080 65700750 i f @th t d C i ht d W b th t d P 5

    Representation of negative numbers

    For fixed point numbers, we have to determine the way negative numbers are represented. Two

    different terms are commonly used:

    1.

    Sign and magnitude representation

    Which is also called the signed-magnitude method

    2. Complement representationWhich comprises two alternatives

    Signed magnitude

    In this representation the first digit is the sign digit and the remaining digits representmagnitude. In binary case sign bit is normally selected to be o for +ve numbers and 1 for +veones.

    Let the

    digits representing the magnitude be partitioned into

    and m digits in the

    integral and fractional part, respectively. The largest representable number is then, ( )Thus the range of +ve numbers is [ ]and the range of ve number is ( ).We therefore have two representations of zero, one +ve and ve.A major disadvantage of the signed-magnitude representation is that the operation to beperformed may depend on the signed of the operands. This is avoided in the complementrepresentation methods

    Complement representationThere are two alternatives

    1. Radio complement also called s complement2. Diminished radix complement also called s complement

    In both complement method, a +ve number is represented in the same way as in the signal

    magnitude method, where a negative number is represented by , where R is aconstant. Such a representation satisfies the basis identify One of the major advantages of a complement method is that no decisions have to be made

    before executing an addition or substation If

    the

    ve result

    is already in the same complement form. However if

    , the

    correct result should be , while . The addition term R must bediscarded, and the value of R should be selected to simplify or completely eliminate thiscorrection step.

    In case of s complement the value of R is and for complement the value of R is .The range of numbers in the twos complement for is This range is slightly a symmetric as then is one more ve number than are +ve numbers, on thehand these is a unique representation for 0.

    The range of representable number in the ones complement system is symmetric

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