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IEEE Students Conference on Electrical, Electronics and Computer Science

232

Design of Ultra-Wideband Balun-Low

Noise Amplifiers

B.S.Prakash Reddy

Department of ECENational Institute of Technology

Calicut, India

[email protected]

B.Bhuvan

Department of ECE

National Institute of Technology

Calicut, [email protected]

Abstract A 0.13m CMOS Balun-LNA in the frequency band

of 2.1GHz-9.5GHz for ultra-wideband applications has been

designed and simulated. A Common Gate (CG) amplifier with

source degenerated inductance gives input matching over ultra-

wideband frequency range. The combination of a Common-gate

(CG) stage and an admittance-scaled common-source (CS) stage

with replica biasing is used to maximize balanced operation while

canceling the noise of the CG stage. The simulation results show

that the balun-LNA achieves NF < 2.8dB, S 11 less than -10dB,

maximum gain of 17.8dB with a power consumption of 18.5mW

(including buffers) from 1.2V supply.

Keywords-balun, low noise amplifiers, noise cancellation, wideband matching

I. INTRODUCTIONLow noise amplifiers (LNAs) widely used in wireless

communication are expected to boost the desired signal powerwhile adding as little noise and distortion as possible.Differential signaling in the receivers is preferred in order toreduce second-order distortion and to reject power supply andsubstrate noise. Balun converts a single ended signal into

differential signal and vice-versa. Combining balun and LNAfunctionalities into a single integrated circuit reduces area andpower consumption. This paper discusses the design of anultra-wideband balun-low noise amplifier.

The paper is organized as follows. In section II, a briefreview of simultaneous output balancing and noise canceling isgiven, section III, discusses the matching network designsection IV discusses the circuit implementation and simulationresults while section V draws conclusion.

II. A BRIEF REVIEW OF OUTPUT BALANCING AND NOISECANCELING

A balun formed by the basic common gate and commonsource topology is shown in Fig.1. This parallel combination ofCommon Source (CS) stage and CG stage is implemented in[1], [2] with identical size and bias for CG and CS devices. Thecircuit implemented in [1] has drawback of gain imbalancesince the CS stage is scaled n-times that of CG stage. Variousdesign considerations for balun-LNA are presented in [3], [4].To create balun, the gain of the CS stage in Fig.1 should beequal, but have opposite sign to that of CG stage. For effectivethermal noise canceling with output balancing appropriatescaling of the CS stage is necessary [5].

Fig.1 Balun-LNA [5]

III. ULTRA-WIDEBAND INPUT MATCHINGIn [5] the bias to the CS stage is given through a resistor

RB. This consumes valuable DC voltage headroom. Apart fromthis, resistor RB contributes to thermal noise at the output. Thewidth of the CG transistor with degenerated resistor has to be

increased to maintain the of 20mS and IDS of 2.3mA for thesame bias voltage as compared to CG transistor withdegenerated inductor. This increases the parasitic capacitancesat the input which degrades the input matching. Due to theimpedance mismatch the signal transfer to the source of the CGtransistor is a ffected which decreases the gain of the circuit. Toavoid DC voltage drop and to lower the noise figure, theresistor RB is replaced by an inductor. Since the voltage dropacross the inductor is not sufficient to bias the CS stage, thebias for CS stage is applied independently.

The input impedance of the common gate amplifier has tobe 50

power transfer. The quality of the input matching is measuredwith S-parameter S11, which is defined as:

where Zin is the input impedance and Z0 is the loadimpedance.

Though the CG stage is biased to 20mS to realize 50 realimpedance, the impedance looking into the source of CGtransistor is complex due to the parasitic capacitances presentat the input. To match the network, the reactance part has to be


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Design of Ultra-Wideband Balun-Low Noise Amplifiers


233

kept minimum. The circuit within dotted lines in Fig.2represents the matching network. This matching network canbe viewed as a pi- network.

Fig.2 Input Matching Network

The capacitor C1 is used to block the DC signal from the inputsource and the capacitor C2 is used to prevent the DC currentflowing into the input source. CP is the parasitic capacitance.The parasitic capacitance CP, is absorbed into the matchingimpedance network. The network formed by L1, L2 and C2forms a pi-network which gives band-pass characteristics. Theparallel combination of L2 and CP forms a parallel tank circuit

whose resonant frequency is given by

The parallel tank circuit provides minimum admittance at theresonant frequency around 6GHz.

Design of pi- network:

Fig.3 pi-network

The pi-network is designed to pass the frequencies between3.1GHz to 10.6GHz. The quality factor , of Fig.3 is given by

Where is the center frequency whose value is 5.75GHz

The filter network is realized with the help of a virtual resistor,RV [6]. Two LC sections are separated by the virtual resistor.The source and load impedances are matched to R Vindividually.

The design equations are:

Where = 50 = 0.76

By substituting above values and from (7), (8), (9), (10) the

RV is 32 , L1=L2 2 + C2 .

IV. CIRCUIT IMPLEMENTATIONThe transconductance of the CG transistor shown in Fig.4 is

20mS to realize impedance matching to a 50 ohm source. The

transconductance, .This requires about 2.3mA of

biasing current for a transistor at approximate moderate

overdrive voltage of 0.2V. To find the W/L value, the

current equation can be written as W/L = , where

This corresponds to W/L =

31m/120nm The voltage drop across the load resistor is fixedas 0.7V. This leaves 0.5V for the sum of drain to source

voltages of the input and cascode transistor which is sufficientto keep each MOS transistor in saturation.With 2.3mA bias

current in the CG stage and 0.5V headroom, the CG loadresistor(RL1) is about 300 ohms. The transconductance of the

CS transistor is made approximately 80mS and load resistance

(RL2) is scaled proportionally for simultaneous outputbalancing and noise canceling. This requires about 8mA of

biasing current for a transistor with W/L = 124m/120nm.

The gain of the circuit can be increased by adding the

cascode structure at the cost of noise figure. However, the

cascode structure provides better reverse isolation. Fig.5 &Fig.6 show the effect of cascode on the reverse isolation andnoise figure respectively. At high frequencies, the gain is

limited by the parasitic capacitance at the output. To maintain

flat gain at high frequencies, additional inductance is added to

the load resistors. For effective output balancing, the load

inductances are scaled properly. The values of the inductors

are given in Table I along with other component values.

TABLE I COMPONENT VALUES

Component Value Component Value

M1,M3 31/0.12 M2 124/0.12

M4 96/0.12 C1 10pF

C2 1.5pF CC 3pF

RL1 295 RB, RL2 1K , 72

L1 2.5nH L2 3nH

L3 3nH L4 0.75nH


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234

Fig.4 Ultra Wideband Balun-LNA

Fig.5 Reverse Isolation comparison with CG degeneratedinductor

Fig.6 Noise Figure comparison with CG degenerated Inductor

TABLE II COMPARISON OF BALUN-LNA CIRCUITS

[2] [4] [5] [8] This Work

Freq

(GHz)

0.2-5.2 0.1-6.5 0.05-10 2-9 2.1-9.5

S21(dB)13-15.6 19 18-20 11.5 1dB 14.2-17*

14.5-17.8**

S11(dB)


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235

Table II shows the comparison of the balun-LNA to otherwideband baluns [2], [4], [5] and wideband inductorless single

ended LNAs [8]. IIP2 and IIP3 are evaluated by considering

two near frequencies 3.1 GHz and 3.4GHz within the

frequency band of operation 2.1GHz to 9.5GHz.

Fig.7 Power Gain comparison with cascode structure

Fig.8 Input Matching with cascode structure

Fig.9 Noise Figure comparison with Cascode structure

V CONCLUSION

In this paper, an ultra wideband low noise amplifier withbalun has been presented. The circuit is designed with UMC0.13m CMOS technology for ultra wideband applications.The LNA exhibits maximum gain of 17.8dB, minimum noisefigure of 2.4dB with cascode and 1.8dB without cascodestructures while consuming a DC power of 18.5mW from 1.2Vsupply.

REFERENCES

[1] F.Bruccoleri, E.A.M.Klumperink, and B.Nauta, Wide-band CMOSlow-noise amplifier exploiting thermal noise canceling, IEEE Journalof Solid-State Circuits, Vol. 39, No.2,pp. 275-282, Feb. 2004.

[2] B.Razavi, Cognitive Radio Design Challenges and Techniques, IEEEJ. Solid-State Circuits, vol.45, no. 8, pp. 1542-1553, Aug. 2010.

[3] R.Bagheri, A.Mirzaei, S. Chehrazi, M.E.Heidari, M. Lee, M.Mikhemar,W.Tang, and A. A. Abidi, An 800-MHz-6-GHz software-definedwireless receiver in 90-nm CMOS , IEEE J. Solid-State Circuits, vol.41, no. 12, pp. 2860-2876, Dec. 2006.

[4] S.Chehrazi, A.Mirzaei, R.Bagheri, and A.Abidi, A 6.5GHz wide bandCMOS low noise amplifier for multi-band use, in proc. 2005 IEEECustom Integrated Cicuits Conf. (CICC 2005), San Jose, CA, Sep.2005,pp. 801-804.

[5] S.C.Blaakmeer, E.A.M.Klumperink, D.M.W.Leenaerts, and B.Nauta,

Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling, IEEE Journal of Solid-StateCircuits,Vol. 43,pp. 1341-1350, Jun.2008.

[6] Chris Bowick, RF Circuit Design, Newnes, 1982.

[7] S.C.Blaakemeer,E.A.M.Klumperink,.M.W.Leenaerts,and B.Nauta, TheBLIXER, a wideband Balun-LNA-I/Q Mixer topology, IEEE Journalof Solid-StateCircuits,Vol.43,No.12,Dec.2008.

[8] Taris, T.; Begueret, J.B.; Deval, Y.; A low voltage current reuse LNAin a 130nm CMOS technology for UWB applications, in European

Microwave Conference, 2007.

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