Future of Microprocessors by Christof Kobylko

Seminar „Multi-Core Architectures and Programming“, 16.05.2013

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Table of Contents

● Transistor Technology

● Moore‘s Law

● CMOS Technology Scaling

● Problems and Possible Future Technologies

● Microprocessor Architectures

● Single-Thread Performance Problem

● „Dark Silicon“

● Clock Frequency vs. Power Consumption

● Multi-core Architectures

● Literature

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Moore‘s Law

● Observation of microprocessor trends by Intel co-founder Gordon

Moore in 1965

● States that the number of transistors in integrated circuits doubles

every two years

● Widely applied to many different applications

● Inspired MOSFET scaling theory of Robert Dennard

Scaling of all CMOS design parameters at the same rate:

● Geometric dimensions

● Supply voltage

● Doping concentrations

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CMOS Technology Scaling

● CMOS technology gets to its limits Moore‘s Law too optimistic

● Various projections for future CMOS technology nodes (from [2]):

0

1

2

3

4

5

6

45 32 22 16 11 8

Clock frequency

0

0,2

0,4

0,6

0,8

1

1,2

45 32 22 16 11 8

Technology node [nm]

Core voltage

0

0,2

0,4

0,6

0,8

1

1,2

45 32 22 16 11 8

Power consumption

Moore's Law

ITRS 2010

Conservative studies

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Problems and Possible Future Technologies

● Problem: CMOS Technology starts to reach physical boundaries

● Material properties

● Quantum tunneling not negligible anymore

● Increased leakage current and static power consumption

● Geometric limits (e.g. mono-layer dielectrics)

Recent studies predict end of CMOS between 11 nm and 5 nm

● Arising need for completely new circuit technologies (see [3] and [4])

● Electrical-dependent nanodevices (e.g. nanotubes, quantum dots)

● Magnetic-dependent nanodevices (e.g. SpinFETs)

● Mechanical-dependent nanodevices (e.g. molecular switches)

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Table of Contents

● Transistor Technology

● Moore‘s Law

● CMOS Technology Scaling

● Problems and Possible Future Technologies

● Microprocessor Architectures

● Single-Thread Performance Problem

● „Dark Silicon“

● Clock Frequency vs. Power Consumption

● Multi-core Architectures

● Literature

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Single-Thread Performance Problem

● Main research focus: Increasing single-thread performance

● Problem: Limitation of allowed power consumption

● Typical methods:

● Advances in microarchitecture „Dark silicon“

● Increased clock frequency Energy efficiency

fVCP DD2

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„Dark Silicon“

● Huge power demand for logic transistors unused chip area

● Introduction of caches (low power demand, but limited benefit)

Tradeoff between logic and cache transistors (from [1])

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Clock Frequency vs. Power Consumption

● Transistor speed depends on voltage overdrive

● Cubic dependency between power and clock frequency

Increasing the frequency rapidly decreases efficiency

Dependency between energy efficiency and speed (from [1])

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Multi-core Architectures (1)

● Increasing single-thread performance is inefficient

● Idea: Build multi-core CPUs

Power consumption scales linearly with core count

● Problem: Total performance limited by the applications needs

Waste of available resources

● Possible solution: Heterogeneous architectures

● One large and fast core single-thread performance

● Many small and slower core throughput and peak performance

● Dedicated specialized accelerators energy efficiency

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Multi-core Architectures (2)

● Further increase in efficiency by fine-grain power management

● Some cores at maximum frequency single-thread performance

● Many cores at lower frequency and voltage efficiency

a) b) c) d)

Various multi-core architectures: a) few homogeneous large cores, b) many homogeneous small cores,

c) heterogeneous cores, d) heterogeneous cores with fine-grain power management (from [1])

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Multi-core Architectures (3)

● Rising number of cores Higher demand on interconnection

● Bus-based interconnection

● Pro: Fast transmission, low energy effort

● Contra: One connection at-a-time

● “Circuit-Switching”-based interconnection

● Pro: Fast transmission, low energy effort

● Contra: Connection overhead, Number of connections limited

● “Network-on-Chip”- / NoC-based interconnection

● Pro: Dynamic routing High throughput

● Contra: Packet-overhead, very high energy consumption

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Multi-core Architectures (4)

● No overall superiority of any interconnection type

Hierarchical, heterogeneous interconnect-networks with high locality

Example architectures for hierarchical interconnect-networks (from [1])

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Literature

● [1] S. Borkar and A. A. Cien. „The Future of Microprocessors“.

Communications of the ACM, 54(5): 67-77, May 2011

● [2] H. Esmaeilzadeh et al. „Dark Silicon and the End of Multicore

Scaling“. IEEE International Symposium on Computer Architecture,

pp. 365-376, June 2011

● [3] N. Z. Haron and S. Hamdioui. „Why is CMOS scaling coming to

an END?“. IEEE International Design and Test Workshop,

pp. 98-103, December 2008

● [4] N. Z. Haron et al. „Emerging Non-CMOS Nanoelectronic Devices -

What Are They?“. IEEE International Conference on Nano/Micro

Engineered and Molecular Systems, pp. 63-68, January 2009

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Questions ?