FUSE 27436 Rev. 1 15.02.00 1

FUSE DEMONSTRATOR DOCUMENT

Application Experiment No. 27436

Company name: DATALOGIC S.p.A.via Candini, 240012 - Lippo di Calderara di RenoBOLOGNA - ITALIA

Tel: +39 51 6459211Fax: +39 51 725223

e-mail: rzocca@datalogic.itweb address http:// www.datalogic.itAE Number: 27436

Project: A MICROSYSTEM FOR A BARCODE SCANNERA CMOS-microsystem, integrating image sensor and electronics in a single chip, allows aconsistent size reduction and achieves a cost saving of 24%.

Duration: 20 monthsCost: 150 KEURO

Industrial sector: Optical Instruments and Photographic Equipment- PRODCOM: 3340Company size: 200

Ass. TTN centre: CESVIT S.p.A. - ITALY

FUSE 27436 Rev. 1 15.02.00 2

AE abstractDatalogic is an European leader in the design, manufacture, sales, distribution and service of CCD and laser-based HandHeld and Fixed Position Bar Code Readers, Portable Data Capture, Automated Data Collection in manufacturing,transportation, distribution, retail, airports, food and health care industries and all levels of government.In 1998 Datalogic produced a turnover exceeding 55 million EUROs The employees are about 520 world wide. Datalogicproducts are sold through original equipment manufacturers (OEMs), value-added resellers (VARs), distributors, retailersand system integrators worldwide.Products that Datalogic sells in the largest volume are hand held bar-code reader actually based on a CCD sensor of 2048pixels and the IHHC, an ASIC using mixed Analog\Digital BiCMOS technology. Main applications are retail, officeautomation, and logistics in light industrial environments.The purpose of the Application Experiment has been to develop a microsystem integrating both the optical sensor andthe electronic circuit necessary for signal processing using CMOS technology. Recent advances have led to the CMOSactive pixel sensor (APS, having a buffer/amplifier into the pixel) that is performance competitive with CCDs but withvastly increased functionality. CMOS-based image sensor, thanks to its full compatibility with CMOS technologies,offers the potential opportunity to integrate a significant amount of VLSI electronics on-chip and to reduce componentand packaging costs.The main purpose of this project was to take advantage in competitiveness on the market by a cost reduction passingthrough the technology innovation of the products. In addition to cost reduction, this new technology gave additionalinteresting features as size reduction, configurability, and reliability of the readers, as well as high performance.The duration of the AE was 20 months, its cost was of about 150 KEURO The pay back period is about 24 months. Thereturn of the investment sustained to develop the prototype of the new product is anticipated in 567%.Additional 114 KEURO will be required to carry out the industrialisation phase of the developed prototype. ROI will be of326% if considering these costs also.

The AE is in the interest of companies that work in the automatic identification area using image sensor along with signalprocessing circuits for low cost applications.

Keywords: MicrosystemCMOS sensor and switched capacitor circuitBarcode readerChip Size PackagingCCD technologySuccessful project planning with contingency planAppropriate choice of subcontractor

Signature: 7-11545101440-2-3340-2-33-I

1. Company name and addressDATALOGIC S.p.A.via Candini, 240012 Lippo di Calderara di RenoBolognaITALY

Phone +39 51 6459211Fax +39 51 725223WWW address www.datalogic.it

AE contact person: Rinaldo Zocca (email: rzocca@datalogic.it)

FUSE 27436 Rev. 1 15.02.00 3

2. Company sizeDatalogic S.p.A., consequently to a reorganisation process, carried out a company split at the end of 1997.Starting from 02.01.98, there are two companies that act on the market: Datalogic S.p.A. and INDUSTRIEELETTRONICHE SENSOR S.p.A. (shortened in I.E.S. S.p.A.) with head office in Monte S.Pietro (Bo) involved in design,manufacturing and distribution of automation products.I.E.S. S.p.a., as “spinor”, is the company which the economic relations and obligations born before the split refer to.The reason of this operation is to better take the development opportunities offered to the two business unit (devices toread the bar code and automation products).

Nowadays, Datalogic has its headquarters, Datalogic S.p.A, in Lippo di Calderara di Reno, in the Italian province ofBologna. The employees are about 200 in Bologna and more than 520 for the whole Datalogic Group.

0 10 20 30 40 50 60 70

ENGINEERS

TECHNICAL SUPPORT

PRODUCTION

SALES

Fig. 1 Datalogic S.p.A: people distribution by professional group

In 1998 Datalogic produced a turnover exceeding 55 million EUROs. Since Datalogic S.p.A. is a new company there arenot Financial Reports before 1998. Anyway Datalogic S.p.A. has a strong financial structure and, in prospect, a veryinteresting profitability.

Datalogic is present world-wide with its sales organisation composed by direct subsidiaries and partners and it is directlypresent in Australia, Austria, Denmark, France, Germany, Great Britain, Japan, India, Italy, the Netherlands, Spain,Sweden and in the U.S.A.In order to promote the penetration of its products, in recent years the company developed a network of specialiseddistributors and VARs called Quality Partners, selected and qualified in order to offer services and solutions up to thehighest level in industry.

46%

12%6%

6%

16%

5% 3% 6%ITALYDL SUDNORTHERN EUROPEWESTERN EUROPECENTRAL EUROPEUSAAUSTRALIAUK

Fig. 2 Datalogic world-wide: people distribution by country

Datalogic’s offer is structured in three Product Groups:

• HHD - Hand-Held Devices — hand held bar code readers for automatic data collection in the retail, officeautomation, logistics and services sector.

• USS - Unattended Scanning Systems — industrial fixed position bar code scanners for automatic data collection inthe manufacturing, automation, logistics, and transport sectors.

FUSE 27436 Rev. 1 15.02.00 4

• PDC – Portable Data Collection - portable both in batch and wireless configurations for automatic data capture inmanufacturing, logistics, distribution and retail.

Datalogic has in Italy three facilities structured as follows:

Datalogic S.p.A. Lippo di Calderara (Bologna) Italy• Datalogic’s headquarters• Design and develope for HHD product group• Design, develope, and manufacturing for USS product group

Datasud S.r.l. Castiglione Messer Raimondo (Teramo) Italy• Manufacturing for HHD product group

IDWare Mobile Computing & Communications S.r.l. Mogliano Veneto (Treviso) Italy• Design, develope, and manufacturing for PDC product group

3. Company business descriptionDatalogic product range covers both hand-held and fixed-position bar code readers using both laser and CCDtechnologies. With the acquisition of IDWare Mobile Computing & Communications S.r.l., the largest Europeanmanufacturer of portable terminals, Datalogic’s offer today also includes one of the widest ranges of portable terminalsfor data collection available on the market.

HHD - Hand-Held DevicesDatalogic, that is the only European company that manufactures both laser gunsand CCDs, offers products designed for use in three main fields: Point of Sale(POS), with typical implementation in the non food sectors; Office Automation,with applications such as document tracking in post offices, banks andgovernmental offices; and Logistics, typically in production flow and stocksmanagement control.

Datalogic’s HHD range includes optic pens, CCD and laser readers, decoders andportable terminals for automatic data collection in the retail, office automation,logistics, services and industrial sectors.

CCD readers include the product that is identified as DLC7070, CCD GUN™,offering the performance of a laser reader at the price of a CCD reader. Moreover, it is the only bar code reader on themarket designed to operate at the “instinctive reading distance” (3-18 cm) in the best possible way. Laser scanners consist of industrial laser guns characterised by raggedness, reliability and durability. Some of them areavailable in both wired and wireless versions. For instance DL910/910LR, especially created for harsh environments,offers IP64 protection class and a maximum reading distance of 2 m. (in its Long-Range version). Witin the same familyDLL5010-M, the Shark™, was Winner of the Industrial Design Excellence Award of the Industrial Design Society ofAmerica in 1997.Among the optic pens, P51 is suitable to both office and industrial environments thanks to its IP64 protection class andretractable tip. Finally, Datalogic decoders are compact multistandard decoders covering the most common applications with highdecoding performance. They offer many connection possibilities, in particular LAN data collection, in line with the mostcommon industrial standards.

USS - Unattended Scanning SystemsIn the field of industrial automation applications requiring unattended or fixed position bar code scanning, Datalogic USSscanners has gained an outstanding reputation. Datalogic USS range targets the OEM and manufacturing markets

FUSE 27436 Rev. 1 15.02.00 5

(automatic sorting and assembly, quality control, automated document handling),distribution, logistics and material handling (airport baggage sorting, airport cargoservices, express couriers, postal services, mail ordering).The whole range of fixed-position bar code scanners will also be on display. Itconsists of the following four families, based on the segmentation of products byperformance and target markets:

• Family 2000 (Compactness), including TC2100, compact CCD scannercombining advanced optics with the innovative SFLS™ (Software FocusLevel System) for easy decoding of high- and low-density codes. This

family includes also DS2200, the smallest laser scanner in the world • Family 4000 (Flexibility); features high reading and decoding performance, compact dimensions and anexcellent price/performance ratio. • Family 6000 (Performance) offers immunity to ambient light and very high reading and decoding performancethanks to innovative Datalogic patented technologies. It includes products like laser scanners with display,keypad, Adjustable Focus System and a built-in decoder. • Family 8000 (Solution) offers top reading and decoding performance and 2D-symbologies decoding thanks toinnovative Datalogic’s patented technologies. It includes DS8100, the most powerful laser scanner on themarket, VS8000, a new exceptional volume-measuring laser scanner, and DVS360 which is a stationary CCDscanner for the automatic omni-directional reading of all the most popular bar codes and 2D symbols.

The USS range also includes industrial decoders, combining decoding functions, ease-of-installation with cost-effectiveness, and controllers with display and keypad for high-speed data collection, real time elaboration and systemsupervision.

PDC – Portable Data Collection Datalogic’s PDC range includes portable terminals in different sizes: pens, microterminals, hand held PCs and radio scanners for automatic data collection in theretail, office automation, logistics, services and industrial sectors. Optic pen terminals include memory pens with integrated optic scanner, as wellas portable and fully programmable pen terminals with integrated optic scanner.These latter are equipped with wide and easy-to-read display and are available inbatch and license-free radio-frequency versions for distances up to 50 m.

Micro terminals consist of pocket micro terminals with integrated laser reader.They are available in batch and wireless versions, with RF communications at 433 MHz, license-free (ETSI regulations300-220).Among the radio scanners is Formula 720, a portable wireless laser scanner with RF communication in a range from 15 to20 meters.

Finally, the Formula 8500 is Datalogic’s top-of-the-range laser hand-held PC, the only palm PC on the market to use a486 platform and, with integrated laser scanner, to weigh in at just over 300 grams. It is available in both batch and radio-frequency versions (license-free Spread Spectrum at 2.4 GHz).

Datalogic also offers a series of software products for simplifying the entire process, from development to integration.

FUSE 27436 Rev. 1 15.02.00 6

4. Company markets and competitive position at the start of the AEDatalogic, in the three main product lines shows a different market penetration in Europe and in the world:

HHD: CCD readers: one of the major players in EuropeLaser readers: a minor player in Europe, however with growing market share

USS: market leader in Europeone of the most important players in the world

PDC: Portable terminals: an important player in Italy, a secondary player in Europe showing however high growthrates thanks to the acquisition of a company - ID WARE - specialised in this area.

The project we have developed can have a beneficial impact on:

HHD products: CCD readerPDC products: portable terminals with scanning engines based on CCD technologyUSS products: low cost fixed position readers

To be noticed that CMOS linear sensors are quite new devices in barcode application field.Hand Held Barcode readers using linear sensor as light detection device (arranged as array of pixels) and using atechnology different from laser, are based on CCD technology. And at present no Datalogic competitors are using theCMOS linear sensor approach - larger competitors are using CCD plus ASIC technology; smaller competitors are usingCCD sensors plus discrete components.

Fig. 3 European market growth of CCD readers

Focusing on Europe, the main market for Datalogic products, and in particular on CCD readers, which is the product linemore interested in this project, we point out the following trends is shown in Fig. 3.The European market of the hand held bar-code readers is a growing market, at compound rate around 15% per year.The quantities are strongly growing while the medium price is linearly decreasing. Observing the market data relative toCCD readers in the last 6 years (Fig. 3) it is possible to notice that the total invoice of Datalogic has been growing at alower rate than the market one, so that the percentage of the market owned by Datalogic has progressively lowered invalue.This is due to the fact that the medium price of our products is higher than the medium price of the products available onthe market.

European Market Invoice in MEURO

0

20

40

60

80

Competitors

Datalogic

1995 1996 1997 1998

FUSE 27436 Rev. 1 15.02.00 7

Fig. 4 Average price of an Hand Held reader

The reasons of this situation are due to the fact that we have two kind of competitors. On one side we have two bigcompetitors (Welch Allyn USA, and Nippondenso Japan) that produce very large quantities and are the leaders in theirnational markets. This allows them to hold a great contractual sway over the suppliers of basic components andconsequently to enjoy a lower cost of the final product. On the other side we also have many small competitors mainlyfrom the Far East (Taiwan, Korea and so on) and they can take advantage from a lower cost of the labour in that area.Though the quality of their product is not as good as ours, the lower price allows them to get a consistent percentage ofthe market.It is very important to point out that UBI, the only European competitor in a situation similar to ours, has been acquiredby Western Atlas, a very large American holding company.The following figure shows the share of the European market for CCD readers in 1998.

13%

31%

12%

17%

27%

Nippon Denso

Datalogic

UBI

Welch Allyn

Others

Fig. 5 CCD readers European market share in 1998

Until 1995 Datalogic has sold its products both to end users and distributors. Owing to continuous decrease of productprices and raising of the costs of sales Datalogic has decided to create an indirect sales network based on distributors. Afirst result of this approach is already visible in the medium price reduction of 1996 that allowed Datalogic to maintain thesame market share held in 1995. It appears that the average sale price for distributors must be lower than the price for anend user so that the direct result for Datalogic is a reduction of the profit for each device sold.To be competitive in this area, considering the Far East competition and the need to maintain an adequate profit it ismandatory to reduce the direct cost of the product.In the last year, Datalogic developed a new class of reader, the DLC7070-M CCD CCD-Gun, announced on June 1998(see chapter 16) that for the first time applied the CCD technology on Long Distance reading. During the AE, FU realisedas the new technology features fitted the requirements for this new class of reader. This gave the possibility to apply the

Medium price in EURO

200210220230240250260270280290300310

1993 1994 1995 1996 1997 1998

Datalogic

Competitors

FUSE 27436 Rev. 1 15.02.00 8

AE results on this CCD-Gun rather than on the Entry Level CCD Reader (DLC6065) taking advantage by higher pricepositioning.The CCD Gun sales figures for the past two years and expected for 2000 are as follows:

1998(*) 1999 2000CCD Gun (current product)Turnover (KEURO) 2150 4869 5433Average price (EURO) 215 204 194Number of products sold 10000 24000 28000

(*): Six months only

The Datalogic DLC7070-M CCD GUN™ opened new horizons in scanner technology. The main feature is very goodperformance at Instinctive reading distance 30mm through 180mm that means the most natural position reading a barcode. Anyway, thanks to the optical system and to a powerful signal processing system the depth of field is very goodboth at long distance (low cost laser like performance) and nearly contact (contact CCD like performance). The DLC7070-M, CCD GUN™, can read EAN13 codes with a mag. factor of 1 (resolution: 0.33 mm) from a maximum distance of 14 cm,and it can reach 34 cm on codes with a resolution of 1 mm.Although Datalogic can offers a very aggressive price, this one is the most important parameter to improve in order to bemore competitive on the market. As the technology innovation proposed with AE will allow a cost reduction, FU mayoffers a lower price in such a way to improve market share and then the profit.

The cost reduction expected at the start of the AE with this new technology was estimated in 5 EUROs each unitconsidering an actual cost for CCD + BiCMOS ASIC + circuitry of 13.5 EUROs and a cost for CMOS microsystemmounted with a COB (Chip On Board) or CSP (Chip Size Packaging) technology of 8.5 EUROs.

5. Product to be improved and its industrial sectorsAt present Datalogic uses CCD linear sensor in most of its low cost barcode reader:

• CCD touch readers (DLC6065/90-M, DL65/80), with different dimension of the "mouth" of the reader (65 or 80 mm)• CCD Long Range readers (DLC7070, CCD GUN™), for medium and long distance high performance• Low cost fix position scanner (TC2100),

The Smart CMOS linear sensor, result of the AE, has to be considered as scanning engine for many application with thesame functionality of a linear CCD. So, it is clear that the products to be improved is all the actual products based onlinear CCD technology.

The basic architecture for a CCD readers can be summarised as in the following block diagram:

P with integrated timer µ

ASIC Mixed Analog\Digital

IlluminatingSystem

Emitted Light

Barcode

Diffused Light

PhotoSensor

AGCAmplifier

SensorSignal

Digitizer

AmplifiedSignal

Sampler

DigitizedSignal

Decoder

NumericSequence

DecodedString

OutputInterface

OutputSignal

LED ARRAY

CCD Linear

Multi-InterfaceCCDDriver

ArrayModule

Fig. 6 Basic architecture for a CCD readers

An array of red LEDs is used to illuminate the code. The light diffused by the code is collected through an optical systemon a CCD linear sensor. The signal produced by the sensor is amplified using an automatic gain control system and the

FUSE 27436 Rev. 1 15.02.00 9

Amplified Signal is digitised. (This step is also often called "binarysation"). The Digitised Signal is a two level signal(high or low) that reproduces the image of the bar code in term of white and black elements. These functions arecurrently implemented in a BiCMOS ASIC with mixed Analog\Digital signals that is also used to control the CCD. Thedimension of the ASIC is about 27 mm2 in a 48 PLCC package.The width of each black or white element in the Digitised Signal is measured using a timer integrated in the µP, so aNumeric Sequence of data is produced and stored in the memory of the µP itself. The Numeric Sequence is used by adecoding algorithm running on the µP, to recognise the code symbols and to decode the information. Finally, the µPoutputs the Decoded String to the host device through an output interface.

The reference product for the AE using the CCD structure described above is DLC7070 (CCDGUN™) used in applications such as retail and office automation. It operates at up to 40 cm fromthe bar code and is based on the most innovative CCD technology, previously reserved forcontact reading, allowing it to read like a laser scanner over long distances, with equal or betterresults. With the objective of making the operator’s job easier, the DLC7070-M CCD GUN™ offersergonomic solutions designed to optimise handling and ease of use. The 100 scans/sec scan rateis perfectly combined with a powerful Datalogic decoding unit working at 25 MHz.. Connection toRS232, Wedge and Pen Emulation can be obtained thanks to the multi-standard interface mountedon a board, by simply changing the plug-in cables. From a technological point of view the customchip IHHC (Intelligent Hand-Held Controller) integrates all the discrete components normally used

in these devices. The innovative technology assures extreme reliability (the smaller is the number of components thelower is the statistical risk of failure).

Referring to the block diagram depicted in Fig. 6, follows a more detailed description of DLC7070.

Illuminating system. An double red LEDs array emitting at 660nm is used with cylindrical lenses to produce the brightpointing and illuminating light beam.

CCD sensor. The linear sensor is a 2048 pixels CCD. The focusing optic is a triplet with a focal length of 25 mm and arectangular diaphragm of 0.5 x 6.3 mm to obtain a high depth of field. (The wide side of the diaphragm is perpendicular tothe CCD pixel line).

AGC system. The AGC is composed by many different stages: an input stage adapted to the CCD type, a first pre-amplifier stage with a gain of 5; a 3rd order low pass filter with cut frequency variable in discrete step from of 112 KHz to9 KHz to adapt the system to different types of codes, the selection of the cut frequency is controlled by the µPdepending on the results of the decoding process; a high pass filter to remove the low frequency modulation whichaffects the input signal depending on the optical structure of the system; an Gain stage that produces an output signalof 3 Vpp amplitude. The gain amount is typically constant during each scan and is determined by the type of codeobserved.

Digitizer. The digitizer is mainly an edge detector but it cannot be merely implemented as a threshold system because itmust work with signal of different amplitude (due to the fact that the AGC system cannot remove amplitude modulationinside the code due for example to a de-focused condition) and duration (due to different resolution of the code).Datalogic owns the competencies for design different digitising circuits with optimal performances.

Microprocessor. The microprocessor is a Mitsubishi M37702 working at 25 MHz in single chip mode.

Multi-Interface. The output interface circuitry allows to set the device in different interface configurations, such as EIARS232, keyboard emulation (wedge) and pen emulation (wand).

FUSE 27436 Rev. 1 15.02.00 10

Fig. 7 DLC7070 CCD board assembly

The need of reducing costs led FU to consider the CMOS integrated solution as it was regarded cheaper than theASIC/CCD one.In addition the necessity of reducing reader size coped well with the possibility of contracting the area occupied by theASIC+CCD circuitry to the smaller surface required by a CMOS/switched capacitor device, which is able to embed inone-chip die the signal processing system, the sensor driving circuitry and the sensor itself.As a marginal consequence, the choice of a CMOS sensor along with the related necessity of reconsidering the wholedesign of the signal conditioning system gave us the possibility of embedding in a cheap way a certain amount ofsystem field configurability that had been neglected in the former ASIC project.From the performance and features point of view the existing product has a very good deep of field, wide readingdistance and short decoding time, never seen on the market. But the IHHC ASIC is not a configurable architecture, soyou cannot adjust the analog parameters, even if this feature would be essential to improve the performance in particularapplication field using poor quality or damaged barcode labels.

6. Description of the technical product improvementsThe step that the FU has introduced is the integration on the same component of the Photo Sensor and the electroniccircuitry necessary to process the signal. It is clear how this technology allows a consistent reduction of size and cost ofthe system. The architecture of the product improved can be summarised in the following scheme:

P with integrated timer µ

Opto-ASIC Mixed Analog\Digital

IlluminatingSystem

Emitted Light

Barcode

Diffused Light PhotoSensor

SignalProcessing

SensorSignal

Digitizer

AmplifiedSignal

Sampler

DigitizedSignal

Decoder

NumericSequence

DecodedString

OutputInterface

OutputSignal

LED ARRAY

CMOS Linear

Multi-Interface

Digital Unit(Driving & Control)

Array

Module

Circuit

Fig. 8 Architecture of the improved product

FUSE 27436 Rev. 1 15.02.00 11

The Opto-ASIC, result of the AE and known as BRAHMS, is based on a CMOS sensor and it consists of :• a linear array of 2048 photo diode pixels (2048x1)• a suited readout circuit• a signal processing circuit (SPC)• a digital unit (DU)

The image acquisition is carried out by the 2048 pixel linear array using active pixels (ASP active pixel sensor). The pixelprinciple is based on the integration of the photocurrent on the capacitance of the photodiode itself. The analog outputsignal from the pixel array is readout by correlated double sampling to suppress fixed pattern noise. The transfercharacteristic between incident irradiance and output signal is approximately linear.The CMOS sensor is provided with a built-in rolling snap electronic shutter driven by the DU that automatically set thesuitable integration time frame by frame.The SPC, based on Switched-Capacitor CMOS technology, has in charge to process the signal coming from the CMOSsensor, providing an output signal in a binary form suitable in barcode image decoding.The main tasks for Digital Unit (DU) are sensor driving, the interface to an external control device (usually amicrocontroller), the supervision of SPC activities during normal mode operations and the management of test functions.The interface to the external control is based on a reduced implementation of a 4-bit Microwire serial bus.The system clock run at 3.2MHz and it may be supplied to the device using a quartz crystal (or a ceramic resonator) or anexternal digital clock source.Two operating modes for the IC are supported, controlled and stand-alone.• In controlled operating mode the external controller (e.g microcontroller) accesses the internal registers via the serial

interface to change programming configuration of BRAHMS device.• In stand-alone operating mode the device itself loads the programming configuration (content of parameter

programming and control registers) from an external serial E2PROM at start-up, driving the serial interface.

The IC is provided with Programming and Control registers. The first ones are used for IC trimmering at application level;typically their values are programmed off-line, at the beginning of the normal operating mode (set-up phase). Thesecond ones hold the operating mode configuration; typically its content may be modified during image acquisition, forreal-time control of image acquisition and processing.The following figure shows the block diagram of the 26-pins OptoASIC.

SDO

CHANNEL

(Low-Pass)

df

senso filtoAGC

Automatic

sg

filto agco

Gain Control

FOCUS

f2,f1

ifo analogDIGITIZER analog video

mask

DIGITAL UNIT

scs

sck

sdi

sdo

spen

prs

tup

tdw

SPEN

SDI

SCK

SCS

XTALI XTALO

amsel [7:0]

senso

filtoagcoanalog

analog

pfopfo IMPROVEMENT

dfsgf2,f1

SCAN

mask

SHUTTER

senso

tup CONTROL

Vup

Vdw tdw

prs

VOLTAGE Vdw

Vup

REFERENCE

VDD1

GND1

ANALOG

amsel [7:0]

out

MUX

in0in1in2in3in4in5in6in7

senso

filto

agco

pfo

saenSAEN

RESET

SENSO

SENSOR

2048 PIXEL LINEAR SENSOR

SHIFT REGISTER

SHIFT REGISTER

BIASGENERATION

READOUTCIRCUIT

CLOCKGENERATION

AMOUT

IGND

FILTER

env

dp[2:0]

tsta1

scan flat

tsta1

tsta2

tsta1

tsta2

flat

3

8

SENSI

tsta2

tsta2

tsta3

th2,th1

th2,th1 noslp

tsta3tsta3

scan_out

noslp

2

VREF

IGND VTOPVREF

scan

scan

slpon

slponvgsh

vgsh

slpon

vgsh

slpon

vgsh

VTOP

env

env

flat

3.2MHz

2

video_outVIDEO

dp[2:0]

video_in

10clk_bus[9:0]

stsel

stres

stsel

stres

tres

tselextres_n

reset

tres

tsel

mainclk

mainclk reset

reset

resetreset

iscan

ELECTRONIC

SIGNAL PROCESSING CIRCUIT

VDD2

GND2

VDD3

GND3

VDD4

GND4

VDD5

GND5

VDD6

GND6

Fig. 9 Block Diagram of the Opto-ASIC (BRAHMS)

FUSE 27436 Rev. 1 15.02.00 12

The very small optical package of BRAHMS IC is made thanks to a very innovative packaging technique, the Chip SizePackaging that will be described in detail in chapter 15.In Fig. 10 the IC floorplan is shown. The resulting chip area used is about 62mm2 including 11.5mm2 seal ring arearequired for CSP.

seal ring

2.1mm

31.1mm

Sensor Line

1

Fig. 10 Opto-ASIC floorplan and dimension and picture

The bread-board PCB that has been developed to test the microsystem’s performance is shown in Fig. 10bis:

Fig. 10bis Bread-board including new microsystem

Advantages allowed by the new technology:

• Cost reduction. It is to point out as this operation acts on two of the three high cost components ofthe system: IHHC and CCD (the other expensive component is the microprocessor). The costsobtained with this solution is competitive if compared to other solutions using components alreadyavailable on the market and providing the same functionality and performance.

• One of the most important achieved results has been size reduction that is a key factor in many hand heldapplication fields. Comparing the old architecture based on CCD+IHHC devices to the Smart CMOS Sensor result ofthe AE, it’s immediately visible the reduction of size and component number, getting the same or better functionalityin a single chip solution, although the size reduction is less important for this application. It is very important for theother planned applications, including supply of OEM scanning engine modules.

FUSE 27436 Rev. 1 15.02.00 13

Q Q

R

IHHC - BiCMOS custom IC

R

R

R

Circuitry

IHHC

C

R

R

R

R

R

R

OpAmp

HC4066

HC132CCD device (DIL 20pin) R

R

R

R

R

C

C

C

C

C

C

C

C

C

C

C

C

C

C

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

D D

BRAHMS OptoASIC

Fig. 11 number of component and size reduction achieved

• Improved performance (deep of field with EAN standard codes and normal operative condition increased up to 15%)thanks to the new analogue Signal Processing approach and analogue parameter configurability:- AGC (Automatic Gain Control) block that suppress the continuos component of the input signal and equalisesthe analogue output signals to a defined range.- Focus Improvement block that improve analogue signal focusing in order to optimise following digitizer’sperformance on out-of-focus images. The re-focusing level can be adjusted.- Digitizer block that has been provided of analogue programmable parameters for threshold, slope and hysteresis.The parameters will be adjusted thanks to different capacitor-sizes in the SC-circuit. The correct capacitor-size will beselected with programmable switches driven by the Digital Unit that will provide digital signals. This parameterconfigurability assures good performance and flexibility over a wide range of operating conditions. This newapproach using a “configurable built-in SPC” may takes advantage with respect to the current CCD readerarchitecture.

• low power consumption and better EMC allowed by low clock speed of the system.(3.2MHz)• better reliability of the system compared to the old one thanks to the single chip solution• reduction of component number, decreased testing and manufacturing time make additional cost saving possible.

How it can be seen the project results was been very good and the BRAHMS device, together with a suitable small sizeoptical module under development, could be used with manifold benefits as scan engine in most innovative Datalogic'sproducts.

7. Choices and rationale for the technologies, tools and methodologiesSome alternative architectures have been evaluated (and some of them also realised) before deciding to move toward themicrosystem technology.

The evolution of the DL65/80 has followed these steps:CCD + discrete componentsCCD + ASIC

Both of them have been implemented in FU’s products in different periods and this is the state of the art condition fromwhich we start. Some CMOS sensors already exist (some are also commercially available e.g. from C-Cam Technologies)but they cannot be competitive with CCD because of the very different volume of the market.FU has also evaluated the possibility to integrate a CCD sensor with electronic circuitry. In this case the problem is thatthe CCD is a technology not so widespread over the world and only few factories are capable of producing it and theyare not generally interested in realising custom devices. In any case the resulting component will not probably be sogood value. Nippondenso, a Japanese competitor that is a subsidiary company of the Toshiba group, with the obviousadvantage of having the CCD technology 'near the door', has tried this way in the past but, in a very short time, it hascome back to a standard CCD component.FU considered as hardly reachable further improvements by using standard components and that the only way toproceed was to make a custom microsystem using CMOS technology.

FUSE 27436 Rev. 1 15.02.00 14

Another possibility has been evaluated: the integration of the µP on chip too, but typically the core of a µP whenavailable as a standard cell has a squared area, while the sensor should be long and narrow, having a situation as shownin the figure with a lot of unused area.

SENSOR STANDARD CELL

UNUSED AREA

Fig. 12 Dimensional problem using linear sensor and standard cells

To be a really convenient solution (few external components) also EPROM and RAM should be integrated on the chip.This solution didn’t seem to be suitable for the AE if you consider problems of a lower production yield as well.

CCD+discretecomponents

CCD+ASIC CMOS Sensor andSPC in a single chip

Cost per unit Medium Medium LowerCompactness None High Very HighReability Medium Good Very GoodRisk Low High HighTime to market Low High High

As a conclusion FU decided that the best choice is a system integrating the sensor and the electronic processing circuitinterfaced with a standard µP in a single chip masked version, because the sensor unit has its own distinctcharacteristics from the processing silicon. This qualifies as a microsystem. There are also packaging difficulties as aresult of optical quality.

The choice of Fraunhofer IMS as subcontractor is based on the recognised experience in the design and fabrication ofCMOS image sensors and analogue and digital CMOS circuits. They have already developed and successfully fabricatedmany different CMOS imagers using passive and active photodiode pixels and photo-MOSFETs as sensing elements.For our application a photodiode pixel with charge readout was chosen be used, which ensures high photosensitivity,low temporal and fixed pattern noise, good linearity, and high signal-to-noise ratio. In addition, there is a strongbackground know-how in the area of sensor modelling and analysis and in low-noise CMOS circuit design. FraunhoferIMS offers all in one hand: system development, sensor and electronics design, IC prototype fabrication and testing.They will also be able to do the series production of the proposed sensor IC. The sensor will be fabricated in a 1µmCMOS process.CADENCE FRAMEWORK II design tool were chosen to be used, along with MATLAB 5.2.CADENCE was chosen on recommendation of IMS and especially suitable because FU already had a limited knowledgeof the package.MATLAB 5.2 was selected by the FU because it is a standard package for this work allowing a high level description andsimulation of the functionality of the system.

8. Expertise and experience in microelectronics of the company and the staff allocated to the projectDatalogic’s technical staff has been designing electronic device for over 25 years. The company expertise refers to manydesign area and may be summarised as follows:Hardware design: Analog design, Microprocessor based systems using standard or custom components, FPGA, ASICdesign. Software design: Embedded software using real-time multi-tasking operating systems.Optical design: Usage of LEDs, Lasers, photo diodes and CCD, Optical systems using spherical, and a-spherical lensesin glass or plastic material, Polygonal rotors with mirrors, Coating.

Though the number of electronic engineers working in Datalogic is not small, the technical staff works mainly withtraditional design using SMT and discrete electronic components mounted on printed circuit boards.If we consider the number of engineers working on ASIC developing it is instead really small. Until now, the experienceon ASIC of Datalogic's engineers has been mainly for FPGA. In 1994-1995 the technical leader of the AE was involved inIHHC project (Intelligent Hand Held Controller), that was the develop of a BiCMOS monolithic integrated circuits usingdigital and analog standard cells. The IC, currently used in Datalogic CCD readers, implements an analog channel that

FUSE 27436 Rev. 1 15.02.00 15

converts the electrical signal coming from the CCD (Charge Coupled Device) in a binary form, a digital controller thatdrives the CCD device and a DC-DC converter (booster) for analog supply.

Personnel involved in the AE:

AE role Company role TasksResponsible for the project HHD division director Management and AE supervisorProject leader Analog designer Co-ordination of all the activities and design of the SPCProject assistant Digital ASIC designer Design of the Digital UnitProject assistant Optical designer Sensor technical specificationProject assistant Product manager Marketing and economic impact of the AEProject supervisor Senior designer Technical supervisors of the AE

9. Workplan and rationaleThe following chart shows the original project plan composed by six Workpackages:

Fig. 13 Original workplan

Objectives and detailed descriptions for each task have been planned as follows:

Workpackage 1 Management

Task 1.1 Technical managementDescription: To guarantee the respect of time scheduling and expected results of the AE. One person Datalogic was

in charge for the technical management. IMS gave adequate support. The Datalogic technical managerhad the responsibility to follow the development of the AE and to take decisions about anymodification brought to the workplan or to the technical results with the scope to minimise the effectof problems arising within the duration of the AE itself.

Duration: The entire period of the AEDeliverables: Monthly and Quarterly reports on the progress of the AE (restricted). Final Report (public).

Task 1.2 Economic managementDescription: To prepare or collect all the material relative to the documentation of the costs of the Application

Experiment. IMS supplied an adequate interface and support for the documentation of its own costs.The TTN provided a supervision of the documentation produced.

Duration: The entire period of the experiment.Deliverables: Quarterly report on the costs of the AE (restricted).

Task 1.3 Project Supervision

FUSE 27436 Rev. 1 15.02.00 16

Description: To control that the AE is effectively carried on in the declared time and costs. The TTN provided asupervision of the documentation produced and of the intermediate results.

Duration: The entire period of the experiment.

Workpackage 2 Training

Task 2.1 On job training on circuit designDescription: To provide the know-how necessary to carry out the circuit design with IMS’s technology. IMS

provided on job training to Datalogic designers.Duration: 20 weeks.

Task 2.2 On job training on layout designDescription: The integration of the sensor with the signal processing circuit requires a custom design of the layout.

IMS gave to Datalogic designers information needed to follow the process. The job was handled by IMS.IMS expert helped Datalogic designers

Duration: 20 weeks.

Workpackage 3 Design

Task 3.1 Specification and architecture definitionDescription: According to both the technology capabilities and the application requirement, IMS and Datalogic

define the specification of the microsystem. Special attention was given to the definition of theinterface between the sensor and the signal processing circuit.

Duration: 8 weeks.Deliverables: Detailed Specification (confidential).Milestone: Specification complete.

Task 3.2 Design of sensor and test methodsDescription: Design and simulation of the sensor and definition of test methods according to circuit structure.

Detailed design of the sensor is responsibility of IMS; Datalogic supported adequate interface.Duration: 21 weeks.Deliverables: Detailed design of the optical sensor (confidential).

Task 3.3 Design of the signal processing circuit and test methodsDescription: Design and simulation of the signal processing circuit and the definition of test methods according to

circuit structure. Detailed design of the processing circuit is responsibility of Datalogic. IMS supportedadequate interface.

Duration: 21 weeks.Deliverables: Detailed design of the signal processing circuit (confidential).

Task 3.4 Layout of sensor and circuit and final simulationDescription: Layout of the final microsystem and final simulation performed as functionality verification. Common

responsibility of IMS and Datalogic.Duration: 9 weeks.Deliverables: Microsystem design (confidential).Milestone: Design completed.

Workpackage 4 Fabrication

Task 4.1 Mask fabricationDescription: Fabrication by IMS of the masks for wafer processing.Duration: 2 weeks.Deliverables: Masks (confidential).

Task 4.2 Wafer processingDescription: Using a multi-project wafer capability 20 prototypes of the chip are produced by IMS foundry.Duration: 10 weeks.Deliverables: IC (confidential).

Task 4.3 Microsystem packagingDescription: After the completion of on-wafer test (5.4), the microsystem is housed into a suitable package. The

IMS provided a package for the microsystem suitable for prototype test with no extra cost.Duration: 1 week.Deliverables: Packaged microsystem (confidential).Milestone: Microsystem is available.

Workpackage 5 Test

Task 5.1 Test set-up for wafer test

FUSE 27436 Rev. 1 15.02.00 17

Description: During wafer fabrication, wafer test is set-up by IMS.Duration: 2 weeks.Deliverables: Wafer test plan (confidential).

Task 5.2 Test set-up for sensor testDescription: Experimental environment for sensor test is set-up by IMS.Duration: 2 weeks.Deliverables: Sensor test plan (confidential).

Task 5.3 Test set-up for signal processing circuit testDescription: Experimental environment for signal processing circuit test is set-up by DatalogicDuration: 2 weeks.Deliverables: Signal processing circuit test plan (confidential).

Task 5.4 On-wafer testDescription: Post-fabrication wafer test is performed at IMS’s lab.Duration: 2 weeks.Deliverables: Test report on on-wafer test (restricted).

Task 5.5 Sensor characterizationDescription: Sensor performance and functionality are is characterized at IMS’s lab.Duration: 4 weeks.Deliverables: Test report on sensor quality (restricted).Milestone: Microsystem tested.

Task 5.6 Signal processing circuit characterizationDescription: Signal processing circuit performance and functionality are characterized by Datalogic.Duration: 4 weeks.Deliverables: Test report on signal processing circuit quality (restricted).Milestone: Microsystem tested.

Task 5.7 Microsystem integration into the product prototypeDescription: The tested microsystem is integrated by Datalogic in a working bar-code reader prototype based on a

modified existing product.Duration: 2 weeks.Deliverables: Modified Product using the microsystem (private).

Task 5.8 Product prototype functionality testDescription: The functional performance of a bar code reader prototype equiped with the microsystem is tested using

standard methodologies used for bar-code readers characterisation.Duration: 2 weeks.Deliverables: Report on the performance of the product integrating the microsystem (resctricted).Milestone: Product prototype tested.

Workpackage 6 Dissemination of Results

Task 6.1 Paper writingDescription: To write a paper for publication on a magazine.Duration: 2 weeks.Deliverables: Paper (public).

Task 6.2 Preparation of Dissemination MaterialDescription: To prepare all the material for dissemination purposes (e.g. brochures to be used during exhibitions). In

order to help the TTN to promote awareness of the benefits of advanced microelectronic technologies,Datalogic also provided illustrative materials right for a good pro-active work information on currentand improved product line and application experiment experience. This task has been spread along thewhole duration of the project.

Duration: The entire duration of the projectDeliverables: Dissemination material (public):a brochure on product improvement related with the AE; project

description on Datalogic’s Web-page; a poster for stand in exhibitions; a free microsystem sampleoffered to TTN.

Milestone: Dissemination material available.

The following table shown planned efforts and costs for each workpackage:

ProjectFUSE 27436 WP1

ManagementWP2

TrainingWP3

DesignWP4

FabricationWP5

TestingWP6

Dissemination TOTAL

FUSE 27436 Rev. 1 15.02.00 18

Effort

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kEURO

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P.Days

COST

kEURO

Effort

P.Days

COST

kEURO

Effort

P.Days

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kEURO

Effort

P.Days

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kEURO

Effort

P.Days

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kEURO

Effort

P.Days

COST

kEURO

PlannedFinancialEffort

FU Personnel 24 6 40 10 100 25 60 15 18 4.5 242 60.5

Travel 1 2.5 3.5

Subcontractor 24 12 36 18 --- 16 20 10 80 56Total 24 6 64 23 136 45.5 16 80 25 18 4.5 322 120

Risk analysis and contingency planThe risk analysis and contingency plan identified by FU at the beginning of the AE were as follows:• Datalogic would have take the direct responsibility for the technical management in order to have continuos and

direct control of the AE progress and results. To assure sufficient know-how to carry out the sensor and circuitdesign additional training would have been provided if necessary.

• In case of delay due to complexity under-estimation a back-up designer would have been involved in the job.Workplan would have been modified trying to maintain milestones.

• During the design of the circuit, precautions should have been taken to allow the possibility of off-chip signalprocessing on intermediate nodes of the processing chain, to allow signal restoration on external simple low-noisecircuits in case of insufficient performance (e.g. S/N-ratio degradation due to technology limitations)

• In case of difficulty in optimising the layout the AE would continue with a not optimised layout. Datalogic would re-design a new layout for production.

• Possible delays in die fabrication may be partially compensated by scheduling optimisation allowed by the fact thatfabrication is made by IMS itself, not by a third-party foundry.

• In case of design bugs or functionality not satisfying an analysis of the problem, evaluating if external patchesshould solve the problem, would have been done. Datalogic might decide to re-design and repeat the prototypefabrication.

• A reasonable performance degradation of the microsystem compared to existing products is acceptable, and can bereduced by subsequent software processing. In order to reduce this risk some tests on already existing CMOSsensors developed by IMS will be done during the design phase and results will be used to optimise sensor design.

• If the budget is out of bound Datalogic would have supported additional costs.

FUSE 27436 Rev. 1 15.02.00 19

Fig. 14 Actual workplan

Difference between original and actual workplanThe actual workplan shows some differences with respect to the original one.The total duration of the project was 5 months more than expected. Reasons because some task last longer are presentedand justified as follows:

• Finding the right way to specify and designThe FU had a previous experience with designing in BiCMOS only, which was inappropriate to the needs of thetechnology required. This was the reason for an unanticipated delay at the beginning of the project. The Company hadto find a way to specify and design and interact with subcontractor.This means a new way of defining certain functions and circuits. In particular FU has abandoned the initial idea ofperforming the design of signal processing circuitry up to schematic and layout level owing to the difficulty of quicklylearning a job that IMS staff was already able to do. So it has been settled that FU design job should have beenperformed in term of discrete time signal processing using suitable math software tools in order to get the processingcircuitry structured as blocks described in the form of discrete time algorithms with functions available in the SCtechnology.

The design job was carried out as follows:• IMS and Datalogic defined the specification of the microsystem;• IMS designed the sensor, clock generator and readout buffer;• Datalogic designed (Matlab functional description) the SPC; IMS carried out the SC-design (Schematic entry

and simulation) for SPC designed by Datalogic;• Datalogic designed the Digital Unit on Cadence environment, providing IMS with a Verilog description for

the final synthesis of the circuit;• IMS carried out the lay-out design and verifications;

• Used area.The use of a 1um CMOS technology instead of the 2um BiCMOS technology adopted within the previous FU-developedASIC, allowed FU to expect a very good usage of the available area (40mm2) for extra functionality in addition to theconventional signal processing methods. Instead, during the training on CMOS Switched-Capacitor technology FUfound out that this “initial advantage” wasn’t true because of the different behaviours of CMOS Switched-Capacitorand BiCMOS devices.A more precise evaluation pointed out as the first assessment of total die chip-area requirement for FU application wasout of limits for a cheap Opto-ASIC (the cost of the Opto-ASIC device may be considered roughly as a linear function ofdie chip-area).

• SpecificationDuring the first period of AE both FU and Subcontractor realised that a large part of the planned design activity, inparticular about analog processing blocks, had to be considered as a specification from the FU side because of theapproach exchanging detailed specifications as discrete-time algorithms with function suitable in the SC technology.Because of unexpected design steps necessary to trade off functionality vs. chip area, detailed definitions andspecifications for analog and digital part took a period wider than expected. Keeping in mind the advantage for FU infinding an optimised and cheap Opto-ASIC device, each block definition involved several unexpected steps of revisionand simplification, as the constrains on chip-area usage were stronger than those FU had thought.

• DesignTo find an optimised solutions saving chip area but keeping the essential device functionality, many additional designsteps have been required. On the other hand subcontractor seems to have underestimated complexity and developmenttime of the device.

• LayoutFU evaluated a new approach in packaging technique as suitable for the final device: CSP (Chip Size Packaging) is awafer level packaging process based on an extension of semiconductor type manufacturing processes yielding thethinnest packages on the market. In order to be compatible with CSP many design rules required for this new approach inIC packaging have been considered during the layout phase. This took extra work in Subcontractor’s layout task

FUSE 27436 Rev. 1 15.02.00 20

considering that this packaging technique was quite new for IMS and required a lot of information exchange betweenIMS and CSP manufacturer.

Description of knowledge transfer processIn addition to the daily interactive activity during the specification and design jobs, IMS delivered to FU some technicalmaterial on CMOS sensor, and Switched capacitor circuits. So, on job training to Datalogic’s designers, such as technicalmeeting and documentation exchanges, has been provided by IMS staff. In the course of meetings held in Duisburg c/oIMS, subjects about CMOS sensors, Switched-Capacitor circuits, design and test methodology have been presented bythe subcontractor to Datalogic’s designers, analysing in particular some aspects on Signal to Noise Ratio (SNR) andsensors.The following table shown actual efforts and costs for each workpackage:

ProjectFUSE 27436 WP1

ManagementWP2

TrainingWP3

DesignWP4

FabricationWP5

TestingWP6

Dissemination TOTAL

Effort

P.Days

COST

kEURO

Effort

P.Days

COST

kEURO

Effort

P.Days

COST

kEURO

Effort

P.Days

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kEURO

Effort

P.Days

COST

kEURO

Effort

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kEURO

Effort

P.Days

COST

kEURO

ActualFinancialEffort

FU Personnel 42 12 55 11 337 56 35 7 18 4 487 90

Travel 2 2.1 3.8 7.9Subcontractor 24 12 36 18 --- 16 20 10 80 56Total 42 14 79 25.1 373 77.8 16 55 17 18 4 567 153.

9

10. Subcontractor information

Requirement and selection criteriaThe subcontractor selection was made on the basis of the following requirements:

• good experience in CMOS image sensor• accessibility and geographic closeness to Italy, that allows reduced transfer costs .• availability of MPW facility to reduce the prototyping costs;• interest on production volume with reduced quantities per years

FU chooe the Fraunhofer-Gesellschaft that is a non-profit organisation in Germany that supports applied research anddevelopment in various main technical areas. R&D is carried out in 47 institutes distributed over the country.Fraunhofer IMS offers all in one hand: system development, sensor and electronic design, IC prototype fabrication andtesting. The research in this project was performed in the Fraunhofer-Institut für mikroelektronische Schaltungen und Systeme(Fraunhofer IMS), Duisburg. Fraunhofer IMS performs applied research for industrial and non-industrial customers in the area of microelectronicsdesign, fabrication, and test in all areas of integrated circuits. Fraunhofer IMS has 10 years experience in contract R&D as well as in fabrication of CMOS image sensors and theaccompanying analog and digital signal and image processing. The CMOS imaging activities are headed by Prof.Hosticka and supported by a staff of approx. 30 scientists and engineers including several Ph. D. students. Several 2-D and 1-D image sensors and cameras (up to 400x300 pixel and up to 2048x1 pixels, respectively) have beendeveloped and fabricated, mainly for industrial customers. In the area of low noise CMOS analog sensor readout, which is very important for sensor performance, Fraunhofer IMShas also a strong competence and long term experience.

FUSE 27436 Rev. 1 15.02.00 21

The institute has a 1 micron CMOS process line of industrial standard and is ISO 9001 certified. Fraunhofer IMS is able tofabricate CMOS ICs and microsystems in small and medium volumes.

Service ProvidedThe functions of IMS have been:• supporting Datalogic to define the specification of the Sensor;• supporting Datalogic during the Design (functional description) of the SPC and Digital Unit;• carrying out the SC-Design (Schematic entry and simulation) for SPC defined by FU;• carrying out the lay-out design and verifications;• carrying out masks realization, wafer processing and samples fabrication of the ASIC.• Co-operating with Datalogic defining and carrying on the test procedure and characterisation of the microsystem

Operative InterfaceIn consideration of the geographic distance, FU joined the Subcontractor in Duisburg four times (three or four daysevery time) in occasion of technical review meeting. The daily activities (exchanging specifications, design data andsimulation results) have been carried on using e-mail, phone and fax services.FU used Matlab 5.2 Software for SPC specification. For Digital Unit design FU worked on Cadence environment,providing IMS with a Verilog description for the final synthesis of the circuit.

Contract and complianceA special agreement was made with Subcontractor. Datalogic entrusts the Subcontractor Fraunhofer IMS with thedevelopment of design and the fabrication of the related prototype. The results generated by IMS during the project, andrelated to the field of the project, will be owned by IMS, at the condition that Datalogic will be free to use and exploitthem. IMS will grant to Datalogic an exclusive, free of charge and irrevocable license on IPR. Datalogic will grant to IMS a non-exclusive, free of charge and irrevocable license on IPR only limited to IMS scientific work.

11. Barriers

Technical barriersPrior the execution of this AE, the experience of Datalogic's engineers had been confined to the design of ASIC usingstandard cells. The design of a microsystem using a custom optical sensor is quite different and more complex andcannot be considered as "just another standard cell". For ASIC based on Standard Cell the designer works at "logicallevel" connecting predefined building blocks in order to obtain the desired function. The proposed microsystem requiresinstead a significant step ahead in the technical skills both of the Datalogic’s and Subcontractor’s designers.The optical sensor must be fully designed because, though Subcontractor may have already gained experience in thedesign of optical sensors, it is clear that it is not possible to use an already available sensor. Also the interface betweenthe sensor and the processing circuit must be fully customised and the circuit layout carefully designed both to fit thecustom components and minimise the used area.

Managerial barriersThese activities will not only require a knowledge of the new technology deeper than that actually owned, but alsomanagerial skills to be able to successfully carry on the project involving an high-technology partner. Thesemanagement capabilities must be acquired during the project and are a key factor for the success of the experiment.

Economical barriersAnother important barrier is related to the time to market for the target product using the new technology. Sincemicroelectronic technology changes very quickly while a custom design of an ASIC requires long development time,there is the risk of realising something that will be inadequate if compared to the future requirements of the barcodemarket maybe induced by competitor products.What can be defined as psychological barrier is that the management of Datalogic perceives this project not only ashaving high costs and long development time but also as characterised by an high risk of failure due to the innovativeapproach and technology, and microsystem complexity.

12. Steps taken to overcome the barriers and arrive at an improved product or process

The TTN provided important assistance throughout the project, specifically advice on problem with time-to-market byconsidering how the new technology could impact on the whole spectrum of the Company products and secondly,

FUSE 27436 Rev. 1 15.02.00 22

steering the Company to a successful subcontractor choice and continuously monitoring progress between FU andsubcontractor.

Technical barriersIMS experience in design and fabrication of CMOS image sensors and analog and digital CMOS circuits, helps FU toovercome perception of risk associated with new microelectronic technology. As the technology and designmethodology were new, on job training to Datalogic’s designers, such as technical meeting and documentationexchanges, has been provided by IMS staff. In the course of meetings held in Duisburg c/o IMS, subjects about CMOSsensors, Switched-Capacitor circuits, design and test methodology have been presented by the subcontractor toDatalogic’s designers, analysing in particular some aspects on Signal to Noise Ratio (SNR) and sensor.

Managerial barriers The Fraunhofer IMS experience in contract R&D as well as in fabrication of CMOS image sensors, in addition to TTNassistance for project planning, helped the FU to overcome the perception of risk related to managerial aspect.To meet FU’s skill and SW tool requirements to design signal processing circuits, a suitable design method was set up:FU design job was performed in term of discrete time functional blocks (suitable in the SC technology) using suitablemath software tools (Matlab) while all the problems related to schematics, "physical level" design, and layout weremanaged by IMS staff.

Economical barriersFraunhofer IMS offers all in one hand: system development, sensor and electronic design, IC prototype fabrication andtesting. In addition Fraunhofer IMS is able to fabricate CMOS ICs and microsystems in small and medium volumes formass production of the proposed sensor IC. This helps the customers to take the first step into a new technology withreduced financial risks.

13. Knowledge and experience acquiredThrough FU wasn’t new in the developing of ASICs the AE has been a really instructive experience because of the newtechnology used and the targets achieved. The challenge was both from the technical and managerial point of view andthe results and knowledge acquired may be considered positive.

From the collaboration with Fraunhofer IMS, that has strong competence and years experience in the area of CMOSimage sensors, low noise analogue CMOS sensor readout, signal and image processing, FU acquired important know-how on innovative CMOS sensor, noise issue, and SC circuits. This is an important knowledge achieved as CMOSsensor with built-in circuits seem to be the device of the future in the barcode reading application field, havinginteresting features (low cost, flexibility, vastly increased functionality).Defining the analogue signal processing circuits, FU was forced to describe it as discrete-time functional blocks suitablein the SC technology implementation. This new approach helps FU in defining a mathematical model of the system,finding additional functionality and exploring the behaviours of the processing chain from a new point of view. TheBRAHMS signal processing circuit is now described as Matlab functions, and ready to be simulated, analysed andreadapted for future applications.The new design approach of math modelling for SPC is illustrated in the diagram below:

FUSE 27436 Rev. 1 15.02.00 23

Moreover, exploring the packaging issue FU acquired a lot of knowledge and experience on different packagingtechnique:

• COB (Chip On Board), bonding the IC on a ceramic substrate or others suitable material with transparent glob top,covering the silicon die surface, as protection for the sensitive area.

• CSP (Chip Size Packaging) which is a packaging process based on an extension of the standard process forsemiconductor manufacturing. This is a really innovative and cheaper way to package devices yielding the thinnestpackages on the market (die-size).

In order to be in the lead in high tech application field like automatic identification Datalogic, that is a growing company,knows as the co-operation with external company and to have a good command of the new technologies is a key factorof success. In this background the AE carried out exploring a new technology with the support of qualified externalpartners fits exactly this basic paradigm.

14. Lessons LearnedOne of the most difficult task encountered at the start up of the AE was not only to define the specification but whoshould have define them and what was the operative approach carrying out the specification and design jobs.Thus, a very important effort for this managerial scope has be done by the FUs at the start of the AE defining exactly theactivities that the Subcontractor had to carry out, evaluating available tools, skills and competence in relation to thetechnical and temporal goal of the AE.

During the training on CMOS Switched-Capacitor technology FU found out that the initial area usage estimation, basedon the previous ASIC experience, was far from the actual requirements because of the different behaviours of CMOSSwitched-Capacitor and BiCMOS devices. Developing ASIC circuit you have to pay attention to chip area estimationbecause this parameter strongly impacts on the cost of the final device and on the design time therefore you have to findthe solution with the right compromise between cost and functionality.In order to be compatible with CSP packaging technique many additional design rules have been considered during thelayout phase. This took extra work in Subcontractor’s layout task considering that this approach was quite new for IMS.Developing custom device, FUs has to consider the packaging an issue do not undervalue both for technical and costsconstrains. To be noticed that some kind of package would cost as much as the IC itself.The results achieved in term of performance and features of the microsystem is quite good even if, as mentioned above,the cost of the final device is a little bit higher than expected because of extra-chip area and additional packaging cost. Inaddition the market scenario was changing more rapidly than expected with decreasing price while the AE was in

FUSE 27436 Rev. 1 15.02.00 24

process. Anyway, BRAHMS sensor and its Scanning Module will be the new technology for the industrialisation of newproducts. The target is a new class of reader, the CCD-Gun having distance reading features, instead of the entry Leveltouch reader. Moreover, thanks to the general purpose features of the device, new application field (e.g. OEMapplication) may exploit profitably the results of this AE.

Although risk analysis and contingency plan were identified by FU at the beginning of the AE, the activities got somedelay due basically to the complexity of the system and the underestimation of some issues.Working with external partners, FU learned that to respect the time schedule was not so easy as in case of all therequired resources for the project available inside the company. The delay recovering was really difficult, sometimeimpossible, since the Subcontractor was the main responsible for certain jobs like layout and wafer processing and it wasunable to apply more resources working on AE.

A key factor of success working with external partners is the good quality of the documentation exchangingspecification and design data between the parties. The management job may suffer a lots of inefficient communicationskill. To spend time for producing good documentation is really helpful and may avoid extra work due tomisunderstanding.Finally, preparing all the material for dissemination purposes has been a hard work but a quite formative experience. Withthe helpful and really appreciated support of CESVIT, FU collected a lot of illustrative material suitable for internal andexternal promotion of the new technology as well.

15. Resulting product or process, its industrialisation and internal replicationThe OptoASIC result of the AE, in addition to include in a single chip the image capture sensor and the signalprocessing circuit, has the important feature of a very small size. This fits the initial requirements, defined at the start ofthe AE, in order to realise a small size optical module to be used as scanning engine suitable in many FU’s barcodereading application. This Scanning Module (SM), whose the preliminary arrangement is shown in Fig. 15, consists of:

- board with the OptoASIC and few electronics components- illuminating system (lens and LEDs)- lens and mirrors (receiving optical path)- plastic housing

OptoASIC

Fig. 15 Scanning Module assembly

The SM could be used as scanning engine in all the actual products based on linear CCD technology, and in innovativesmall size products as well, replacing the present state of the art for linear sensor, lens, illuminating system, and signalprocessing circuit.

Besides the improved performance allowed by the Smart CMOS Sensor on the side of receiving optical signal, theScanning Module, therefore the improved product, shows a very sharp light line thanks to the new illuminating system.

FUSE 27436 Rev. 1 15.02.00 25

The sharpness of the light line is a feature very appreciated by the final user since it acts as pointing system for barcodescanning. Respect to the current product the improvement is significant and gives high added value to the new product.

For the final application of the Smart CMOS linear sensor on Datalogic’s products some different packaging techniquehave been evaluated. As both cost and size of the device are key factors for its application the standard packagingprocess providing a plastic or ceramic DIL package (like for the CCDs device) didn’t seem to be suitable, considering thatthis kind of package would cost as much as the IC itself and would have the same dimension of a common CCD device.

In order to achieve low cost and reduced size a first hypothesis proposed by some packaging manufacturer was a ChipOn Board (COB) process to bond the IC on a ceramic substrate (or others suitable material) with transparent glob top,covering the silicon die surface, as protection for the sensitive area. The resulting device would have been suitable forsoldering to a Printed Circuit Board (PCB) by a regular SMT process.

A more innovative and cheaper way to package the Smart Sensor, that has been chosen by FU, is CSP (Chip SizePackaging) which is a packaging process based on an extension of the process for semiconductor manufacturing. Ityields completely packaged wafer-level processed devices employing thin film technology. CSP Opto package measuresfrom 300 to 700 microns in thickness, yielding the thinnest packages on the market. Wafer-level manufacturing, achieveseconomies of scale, flexibility. It also proves to be reliable, the ICs are encased securely in a solid die-size shell. Thepackage prevents silicon from being exposed and ensures excellent mechanical and environmental protection Compliantbumps provide on board reliability.

• Others interesting features of the wafer level packaging are the following:• Miniature footprint equal to the die-size, with standard lead layout• Fast turnaround for processing new dies• Flexible manufacturing process reduces redesign and retooling times• Ease of assembly using conventional SMT soldering techniques• Low parasitic impedance -- short leads minimise parasitic capacitance and inductance• Excellent thermal dissipation• Low cost

This manufacturing paradigm offers a standards-based extension of existing IC Semiconductor processes to Chip ScalePackaging. At the time of the packaging process, the dies are packaged and encapsulated into separate enclosures whilestill in wafer form. Metallic leads are attached to the individual contact pads by a non bonding method, and the wafersingulation yields finished packaged devices. (see Fig. 16)

FUSE 27436 Rev. 1 15.02.00 26

Fig. 16 Basic steps in CSP wafer-level manufacturing process

In Fig. 17 a cross sectional view of the opto-package shows a thin silicon substrate which is sandwiched between twothin protective plates on the top and bottom sides. An epoxy adhesive layer attaches the entire assembly, protecting theedges of the silicon die. Electrical leads connect to the pads of the die to the solder bumps by a non-bonding technique.

die of the OptoASIC

Printed Circuit Board of the SMCB

Fig. 17 CSP device on PCB

Since the CMOS Sensor performance achieved are good and suitable for the new product next steps for industrialisationare as follows:

• Realization of the CSP package. To be notice that the OptoASIC has been designed suitable for this kind ofpackaging technique and thus is not required new mask for the industrialisation.

• Realization of plastic housing and optical components of the Scanning Module• Tooling and Start-up for the volume production

The beginning of the production for selling of the Scanning Module will be on July 2000.To complete the industrialization of the Scanning Module with the new technology the investments necessary are asfollows:

Industrialization costs (KEURO)Molds and Tooling for Scanning Module 41NRE and Tooling for CSP package 38PCB and prototypes 11Personnel 24TOTAL 114

The beginning of the production for selling of the Scanning Module will be on July 2000 following the time scheduleshown below:

Industrialization time schedule Dead LineMolds and Tooling for Scanning Module April 2000Tooling for CSP package April 2000Engineering Samples of the SM May 2000Certification of the SM June 2000Beginning of the production July 2000

The new device will also be incorporated into entry-level scanner for unattended systems and scan engines to be used inportable data collection.

16. Economic impact and improvement in competitive positionWith the new technology FU expects to improve the competitive position on the “CCD readers” market takingadvantage from the cost reduction and improved features achieved. Since the Smart CMOS linear sensor, result of theAE, is a image capture device with similar functionality of a linear CCD plus additional interesting features, starting from

FUSE 27436 Rev. 1 15.02.00 27

the third quarter of 2000 FU may apply the new technology in many actual products at present based on linear CCDdevices (see Scanning Module in Cap. 15).The cost per unit comparison between current and new technology is shown in the following table:

Cost per unit comparison(EURO)

Current product(CCD technology)

Scanning Module(new technology)

CCD+BiCMOS ASIC+Circuitry 13.5 -BRAHMS Smart CMOS sensor - 10.5Lens + Illuminator 9.5 5Mirrors + plastic Housing - 2Total 23 17.5

If you consider only the benefit allowed by the introduction of OptoASIC (see Fig. 11) the cost reduction is around 3EURO, thus lower than expected (see chapter 4) because of the extra chip area usage and additional packaging costs. Butif you consider in addition the cost saving related to the new optical assembly instead of the architecture of the currentCCD readers, the total cost reduction becomes really interesting and may be estimated in 5.5 EURO per unit (24% ofcost reduction).

Today the DL main distribution channel, in Europe, is based on the indirect sales network. During the last three year themedium price of the entry level CCD technology, such as the DLC6065, has been dramatically decreased, more than ithas been supposed. Due to the extremely low cost needed, today the new technology offered by the AE application, wename AE-NT, seem to be not applying anymore to the Entry Level CCD readers, like the DLC6065. For this class ofproduct DL is developing a new CCD reader having very low price and reduced features aligned with marketrequirements.

In the last year, Datalogic announced a new class of reader, the Long Range CCD-Gun, based on the same hardwarearchitecture of the entry Level reader, with an added value on reading features. The different performances allow thiskind of reader to keep an higher medium price in the market arena. Thus, thank to higher price positioning, this new CCD-Gun could take advantage by the AE-NT. The drawing below shows medium price trend and new technology costestimation while the AE was in progress.

M e d i u m P r i c e

T i m e

E n t r y L e v e l C C D( D L C 6 0 6 5 l i k e )

C C D - G U N L o n g R a n g e( D L C 7 0 7 0 l i k e )

E n t r y L e v e l C C D( D L C 6 0 6 5 + A E )

C C D - G U N L o n g R a n g e( D L C 7 0 7 0 + A E )

T o d a yS t a r t o f t h e A E

Fig. 18 Price trend (dotted line) and cost estimation (solid line)

In addition, thanks to the unmatched compactness reachable with the AE-NT adoption, alongside the Long Range CCD-GUN, that is strictly related to an existing product, FU can apply the SM as “scanning engines” in PDC products andlow cost fixed position readers.An important features of the SM is that it was designed to have the same size of a widely used OEM Laser scanningmodule manufactured by a FU’s competitor. Thus, in some application field the new SM could find a new marketreplacing the competitor’s Laser module. In conclusion the AE-NT will be used in for future “CCD-GUN”, in PDC andUSS products and as OEM module.

FUSE 27436 Rev. 1 15.02.00 28

European market of CCD readers 1996 1997 1998 1999 2000Turnover of (KEURO) 48000 56640 66835 78866 93061Average price 261 232 207 184 164Number of product sold 183908 243833 323284 428624 568288

(VDC 1997)

Since the European market analysis of hand held CCD readers indicates an annual revenue growth in the range of 15-20%and considering the pricing advantage coming from the introduction of the AE-NT, FU expects to rise up his marketshare in the CCD-GUN segment. Considering that in the 1999 has been sold about 24Kunits of DLC7070 and at the thirdquarter of 2000 FU will introduce the new technology with a beneficial cost reduction. Adding the increased functionalityand performance, the expected sales figures with and without the AE-NT is as shown in the following table:

2000 2001 2002 2003Turnover without AE-NT (KEURO) 5433 5530 5429 4825CCD Gun (current product)Average price (EURO) 194,0 184 175 166Number of products sold 28000 30000 31000 29000

Total Turnover with AE-NT (KEURO) 5507 6573 7454 8529CCD Gun (before the AE-NT introduction)Average price (EURO) 194Number of products sold 14000AE-NT GunAverage price (EURO) 184 175 166 158Number of products sold 15000 37000 44000 53000OEM module (using AE-NT)Average revenue (EURO) 75 70 67 62Number of unit sold 400 1500 2200 2700

PDC/USS product (placing the new SM)Cost saving using AE-NT (KEURO) 4 12 15 19Number of unit sold 800 2200 2800 3400

Different Turnover (KEURO) 73 1043 2025 3704Total Cost saving using AE-NT (KEURO) 4 12 15 19Increase in profitability (12%) (KEURO) 13 137 258 463

Fig. 19 Turnover comparison with and without the AE-NT

Return of investment.An average value of the net profit for this kind of product is of about 12% of the incoming share (turnover). On this basisthe increase of profitability and the ROI have been evaluated as follows:

Return of investment (FUSE cost only)Total increase in profitability (KEURO) 872AE cost covered by FUSE (KEURO) 153.9

0

2000

4000

6000

8000

10000

Turnover (KEURO)

2000 2001 2002 2003

Turnover Comparison

Current Product

With AE-NT

FUSE 27436 Rev. 1 15.02.00 29

ROI 567%

Total Return of investmentTotal increase in profitability (KEURO) 872AE FUSE cost (KEURO) 153.9Industrialisation cost (KEURO) 114ROI 326%

Payback period of FUSE investment.The increase in profitability equals the AE total cost after about 24 months.

Fig. 20 Increase in profitability with the AE-NT and payback period

17. Added value to the portfolio and target audienceThe Opto-ASIC, developed in the project, integrates the image capture sensor and the electronics in a single chip. Thenew device allows the realisation of a new small size optical module to be used in many barcode reading applications asin Long Range Barcode readers.With the microsystem technology, it is possible the development of a variety of physical functions jointed with analogueand digital microelectronics functions so as to obtain higher performances, in little space and with low consumption andlittle recurrent costs.Many companies have the need to apply these new technologies to maintain their market share, but technical andeconomical barriers oppose a strong resistance.The replication power of this AE could be applied in at least the following product sectors:

Sectors ProdComRationale

Office MachineryComputers and Other InformationProcessing Equipment

3002 The microsystem technology allows the development ofvarious Smart optical peripherals for Computers.

Electric EquipmentInsulated Wire and Cable 3130 The Opto-ASIC could be a good “cable end interface” able to

signal receiving, processing and conditioning.

Precision InstrumentInstrument and appliance for measuring

Industrial Process Control Equipment

Optical Instruments and PhotographicEquipment

3320

3330

3340

Thanks to the Opto-ASIC it is possible to achieve the followingadvantages:• high accuracy, linearity and measurement repeatability• much better reliability thanks to the single chip solution• cost saving – thanks to reduction of components,

decreased testing and manufacturing time

Payback period

-200,0-100,0

0,0100,0200,0300,0400,0500,0600,0700,0800,0

0 12 24 36 48

months

Incr

emen

tal p

rofi

t (K

EU

RO

)

FUSE 27436 Rev. 1 15.02.00 30

• confidentiality: it is possible to protect the know-how

The project demonstrates the advantages in replacing the present version of the barcode readers (a CCD linear sensorand a PCB with electronics) by means of a single Opto-ASIC.

As a microsystem the result of this AE has all the advantages of a monolithic compact component. These advantages are the reasons for a wide target audience:

• Design - integrated optical adjustment• Rugged and compact.• Low production costs• High quality design• Reduction of external components needed

The small outer dimensions and low weight of the sensor allows it to be used for:• Hand-held applications• Stationary applications with limited space availability.

Many Companies, operating in Automatic Identification Technology, Data Capturing and Communication electronicsshould be interested to replicate the Datalogic experience.

From the company profile point of view, all the companies matching with the Datalogic profile should be interested inacquiring experience from this AE. This AE implies a good power for local replication because in TTN region there areother industrial districts such as that where Datalogic is operating. The typical electronic companies that design andsupply electronic inductive sensors are mainly featured on this mask:

Management: Ready to keep up with advanced technologies but with little skillStarting technology: µC, FPGA, ASIC

Applications: Automatic Identification Technology, Data Capturing and CommunicationDevelopment Methodology: Analogue and digital technique

Barriers: Economical worries and cost overestimation with time to market problemsCompany Size: Medium companies

Company turnover: Bigger than 15.0 MEuro

What resulted is that the actual added value of this project in front of the existing portfolio within the FUSE Project isreally high, referring to its following features:

• Company size: discard• Industrial sector: all• Starting technology: FPGA, ASIC• New technology: MST• Key-words: Barcode reader

FUSE 27436 Rev. 1 15.02.00 31

Contents

AE abstract..............................................................................................................................................................................................21. Company name and address.........................................................................................................................................................22. Company size .................................................................................................................................................................................33. ompany business description ......................................................................................................................................................4

HHD - Hand-Held Devices ................................................................................................................................................................4USS - Unattended Scanning Systems .............................................................................................................................................4PDC – Portable Data Collection........................................................................................................................................................5

4. Company markets and competitive position at the start of the AE.......................................................................................65. Product to be improved and its industrial sectors ...................................................................................................................86. Description of the technical product improvements ............................................................................................................ 107. Choices and rationale for the technologies, tools and methodologies .............................................................................. 138. Expertise and experience in microelectronics of the company and the staff allocated to the project......................... 149. Workplan and rationale............................................................................................................................................................ 1510. Subcontractor information.................................................................................................................................................. 2011. Barriers................................................................................................................................................................................... 2112. Steps taken to overcome the barriers and arrive at an improved product or process ............................................. 2113. Knowledge and experience acquired................................................................................................................................... 2214. Lessons Learned.................................................................................................................................................................... 2315. Resulting product or process, its industrialisation and internal replication............................................................. 2416. Economic impact and improvement in competitive position........................................................................................... 2617. Added value to the portfolio and target audience.............................................................................................................. 28